1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK 3 4--- | 5 define i32 @test_icmp_eq_i8(i8 %a, i8 %b) { 6 %r = icmp eq i8 %a, %b 7 %res = zext i1 %r to i32 8 ret i32 %res 9 } 10 11 define i32 @test_icmp_eq_i16(i16 %a, i16 %b) { 12 %r = icmp eq i16 %a, %b 13 %res = zext i1 %r to i32 14 ret i32 %res 15 } 16 17 define i32 @test_icmp_eq_i64(i64 %a, i64 %b) { 18 %r = icmp eq i64 %a, %b 19 %res = zext i1 %r to i32 20 ret i32 %res 21 } 22 23 define i32 @test_icmp_eq_i32(i32 %a, i32 %b) { 24 %r = icmp eq i32 %a, %b 25 %res = zext i1 %r to i32 26 ret i32 %res 27 } 28 29 define i32 @test_icmp_ne_i32(i32 %a, i32 %b) { 30 %r = icmp ne i32 %a, %b 31 %res = zext i1 %r to i32 32 ret i32 %res 33 } 34 35 define i32 @test_icmp_ugt_i32(i32 %a, i32 %b) { 36 %r = icmp ugt i32 %a, %b 37 %res = zext i1 %r to i32 38 ret i32 %res 39 } 40 41 define i32 @test_icmp_uge_i32(i32 %a, i32 %b) { 42 %r = icmp uge i32 %a, %b 43 %res = zext i1 %r to i32 44 ret i32 %res 45 } 46 47 define i32 @test_icmp_ult_i32(i32 %a, i32 %b) { 48 %r = icmp ult i32 %a, %b 49 %res = zext i1 %r to i32 50 ret i32 %res 51 } 52 53 define i32 @test_icmp_ule_i32(i32 %a, i32 %b) { 54 %r = icmp ule i32 %a, %b 55 %res = zext i1 %r to i32 56 ret i32 %res 57 } 58 59 define i32 @test_icmp_sgt_i32(i32 %a, i32 %b) { 60 %r = icmp sgt i32 %a, %b 61 %res = zext i1 %r to i32 62 ret i32 %res 63 } 64 65 define i32 @test_icmp_sge_i32(i32 %a, i32 %b) { 66 %r = icmp sge i32 %a, %b 67 %res = zext i1 %r to i32 68 ret i32 %res 69 } 70 71 define i32 @test_icmp_slt_i32(i32 %a, i32 %b) { 72 %r = icmp slt i32 %a, %b 73 %res = zext i1 %r to i32 74 ret i32 %res 75 } 76 77 define i32 @test_icmp_sle_i32(i32 %a, i32 %b) { 78 %r = icmp sle i32 %a, %b 79 %res = zext i1 %r to i32 80 ret i32 %res 81 } 82 83... 84--- 85name: test_icmp_eq_i8 86alignment: 4 87legalized: true 88regBankSelected: true 89registers: 90 - { id: 0, class: gpr } 91 - { id: 1, class: gpr } 92 - { id: 2, class: gpr } 93 - { id: 3, class: gpr } 94body: | 95 bb.1 (%ir-block.0): 96 liveins: $edi, $esi 97 98 ; CHECK-LABEL: name: test_icmp_eq_i8 99 ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $dil 100 ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil 101 ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags 102 ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags 103 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit 104 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 105 ; CHECK: $eax = COPY [[AND32ri8_]] 106 ; CHECK: RET 0, implicit $eax 107 %0(s8) = COPY $dil 108 %1(s8) = COPY $sil 109 %2(s1) = G_ICMP intpred(eq), %0(s8), %1 110 %3(s32) = G_ZEXT %2(s1) 111 $eax = COPY %3(s32) 112 RET 0, implicit $eax 113 114... 115--- 116name: test_icmp_eq_i16 117alignment: 4 118legalized: true 119regBankSelected: true 120registers: 121 - { id: 0, class: gpr } 122 - { id: 1, class: gpr } 123 - { id: 2, class: gpr } 124 - { id: 3, class: gpr } 125body: | 126 bb.1 (%ir-block.0): 127 liveins: $edi, $esi 128 129 ; CHECK-LABEL: name: test_icmp_eq_i16 130 ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $di 131 ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si 132 ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags 133 ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags 134 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit 135 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 136 ; CHECK: $eax = COPY [[AND32ri8_]] 137 ; CHECK: RET 0, implicit $eax 138 %0(s16) = COPY $di 139 %1(s16) = COPY $si 140 %2(s1) = G_ICMP intpred(eq), %0(s16), %1 141 %3(s32) = G_ZEXT %2(s1) 142 $eax = COPY %3(s32) 143 RET 0, implicit $eax 144 145... 146--- 147name: test_icmp_eq_i64 148alignment: 4 149legalized: true 150regBankSelected: true 151registers: 152 - { id: 0, class: gpr } 153 - { id: 1, class: gpr } 154 - { id: 2, class: gpr } 155 - { id: 3, class: gpr } 156body: | 157 bb.1 (%ir-block.0): 158 liveins: $rdi, $rsi 159 160 ; CHECK-LABEL: name: test_icmp_eq_i64 161 ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 162 ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi 163 ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags 164 ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags 165 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit 166 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 167 ; CHECK: $eax = COPY [[AND32ri8_]] 168 ; CHECK: RET 0, implicit $eax 169 %0(s64) = COPY $rdi 170 %1(s64) = COPY $rsi 171 %2(s1) = G_ICMP intpred(eq), %0(s64), %1 172 %3(s32) = G_ZEXT %2(s1) 173 $eax = COPY %3(s32) 174 RET 0, implicit $eax 175 176... 177--- 178name: test_icmp_eq_i32 179alignment: 4 180legalized: true 181regBankSelected: true 182registers: 183 - { id: 0, class: gpr } 184 - { id: 1, class: gpr } 185 - { id: 2, class: gpr } 186 - { id: 3, class: gpr } 187body: | 188 bb.1 (%ir-block.0): 189 liveins: $edi, $esi 190 191 ; CHECK-LABEL: name: test_icmp_eq_i32 192 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 193 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 194 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 195 ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags 196 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit 197 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 198 ; CHECK: $eax = COPY [[AND32ri8_]] 199 ; CHECK: RET 0, implicit $eax 200 %0(s32) = COPY $edi 201 %1(s32) = COPY $esi 202 %2(s1) = G_ICMP intpred(eq), %0(s32), %1 203 %3(s32) = G_ZEXT %2(s1) 204 $eax = COPY %3(s32) 205 RET 0, implicit $eax 206 207... 208--- 209name: test_icmp_ne_i32 210alignment: 4 211legalized: true 212regBankSelected: true 213registers: 214 - { id: 0, class: gpr } 215 - { id: 1, class: gpr } 216 - { id: 2, class: gpr } 217 - { id: 3, class: gpr } 218body: | 219 bb.1 (%ir-block.0): 220 liveins: $edi, $esi 221 222 ; CHECK-LABEL: name: test_icmp_ne_i32 223 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 224 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 225 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 226 ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit $eflags 227 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], %subreg.sub_8bit 228 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 229 ; CHECK: $eax = COPY [[AND32ri8_]] 230 ; CHECK: RET 0, implicit $eax 231 %0(s32) = COPY $edi 232 %1(s32) = COPY $esi 233 %2(s1) = G_ICMP intpred(ne), %0(s32), %1 234 %3(s32) = G_ZEXT %2(s1) 235 $eax = COPY %3(s32) 236 RET 0, implicit $eax 237 238... 239--- 240name: test_icmp_ugt_i32 241alignment: 4 242legalized: true 243regBankSelected: true 244registers: 245 - { id: 0, class: gpr } 246 - { id: 1, class: gpr } 247 - { id: 2, class: gpr } 248 - { id: 3, class: gpr } 249body: | 250 bb.1 (%ir-block.0): 251 liveins: $edi, $esi 252 253 ; CHECK-LABEL: name: test_icmp_ugt_i32 254 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 255 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 256 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 257 ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags 258 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], %subreg.sub_8bit 259 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 260 ; CHECK: $eax = COPY [[AND32ri8_]] 261 ; CHECK: RET 0, implicit $eax 262 %0(s32) = COPY $edi 263 %1(s32) = COPY $esi 264 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1 265 %3(s32) = G_ZEXT %2(s1) 266 $eax = COPY %3(s32) 267 RET 0, implicit $eax 268 269... 270--- 271name: test_icmp_uge_i32 272alignment: 4 273legalized: true 274regBankSelected: true 275registers: 276 - { id: 0, class: gpr } 277 - { id: 1, class: gpr } 278 - { id: 2, class: gpr } 279 - { id: 3, class: gpr } 280body: | 281 bb.1 (%ir-block.0): 282 liveins: $edi, $esi 283 284 ; CHECK-LABEL: name: test_icmp_uge_i32 285 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 286 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 287 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 288 ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit $eflags 289 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAEr]], %subreg.sub_8bit 290 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 291 ; CHECK: $eax = COPY [[AND32ri8_]] 292 ; CHECK: RET 0, implicit $eax 293 %0(s32) = COPY $edi 294 %1(s32) = COPY $esi 295 %2(s1) = G_ICMP intpred(uge), %0(s32), %1 296 %3(s32) = G_ZEXT %2(s1) 297 $eax = COPY %3(s32) 298 RET 0, implicit $eax 299 300... 301--- 302name: test_icmp_ult_i32 303alignment: 4 304legalized: true 305regBankSelected: true 306registers: 307 - { id: 0, class: gpr } 308 - { id: 1, class: gpr } 309 - { id: 2, class: gpr } 310 - { id: 3, class: gpr } 311body: | 312 bb.1 (%ir-block.0): 313 liveins: $edi, $esi 314 315 ; CHECK-LABEL: name: test_icmp_ult_i32 316 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 317 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 318 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 319 ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit $eflags 320 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBr]], %subreg.sub_8bit 321 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 322 ; CHECK: $eax = COPY [[AND32ri8_]] 323 ; CHECK: RET 0, implicit $eax 324 %0(s32) = COPY $edi 325 %1(s32) = COPY $esi 326 %2(s1) = G_ICMP intpred(ult), %0(s32), %1 327 %3(s32) = G_ZEXT %2(s1) 328 $eax = COPY %3(s32) 329 RET 0, implicit $eax 330 331... 332--- 333name: test_icmp_ule_i32 334alignment: 4 335legalized: true 336regBankSelected: true 337registers: 338 - { id: 0, class: gpr } 339 - { id: 1, class: gpr } 340 - { id: 2, class: gpr } 341 - { id: 3, class: gpr } 342body: | 343 bb.1 (%ir-block.0): 344 liveins: $edi, $esi 345 346 ; CHECK-LABEL: name: test_icmp_ule_i32 347 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 348 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 349 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 350 ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit $eflags 351 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBEr]], %subreg.sub_8bit 352 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 353 ; CHECK: $eax = COPY [[AND32ri8_]] 354 ; CHECK: RET 0, implicit $eax 355 %0(s32) = COPY $edi 356 %1(s32) = COPY $esi 357 %2(s1) = G_ICMP intpred(ule), %0(s32), %1 358 %3(s32) = G_ZEXT %2(s1) 359 $eax = COPY %3(s32) 360 RET 0, implicit $eax 361 362... 363--- 364name: test_icmp_sgt_i32 365alignment: 4 366legalized: true 367regBankSelected: true 368registers: 369 - { id: 0, class: gpr } 370 - { id: 1, class: gpr } 371 - { id: 2, class: gpr } 372 - { id: 3, class: gpr } 373body: | 374 bb.1 (%ir-block.0): 375 liveins: $edi, $esi 376 377 ; CHECK-LABEL: name: test_icmp_sgt_i32 378 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 379 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 380 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 381 ; CHECK: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags 382 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGr]], %subreg.sub_8bit 383 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 384 ; CHECK: $eax = COPY [[AND32ri8_]] 385 ; CHECK: RET 0, implicit $eax 386 %0(s32) = COPY $edi 387 %1(s32) = COPY $esi 388 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1 389 %3(s32) = G_ZEXT %2(s1) 390 $eax = COPY %3(s32) 391 RET 0, implicit $eax 392 393... 394--- 395name: test_icmp_sge_i32 396alignment: 4 397legalized: true 398regBankSelected: true 399registers: 400 - { id: 0, class: gpr } 401 - { id: 1, class: gpr } 402 - { id: 2, class: gpr } 403 - { id: 3, class: gpr } 404body: | 405 bb.1 (%ir-block.0): 406 liveins: $edi, $esi 407 408 ; CHECK-LABEL: name: test_icmp_sge_i32 409 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 410 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 411 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 412 ; CHECK: [[SETGEr:%[0-9]+]]:gr8 = SETGEr implicit $eflags 413 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGEr]], %subreg.sub_8bit 414 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 415 ; CHECK: $eax = COPY [[AND32ri8_]] 416 ; CHECK: RET 0, implicit $eax 417 %0(s32) = COPY $edi 418 %1(s32) = COPY $esi 419 %2(s1) = G_ICMP intpred(sge), %0(s32), %1 420 %3(s32) = G_ZEXT %2(s1) 421 $eax = COPY %3(s32) 422 RET 0, implicit $eax 423 424... 425--- 426name: test_icmp_slt_i32 427alignment: 4 428legalized: true 429regBankSelected: true 430registers: 431 - { id: 0, class: gpr } 432 - { id: 1, class: gpr } 433 - { id: 2, class: gpr } 434 - { id: 3, class: gpr } 435body: | 436 bb.1 (%ir-block.0): 437 liveins: $edi, $esi 438 439 ; CHECK-LABEL: name: test_icmp_slt_i32 440 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 441 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 442 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 443 ; CHECK: [[SETLr:%[0-9]+]]:gr8 = SETLr implicit $eflags 444 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLr]], %subreg.sub_8bit 445 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 446 ; CHECK: $eax = COPY [[AND32ri8_]] 447 ; CHECK: RET 0, implicit $eax 448 %0(s32) = COPY $edi 449 %1(s32) = COPY $esi 450 %2(s1) = G_ICMP intpred(slt), %0(s32), %1 451 %3(s32) = G_ZEXT %2(s1) 452 $eax = COPY %3(s32) 453 RET 0, implicit $eax 454 455... 456--- 457name: test_icmp_sle_i32 458alignment: 4 459legalized: true 460regBankSelected: true 461registers: 462 - { id: 0, class: gpr } 463 - { id: 1, class: gpr } 464 - { id: 2, class: gpr } 465 - { id: 3, class: gpr } 466body: | 467 bb.1 (%ir-block.0): 468 liveins: $edi, $esi 469 470 ; CHECK-LABEL: name: test_icmp_sle_i32 471 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 472 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 473 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 474 ; CHECK: [[SETLEr:%[0-9]+]]:gr8 = SETLEr implicit $eflags 475 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLEr]], %subreg.sub_8bit 476 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 477 ; CHECK: $eax = COPY [[AND32ri8_]] 478 ; CHECK: RET 0, implicit $eax 479 %0(s32) = COPY $edi 480 %1(s32) = COPY $esi 481 %2(s1) = G_ICMP intpred(sle), %0(s32), %1 482 %3(s32) = G_ZEXT %2(s1) 483 $eax = COPY %3(s32) 484 RET 0, implicit $eax 485 486... 487