1; RUN: llc < %s -mtriple=i386 -mcpu=pentium4 | FileCheck %s
2; RUN: llc < %s -mtriple=i386 -mcpu=pentium4m | FileCheck %s
3; RUN: llc < %s -mtriple=i386 -mcpu=pentium-m | FileCheck %s
4; RUN: llc < %s -mtriple=i386 -mcpu=prescott | FileCheck %s
5; RUN: llc < %s -mtriple=i386 -mcpu=nocona | FileCheck %s
6;
7; Verify that scheduling puts some distance between a load feeding into
8; the address of another load, and that second load.  This currently
9; happens during the post-RA-scheduler, which should be enabled by
10; default with the above specified cpus.
11
12@ptrs = external global [0 x i32*], align 4
13@idxa = common global i32 0, align 4
14@idxb = common global i32 0, align 4
15@res = common global i32 0, align 4
16
17define void @addindirect() {
18; CHECK-LABEL: addindirect:
19; CHECK:       # %bb.0: # %entry
20; CHECK-NEXT:    movl idxb, %ecx
21; CHECK-NEXT:    movl idxa, %eax
22; CHECK-NEXT:    movl ptrs(,%ecx,4), %ecx
23; CHECK-NEXT:    movl ptrs(,%eax,4), %eax
24; CHECK-NEXT:    movl (%ecx), %ecx
25; CHECK-NEXT:    addl (%eax), %ecx
26; CHECK-NEXT:    movl %ecx, res
27; CHECK-NEXT:    retl
28entry:
29  %0 = load i32, i32* @idxa, align 4
30  %arrayidx = getelementptr inbounds [0 x i32*], [0 x i32*]* @ptrs, i32 0, i32 %0
31  %1 = load i32*, i32** %arrayidx, align 4
32  %2 = load i32, i32* %1, align 4
33  %3 = load i32, i32* @idxb, align 4
34  %arrayidx1 = getelementptr inbounds [0 x i32*], [0 x i32*]* @ptrs, i32 0, i32 %3
35  %4 = load i32*, i32** %arrayidx1, align 4
36  %5 = load i32, i32* %4, align 4
37  %add = add i32 %5, %2
38  store i32 %add, i32* @res, align 4
39  ret void
40}
41