1# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=+micromips,+eva 2>%t1 2# RUN: FileCheck %s < %t1 3 4 addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4 5 addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 8 addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 11 addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate 13 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate 14 beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 15 beqzc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 16 beqzc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 17 bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 18 bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 19 bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 20 break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 21 break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 22 break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 23 break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 24 break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate 25 break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate 26 break 1023, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate 27 cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate 28 cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate 29 # FIXME: Check '0 < pos + size <= 32' constraint on ext 30 ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 31 ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 32 ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 33 ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 34 ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 35 ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 36 ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number 37 swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid register number 38 swe $5, 8($34) # CHECK: :[[@LINE]]:13: error: invalid register number 39 swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 40 lapc $7, 1048576 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4 41 lapc $6, -1048580 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4 42 lapc $3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4 43 lapc $3, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4 44 lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 45 lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 46 lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 47 lbu16 $16, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 48 lhu16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 49 lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 50 lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 51 lhu16 $16, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 52 li16 $4, -2 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126 53 li16 $4, 127 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126 54 lsa $4, $2, $3, 0 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 4 55 lsa $4, $2, $3, 5 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 4 56 lw16 $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 57 lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 58 lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 59 lw16 $17, 8($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 60 pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate 61 pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate 62 teq $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number 63 teq $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number 64 tge $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number 65 tge $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number 66 tgeu $34, $9, 5 # CHECK: :[[@LINE]]:8: error: invalid register number 67 tgeu $8, $35, 6 # CHECK: :[[@LINE]]:12: error: invalid register number 68 tlt $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number 69 tlt $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number 70 tltu $34, $9, 5 # CHECK: :[[@LINE]]:8: error: invalid register number 71 tltu $8, $35, 6 # CHECK: :[[@LINE]]:12: error: invalid register number 72 tne $34, $9, 5 # CHECK: :[[@LINE]]:7: error: invalid register number 73 tne $8, $35, 6 # CHECK: :[[@LINE]]:11: error: invalid register number 74 wait -1 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate 75 wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate 76 wrpgpr $34, $4 # CHECK: :[[@LINE]]:10: error: invalid register number 77 wrpgpr $3, $33 # CHECK: :[[@LINE]]:14: error: invalid register number 78 wsbh $34, $4 # CHECK: :[[@LINE]]:8: error: invalid register number 79 wsbh $3, $33 # CHECK: :[[@LINE]]:12: error: invalid register number 80 jrcaddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 81 jrcaddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 82 jrcaddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 83 jrcaddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 84 jrcaddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 85 jrcaddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 86 jrcaddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 87 jrcaddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 88 jrcaddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 89 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected 90 lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected 91 lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 92 lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 93 lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 94 lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 95 lwm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 96 lwm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 97 sb16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 98 sb16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 99 sb16 $16, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 100 sb16 $7, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 101 sh16 $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 102 sh16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 103 sh16 $16, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 104 sh16 $7, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 105 sync -1 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate 106 sync 32 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate 107 sw16 $9, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 108 sw16 $4, 64($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 109 sw16 $16, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 110 sw16 $7, 4($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 111 swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected 112 swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected 113 swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 114 swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 115 swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 116 swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 117 swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 118 swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 119 mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 120 mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 121 mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 122 mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 123 mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 124 mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 125 mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 126 mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 127 tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 128 tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 129 tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 130 tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 131 tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 132 tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 133 tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 134 tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 135 tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 136 tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 137 tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 138 tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 139 dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 140 dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 141 evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 142 evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 143 jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 144 jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 145 sll $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 146 sll $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 147 sra $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 148 sra $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 149 srl $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 150 srl $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 151 sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 152 sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 153 sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 154 sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 155 srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 156 srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 157 ll $33, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number 158 ll $4, 8($33) # CHECK: :[[@LINE]]:12: error: invalid register number 159 ll $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 160 ll $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 161 lle $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number 162 lle $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number 163 lle $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 164 lle $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 165 lwe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number 166 lwe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number 167 lwe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 168 lwe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 169 sbe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number 170 sbe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number 171 sbe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 172 sbe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 173 sc $33, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number 174 sc $4, 8($33) # CHECK: :[[@LINE]]:12: error: invalid register number 175 sc $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 176 sc $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 177 sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number 178 sce $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number 179 sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 180 sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 181 she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number 182 she $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number 183 she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 184 she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 185 swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 186 lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number 187 lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number 188 lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number 189 lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number 190 lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number 191 lhe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number 192 lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number 193 lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number 194 lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset 195 lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset 196 lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 197 lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 198 lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset 199 lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset 200 lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 201 lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 202 lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected 203 lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected 204 lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 205 lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 206 movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 207 movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 208 movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 209 movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 210 rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate 211 rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate 212 rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate 213 rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate 214 rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 215 swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected 216 swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected 217 swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 218 lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 219 # FIXME: This ought to point at the $34 but memory is treated as one operand. 220 lwp $16, 8($34) # CHECK: :[[@LINE]]:14: error: invalid register number 221 lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset 222 lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 223 swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 224 swp $16, 8($34) # CHECK: :[[@LINE]]:14: error: invalid register number 225 swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset 226 # bposge32 is microMIPS DSP instruction 227 bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 228 bc1eqzc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 229 bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 230 bc1eqzc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 231 bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 232 bc1eqzc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 233 bc1nezc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 234 bc1nezc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 235 bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 236 bc1nezc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 237 bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 238 bc2eqzc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid register number 239 bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 240 bc2eqzc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 241 bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 242 bc2eqzc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 243 bc2nezc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid register number 244 bc2nezc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 245 bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 246 bc2nezc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 247 bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 248 jalrc $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 249 jalrc $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 250 andi $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate 251 andi $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate 252 andi $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate 253 andi $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate 254 ori $3, $4, -1 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate 255 ori $3, $4, 65536 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate 256 ori $3, -1 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate 257 ori $3, 65536 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate 258 xori $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate 259 xori $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate 260 xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate 261 xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate 262 not $3, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 263 lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number 264 lb $4, -2147483649($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset 265 lb $4, 2147483648($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset 266 lb $4, 8($32) # CHECK: :[[@LINE]]:12: error: invalid register number 267 lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number 268 lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset 269 lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset 270 lbu $4, 8($32) # CHECK: :[[@LINE]]:13: error: invalid register number 271 ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 272 ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 273 ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 274 ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:17: error: invalid register number 275 sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 276 sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 277 sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 278 sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:16: error: invalid register number 279 lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 280 lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 281 lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 282 lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:16: error: invalid register number 283 swc1 $f32, 369($13) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 284 swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 285 swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 286 swc1 $f6, 369($32) # CHECK: :[[@LINE]]:17: error: invalid register number 287 ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:8: error: invalid register number 288 sdc2 $32, 8($16) # CHECK: :[[@LINE]]:8: error: invalid register number 289 lwc2 $32, 16($4) # CHECK: :[[@LINE]]:8: error: invalid register number 290 swc2 $32, 777($17) # CHECK: :[[@LINE]]:8: error: invalid register number 291 sdc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 292 sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 293 swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 294 swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 295 bgec $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 296 bgec $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 297 bgec $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 298 bgec $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 299 bgec $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 300 bgec $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 301 bltc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 302 bltc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 303 bltc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 304 bltc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 305 bltc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 306 bltc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 307 bgeuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 308 bgeuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 309 bgeuc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 310 bgeuc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 311 bgeuc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 312 bgeuc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 313 bltuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 314 bltuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 315 bltuc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 316 bltuc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 317 bltuc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 318 bltuc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 319 beqc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 320 beqc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 321 beqc $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 322 beqc $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 323 beqc $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 324 beqc $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 325 bnec $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 326 bnec $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 327 bnec $2, $4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 328 bnec $2, $4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 329 bnec $2, $4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 330 bnec $2, $4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 331 blezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 332 blezc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 333 blezc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 334 blezc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 335 blezc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 336 bgezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 337 bgezc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 338 bgezc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 339 bgezc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 340 bgezc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 341 bgtzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 342 bgtzc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 343 bgtzc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 344 bgtzc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 345 bgtzc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 346 bltzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 347 bltzc $2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 348 bltzc $2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 349 bltzc $2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 350 bltzc $2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 351 beqzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 352 beqzc $2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 353 beqzc $2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 354 beqzc $2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 355 beqzc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 356 bnezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 357 bnezc $2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 358 bnezc $2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 359 bnezc $2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 360 bnezc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 361 teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate 362 teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate 363 tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate 364 tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate 365 tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate 366 tgeu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate 367 tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate 368 tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate 369 tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate 370 tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate 371 tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate 372 tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate 373 teqi $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 374 tgei $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 375 tgeiu $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 376 tlti $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 377 tltiu $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 378 tnei $4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 379 syscall -1 # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate 380 syscall $4 # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate 381 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:17: error: invalid register number 382 lwc2 $1, 16($32) # CHECK: :[[@LINE]]:15: error: invalid register number 383 sdc2 $1, 8($32) # CHECK: :[[@LINE]]:14: error: invalid register number 384 swc2 $1, 777($32) # CHECK: :[[@LINE]]:16: error: invalid register number 385 movn $3, $3, $4 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 386 movz $3, $3, $4 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 387 movt $4, $5, $fcc0 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 388 movf $4, $5, $fcc0 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 389 madd $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 390 maddu $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 391 msub $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 392 msubu $4, $5 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled 393