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1; RUN: opt < %s -indvars -S | FileCheck %s
2
3; Provide legal integer types.
4target datalayout = "n8:16:32:64"
5
6; CHECK-NOT: sext
7
8define i64 @test(i64* nocapture %first, i32 %count) nounwind readonly {
9entry:
10	%t0 = icmp sgt i32 %count, 0		; <i1> [#uses=1]
11	br i1 %t0, label %bb.nph, label %bb2
12
13bb.nph:		; preds = %entry
14	br label %bb
15
16bb:		; preds = %bb1, %bb.nph
17	%result.02 = phi i64 [ %t5, %bb1 ], [ 0, %bb.nph ]		; <i64> [#uses=1]
18	%n.01 = phi i32 [ %t6, %bb1 ], [ 0, %bb.nph ]		; <i32> [#uses=2]
19	%t1 = sext i32 %n.01 to i64		; <i64> [#uses=1]
20	%t2 = getelementptr i64, i64* %first, i64 %t1		; <i64*> [#uses=1]
21	%t3 = load i64, i64* %t2, align 8		; <i64> [#uses=1]
22	%t4 = lshr i64 %t3, 4		; <i64> [#uses=1]
23	%t5 = add i64 %t4, %result.02		; <i64> [#uses=2]
24	%t6 = add i32 %n.01, 1		; <i32> [#uses=2]
25	br label %bb1
26
27bb1:		; preds = %bb
28	%t7 = icmp slt i32 %t6, %count		; <i1> [#uses=1]
29	br i1 %t7, label %bb, label %bb1.bb2_crit_edge
30
31bb1.bb2_crit_edge:		; preds = %bb1
32	%.lcssa = phi i64 [ %t5, %bb1 ]		; <i64> [#uses=1]
33	br label %bb2
34
35bb2:		; preds = %bb1.bb2_crit_edge, %entry
36	%result.0.lcssa = phi i64 [ %.lcssa, %bb1.bb2_crit_edge ], [ 0, %entry ]		; <i64> [#uses=1]
37	ret i64 %result.0.lcssa
38}
39
40define void @foo(i16 signext %N, i32* nocapture %P) nounwind {
41entry:
42	%t0 = icmp sgt i16 %N, 0		; <i1> [#uses=1]
43	br i1 %t0, label %bb.nph, label %return
44
45bb.nph:		; preds = %entry
46	br label %bb
47
48bb:		; preds = %bb1, %bb.nph
49	%i.01 = phi i16 [ %t3, %bb1 ], [ 0, %bb.nph ]		; <i16> [#uses=2]
50	%t1 = sext i16 %i.01 to i64		; <i64> [#uses=1]
51	%t2 = getelementptr i32, i32* %P, i64 %t1		; <i32*> [#uses=1]
52	store i32 123, i32* %t2, align 4
53	%t3 = add i16 %i.01, 1		; <i16> [#uses=2]
54	br label %bb1
55
56bb1:		; preds = %bb
57	%t4 = icmp slt i16 %t3, %N		; <i1> [#uses=1]
58	br i1 %t4, label %bb, label %bb1.return_crit_edge
59
60bb1.return_crit_edge:		; preds = %bb1
61	br label %return
62
63return:		; preds = %bb1.return_crit_edge, %entry
64	ret void
65}
66
67; Test cases from PR1301:
68
69define void @kinds__srangezero([21 x i32]* nocapture %a) nounwind {
70bb.thread:
71  br label %bb
72
73bb:             ; preds = %bb, %bb.thread
74  %i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ]           ; <i8> [#uses=2]
75  %tmp12 = sext i8 %i.0.reg2mem.0 to i32                ; <i32> [#uses=1]
76  %tmp4 = add i32 %tmp12, 10            ; <i32> [#uses=1]
77  %tmp5 = getelementptr [21 x i32], [21 x i32]* %a, i32 0, i32 %tmp4                ; <i32*> [#uses=1]
78  store i32 0, i32* %tmp5
79  %tmp7 = add i8 %i.0.reg2mem.0, 1              ; <i8> [#uses=2]
80  %0 = icmp sgt i8 %tmp7, 10            ; <i1> [#uses=1]
81  br i1 %0, label %return, label %bb
82
83return:         ; preds = %bb
84  ret void
85}
86
87define void @kinds__urangezero([21 x i32]* nocapture %a) nounwind {
88bb.thread:
89  br label %bb
90
91bb:             ; preds = %bb, %bb.thread
92  %i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ]            ; <i8> [#uses=2]
93  %tmp12 = sext i8 %i.0.reg2mem.0 to i32                ; <i32> [#uses=1]
94  %tmp4 = add i32 %tmp12, -10           ; <i32> [#uses=1]
95  %tmp5 = getelementptr [21 x i32], [21 x i32]* %a, i32 0, i32 %tmp4                ; <i32*> [#uses=1]
96  store i32 0, i32* %tmp5
97  %tmp7 = add i8 %i.0.reg2mem.0, 1              ; <i8> [#uses=2]
98  %0 = icmp sgt i8 %tmp7, 30            ; <i1> [#uses=1]
99  br i1 %0, label %return, label %bb
100
101return:         ; preds = %bb
102  ret void
103}
104
105define void @promote_latch_condition_decrementing_loop_01(i32* %p, i32* %a) {
106
107; CHECK-LABEL: @promote_latch_condition_decrementing_loop_01(
108; CHECK-NOT:     trunc
109
110entry:
111  %len = load i32, i32* %p, align 4, !range !0
112  %len.minus.1 = add nsw i32 %len, -1
113  %zero_check = icmp eq i32 %len, 0
114  br i1 %zero_check, label %loopexit, label %preheader
115
116preheader:
117  br label %loop
118
119loopexit:
120  ret void
121
122loop:
123  %iv = phi i32 [ %iv.next, %loop ], [ %len.minus.1, %preheader ]
124  ; CHECK: %indvars.iv = phi i64
125  %iv.wide = zext i32 %iv to i64
126  %el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
127  store atomic i32 0, i32* %el unordered, align 4
128  %iv.next = add nsw i32 %iv, -1
129  ; CHECK: %loopcond = icmp slt i64 %indvars.iv, 1
130  %loopcond = icmp slt i32 %iv, 1
131  br i1 %loopcond, label %loopexit, label %loop
132}
133
134define void @promote_latch_condition_decrementing_loop_02(i32* %p, i32* %a) {
135
136; CHECK-LABEL: @promote_latch_condition_decrementing_loop_02(
137; CHECK-NOT:     trunc
138
139entry:
140  %len = load i32, i32* %p, align 4, !range !0
141  %zero_check = icmp eq i32 %len, 0
142  br i1 %zero_check, label %loopexit, label %preheader
143
144preheader:
145  br label %loop
146
147loopexit:
148  ret void
149
150loop:
151  %iv = phi i32 [ %iv.next, %loop ], [ %len, %preheader ]
152  ; CHECK: %indvars.iv = phi i64
153  %iv.wide = zext i32 %iv to i64
154  %el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
155  store atomic i32 0, i32* %el unordered, align 4
156  %iv.next = add nsw i32 %iv, -1
157  ; CHECK: %loopcond = icmp slt i64 %indvars.iv, 1
158  %loopcond = icmp slt i32 %iv, 1
159  br i1 %loopcond, label %loopexit, label %loop
160}
161
162define void @promote_latch_condition_decrementing_loop_03(i32* %p, i32* %a) {
163
164; CHECK-LABEL: @promote_latch_condition_decrementing_loop_03(
165; CHECK-NOT:     trunc
166
167entry:
168  %len = load i32, i32* %p, align 4, !range !0
169  %len.plus.1 = add i32 %len, 1
170  %zero_check = icmp eq i32 %len, 0
171  br i1 %zero_check, label %loopexit, label %preheader
172
173preheader:
174  br label %loop
175
176loopexit:
177  ret void
178
179loop:
180  %iv = phi i32 [ %iv.next, %loop ], [ %len.plus.1, %preheader ]
181  ; CHECK: %indvars.iv = phi i64
182  %iv.wide = zext i32 %iv to i64
183  %el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
184  store atomic i32 0, i32* %el unordered, align 4
185  %iv.next = add nsw i32 %iv, -1
186  ; CHECK: %loopcond = icmp slt i64 %indvars.iv, 1
187  %loopcond = icmp slt i32 %iv, 1
188  br i1 %loopcond, label %loopexit, label %loop
189}
190
191define void @promote_latch_condition_decrementing_loop_04(i32* %p, i32* %a, i1 %cond) {
192
193; CHECK-LABEL: @promote_latch_condition_decrementing_loop_04(
194; CHECK-NOT:     trunc
195
196entry:
197  %len = load i32, i32* %p, align 4, !range !0
198  %len.minus.1 = add nsw i32 %len, -1
199  br i1 %cond, label %if.true, label %if.false
200
201if.true:
202  br label %merge
203
204if.false:
205  br label %merge
206
207merge:
208  %iv_start = phi i32 [ %len, %if.true ], [%len.minus.1, %if.false ]
209  %zero_check = icmp eq i32 %len, 0
210  br i1 %zero_check, label %loopexit, label %preheader
211
212preheader:
213  br label %loop
214
215loopexit:
216  ret void
217
218loop:
219  %iv = phi i32 [ %iv.next, %loop ], [ %iv_start, %preheader ]
220  ; CHECK: %indvars.iv = phi i64
221  %iv.wide = zext i32 %iv to i64
222  %el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
223  store atomic i32 0, i32* %el unordered, align 4
224  %iv.next = add nsw i32 %iv, -1
225  ; CHECK: %loopcond = icmp slt i64 %indvars.iv, 1
226  %loopcond = icmp slt i32 %iv, 1
227  br i1 %loopcond, label %loopexit, label %loop
228}
229
230!0 = !{i32 0, i32 2147483647}
231