1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4define i32 @select_0_or_1_from_bool(i1 %x) { 5; CHECK-LABEL: @select_0_or_1_from_bool( 6; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[X:%.*]], true 7; CHECK-NEXT: [[ADD:%.*]] = zext i1 [[TMP1]] to i32 8; CHECK-NEXT: ret i32 [[ADD]] 9; 10 %ext = sext i1 %x to i32 11 %add = add i32 %ext, 1 12 ret i32 %add 13} 14 15define <2 x i32> @select_0_or_1_from_bool_vec(<2 x i1> %x) { 16; CHECK-LABEL: @select_0_or_1_from_bool_vec( 17; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i1> [[X:%.*]], <i1 true, i1 true> 18; CHECK-NEXT: [[ADD:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32> 19; CHECK-NEXT: ret <2 x i32> [[ADD]] 20; 21 %ext = sext <2 x i1> %x to <2 x i32> 22 %add = add <2 x i32> %ext, <i32 1, i32 1> 23 ret <2 x i32> %add 24} 25 26define i32 @select_C_minus_1_or_C_from_bool(i1 %x) { 27; CHECK-LABEL: @select_C_minus_1_or_C_from_bool( 28; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[X:%.*]] to i32 29; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[EXT]], 42 30; CHECK-NEXT: ret i32 [[ADD]] 31; 32 %ext = sext i1 %x to i32 33 %add = add i32 %ext, 42 34 ret i32 %add 35} 36 37define <2 x i32> @select_C_minus_1_or_C_from_bool_vec(<2 x i1> %x) { 38; CHECK-LABEL: @select_C_minus_1_or_C_from_bool_vec( 39; CHECK-NEXT: [[EXT:%.*]] = sext <2 x i1> [[X:%.*]] to <2 x i32> 40; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i32> [[EXT]], <i32 42, i32 43> 41; CHECK-NEXT: ret <2 x i32> [[ADD]] 42; 43 %ext = sext <2 x i1> %x to <2 x i32> 44 %add = add <2 x i32> %ext, <i32 42, i32 43> 45 ret <2 x i32> %add 46} 47 48; This is an 'andn' of the low bit. 49 50define i32 @flip_and_mask(i32 %x) { 51; CHECK-LABEL: @flip_and_mask( 52; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1 53; CHECK-NEXT: [[INC:%.*]] = xor i32 [[TMP1]], 1 54; CHECK-NEXT: ret i32 [[INC]] 55; 56 %shl = shl i32 %x, 31 57 %shr = ashr i32 %shl, 31 58 %inc = add i32 %shr, 1 59 ret i32 %inc 60} 61 62define <2 x i8> @flip_and_mask_splat(<2 x i8> %x) { 63; CHECK-LABEL: @flip_and_mask_splat( 64; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], <i8 1, i8 1> 65; CHECK-NEXT: [[INC:%.*]] = xor <2 x i8> [[TMP1]], <i8 1, i8 1> 66; CHECK-NEXT: ret <2 x i8> [[INC]] 67; 68 %shl = shl <2 x i8> %x, <i8 7, i8 7> 69 %shr = ashr <2 x i8> %shl, <i8 7, i8 7> 70 %inc = add <2 x i8> %shr, <i8 1, i8 1> 71 ret <2 x i8> %inc 72} 73 74define i32 @test1(i32 %A) { 75; CHECK-LABEL: @test1( 76; CHECK-NEXT: ret i32 [[A:%.*]] 77; 78 %B = add i32 %A, 0 79 ret i32 %B 80} 81 82define i32 @test2(i32 %A) { 83; CHECK-LABEL: @test2( 84; CHECK-NEXT: ret i32 [[A:%.*]] 85; 86 %B = add i32 %A, 5 87 %C = add i32 %B, -5 88 ret i32 %C 89} 90 91define i32 @test3(i32 %A) { 92; CHECK-LABEL: @test3( 93; CHECK-NEXT: ret i32 [[A:%.*]] 94; 95 %B = add i32 %A, 5 96 %C = sub i32 %B, 5 97 ret i32 %C 98} 99 100; D = B + -A = B - A 101define i32 @test4(i32 %A, i32 %B) { 102; CHECK-LABEL: @test4( 103; CHECK-NEXT: [[D:%.*]] = sub i32 [[B:%.*]], [[A:%.*]] 104; CHECK-NEXT: ret i32 [[D]] 105; 106 %C = sub i32 0, %A 107 %D = add i32 %B, %C 108 ret i32 %D 109} 110 111; D = -A + B = B - A 112define i32 @test5(i32 %A, i32 %B) { 113; CHECK-LABEL: @test5( 114; CHECK-NEXT: [[D:%.*]] = sub i32 [[B:%.*]], [[A:%.*]] 115; CHECK-NEXT: ret i32 [[D]] 116; 117 %C = sub i32 0, %A 118 %D = add i32 %C, %B 119 ret i32 %D 120} 121 122define <2 x i8> @neg_op0_vec_undef_elt(<2 x i8> %a, <2 x i8> %b) { 123; CHECK-LABEL: @neg_op0_vec_undef_elt( 124; CHECK-NEXT: [[R:%.*]] = sub <2 x i8> [[B:%.*]], [[A:%.*]] 125; CHECK-NEXT: ret <2 x i8> [[R]] 126; 127 %nega = sub <2 x i8> <i8 0, i8 undef>, %a 128 %r = add <2 x i8> %nega, %b 129 ret <2 x i8> %r 130} 131 132define <2 x i8> @neg_neg_vec_undef_elt(<2 x i8> %a, <2 x i8> %b) { 133; CHECK-LABEL: @neg_neg_vec_undef_elt( 134; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i8> [[A:%.*]], [[B:%.*]] 135; CHECK-NEXT: [[R:%.*]] = sub <2 x i8> zeroinitializer, [[TMP1]] 136; CHECK-NEXT: ret <2 x i8> [[R]] 137; 138 %nega = sub <2 x i8> <i8 undef, i8 0>, %a 139 %negb = sub <2 x i8> <i8 undef, i8 0>, %b 140 %r = add <2 x i8> %nega, %negb 141 ret <2 x i8> %r 142} 143 144; C = 7*A+A == 8*A == A << 3 145define i32 @test6(i32 %A) { 146; CHECK-LABEL: @test6( 147; CHECK-NEXT: [[C:%.*]] = shl i32 [[A:%.*]], 3 148; CHECK-NEXT: ret i32 [[C]] 149; 150 %B = mul i32 7, %A 151 %C = add i32 %B, %A 152 ret i32 %C 153} 154 155; C = A+7*A == 8*A == A << 3 156define i32 @test7(i32 %A) { 157; CHECK-LABEL: @test7( 158; CHECK-NEXT: [[C:%.*]] = shl i32 [[A:%.*]], 3 159; CHECK-NEXT: ret i32 [[C]] 160; 161 %B = mul i32 7, %A 162 %C = add i32 %A, %B 163 ret i32 %C 164} 165 166; (A & C1)+(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 167define i32 @test8(i32 %A, i32 %B) { 168; CHECK-LABEL: @test8( 169; CHECK-NEXT: [[A1:%.*]] = and i32 [[A:%.*]], 7 170; CHECK-NEXT: [[B1:%.*]] = and i32 [[B:%.*]], 128 171; CHECK-NEXT: [[C:%.*]] = or i32 [[A1]], [[B1]] 172; CHECK-NEXT: ret i32 [[C]] 173; 174 %A1 = and i32 %A, 7 175 %B1 = and i32 %B, 128 176 %C = add i32 %A1, %B1 177 ret i32 %C 178} 179 180define i32 @test9(i32 %A) { 181; CHECK-LABEL: @test9( 182; CHECK-NEXT: [[C:%.*]] = shl i32 [[A:%.*]], 5 183; CHECK-NEXT: ret i32 [[C]] 184; 185 %B = shl i32 %A, 4 186 %C = add i32 %B, %B 187 ret i32 %C 188} 189 190; a != -b 191define i1 @test10(i8 %a, i8 %b) { 192; CHECK-LABEL: @test10( 193; CHECK-NEXT: [[ADD:%.*]] = sub i8 0, [[B:%.*]] 194; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[ADD]], [[A:%.*]] 195; CHECK-NEXT: ret i1 [[C]] 196; 197 %add = add i8 %a, %b 198 %c = icmp ne i8 %add, 0 199 ret i1 %c 200} 201 202define <2 x i1> @test10vec(<2 x i8> %a, <2 x i8> %b) { 203; CHECK-LABEL: @test10vec( 204; CHECK-NEXT: [[C:%.*]] = sub <2 x i8> zeroinitializer, [[B:%.*]] 205; CHECK-NEXT: [[D:%.*]] = icmp ne <2 x i8> [[C]], [[A:%.*]] 206; CHECK-NEXT: ret <2 x i1> [[D]] 207; 208 %c = add <2 x i8> %a, %b 209 %d = icmp ne <2 x i8> %c, zeroinitializer 210 ret <2 x i1> %d 211} 212 213define i1 @test11(i8 %A) { 214; CHECK-LABEL: @test11( 215; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A:%.*]], 1 216; CHECK-NEXT: ret i1 [[C]] 217; 218 %B = add i8 %A, -1 219 %c = icmp ne i8 %B, 0 220 ret i1 %c 221} 222 223define <2 x i1> @test11vec(<2 x i8> %a) { 224; CHECK-LABEL: @test11vec( 225; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> [[A:%.*]], <i8 1, i8 1> 226; CHECK-NEXT: ret <2 x i1> [[C]] 227; 228 %b = add <2 x i8> %a, <i8 -1, i8 -1> 229 %c = icmp ne <2 x i8> %b, zeroinitializer 230 ret <2 x i1> %c 231} 232 233; Should be transformed into shl A, 1? 234 235define i32 @test12(i32 %A, i32 %B) { 236; CHECK-LABEL: @test12( 237; CHECK-NEXT: br label [[X:%.*]] 238; CHECK: X: 239; CHECK-NEXT: [[C_OK:%.*]] = add i32 [[B:%.*]], [[A:%.*]] 240; CHECK-NEXT: [[D:%.*]] = add i32 [[C_OK]], [[A]] 241; CHECK-NEXT: ret i32 [[D]] 242; 243 %C_OK = add i32 %B, %A 244 br label %X 245 246X: ; preds = %0 247 %D = add i32 %C_OK, %A 248 ret i32 %D 249} 250 251;; TODO: shl A, 1? 252define i32 @test13(i32 %A, i32 %B, i32 %C) { 253; CHECK-LABEL: @test13( 254; CHECK-NEXT: [[D_OK:%.*]] = add i32 [[A:%.*]], [[B:%.*]] 255; CHECK-NEXT: [[E_OK:%.*]] = add i32 [[D_OK]], [[C:%.*]] 256; CHECK-NEXT: [[F:%.*]] = add i32 [[E_OK]], [[A]] 257; CHECK-NEXT: ret i32 [[F]] 258; 259 %D_OK = add i32 %A, %B 260 %E_OK = add i32 %D_OK, %C 261 %F = add i32 %E_OK, %A 262 ret i32 %F 263} 264 265define i32 @test14(i32 %offset, i32 %difference) { 266; CHECK-LABEL: @test14( 267; CHECK-NEXT: [[TMP_2:%.*]] = and i32 [[DIFFERENCE:%.*]], 3 268; CHECK-NEXT: [[TMP_3_OK:%.*]] = add i32 [[TMP_2]], [[OFFSET:%.*]] 269; CHECK-NEXT: [[TMP_5_MASK:%.*]] = and i32 [[DIFFERENCE]], -4 270; CHECK-NEXT: [[TMP_8:%.*]] = add i32 [[TMP_3_OK]], [[TMP_5_MASK]] 271; CHECK-NEXT: ret i32 [[TMP_8]] 272; 273 %tmp.2 = and i32 %difference, 3 274 %tmp.3_OK = add i32 %tmp.2, %offset 275 %tmp.5.mask = and i32 %difference, -4 276 ; == add %offset, %difference 277 %tmp.8 = add i32 %tmp.3_OK, %tmp.5.mask 278 ret i32 %tmp.8 279} 280 281; Only one bit set 282define i8 @test15(i8 %A) { 283; CHECK-LABEL: @test15( 284; CHECK-NEXT: [[C:%.*]] = and i8 [[A:%.*]], 16 285; CHECK-NEXT: ret i8 [[C]] 286; 287 %B = add i8 %A, -64 288 %C = and i8 %B, 16 289 ret i8 %C 290} 291 292; Only one bit set 293define i8 @test16(i8 %A) { 294; CHECK-LABEL: @test16( 295; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], 16 296; CHECK-NEXT: [[C:%.*]] = xor i8 [[B]], 16 297; CHECK-NEXT: ret i8 [[C]] 298; 299 %B = add i8 %A, 16 300 %C = and i8 %B, 16 301 ret i8 %C 302} 303 304define i32 @test17(i32 %A) { 305; CHECK-LABEL: @test17( 306; CHECK-NEXT: [[C:%.*]] = sub i32 0, [[A:%.*]] 307; CHECK-NEXT: ret i32 [[C]] 308; 309 %B = xor i32 %A, -1 310 %C = add i32 %B, 1 311 ret i32 %C 312} 313 314define i8 @test18(i8 %A) { 315; CHECK-LABEL: @test18( 316; CHECK-NEXT: [[C:%.*]] = sub i8 16, [[A:%.*]] 317; CHECK-NEXT: ret i8 [[C]] 318; 319 %B = xor i8 %A, -1 320 %C = add i8 %B, 17 321 ret i8 %C 322} 323 324define <2 x i64> @test18vec(<2 x i64> %A) { 325; CHECK-LABEL: @test18vec( 326; CHECK-NEXT: [[ADD:%.*]] = sub <2 x i64> <i64 1, i64 2>, [[A:%.*]] 327; CHECK-NEXT: ret <2 x i64> [[ADD]] 328; 329 %xor = xor <2 x i64> %A, <i64 -1, i64 -1> 330 %add = add <2 x i64> %xor, <i64 2, i64 3> 331 ret <2 x i64> %add 332} 333 334define i32 @test19(i1 %C) { 335; CHECK-LABEL: @test19( 336; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 1123, i32 133 337; CHECK-NEXT: ret i32 [[V]] 338; 339 %A = select i1 %C, i32 1000, i32 10 340 %V = add i32 %A, 123 341 ret i32 %V 342} 343 344define <2 x i32> @test19vec(i1 %C) { 345; CHECK-LABEL: @test19vec( 346; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1123, i32 1123>, <2 x i32> <i32 133, i32 133> 347; CHECK-NEXT: ret <2 x i32> [[V]] 348; 349 %A = select i1 %C, <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10> 350 %V = add <2 x i32> %A, <i32 123, i32 123> 351 ret <2 x i32> %V 352} 353 354; This is an InstSimplify fold, but test it here to make sure that 355; InstCombine does not prevent the fold. 356; With NSW, add of sign bit -> or of sign bit. 357 358define i32 @test20(i32 %x) { 359; CHECK-LABEL: @test20( 360; CHECK-NEXT: ret i32 [[X:%.*]] 361; 362 %y = xor i32 %x, -2147483648 363 %z = add nsw i32 %y, -2147483648 364 ret i32 %z 365} 366 367define i32 @xor_sign_bit(i32 %x) { 368; CHECK-LABEL: @xor_sign_bit( 369; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], -2147483606 370; CHECK-NEXT: ret i32 [[ADD]] 371; 372 %xor = xor i32 %x, 2147483648 373 %add = add i32 %xor, 42 374 ret i32 %add 375} 376 377; No-wrap info allows converting the add to 'or'. 378 379define i8 @add_nsw_signbit(i8 %x) { 380; CHECK-LABEL: @add_nsw_signbit( 381; CHECK-NEXT: [[Y:%.*]] = or i8 [[X:%.*]], -128 382; CHECK-NEXT: ret i8 [[Y]] 383; 384 %y = add nsw i8 %x, -128 385 ret i8 %y 386} 387 388; No-wrap info allows converting the add to 'or'. 389 390define i8 @add_nuw_signbit(i8 %x) { 391; CHECK-LABEL: @add_nuw_signbit( 392; CHECK-NEXT: [[Y:%.*]] = or i8 [[X:%.*]], -128 393; CHECK-NEXT: ret i8 [[Y]] 394; 395 %y = add nuw i8 %x, 128 396 ret i8 %y 397} 398 399define i1 @test21(i32 %x) { 400; CHECK-LABEL: @test21( 401; CHECK-NEXT: [[Y:%.*]] = icmp eq i32 [[X:%.*]], 119 402; CHECK-NEXT: ret i1 [[Y]] 403; 404 %t = add i32 %x, 4 405 %y = icmp eq i32 %t, 123 406 ret i1 %y 407} 408 409define <2 x i1> @test21vec(<2 x i32> %x) { 410; CHECK-LABEL: @test21vec( 411; CHECK-NEXT: [[Y:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 119, i32 119> 412; CHECK-NEXT: ret <2 x i1> [[Y]] 413; 414 %t = add <2 x i32> %x, <i32 4, i32 4> 415 %y = icmp eq <2 x i32> %t, <i32 123, i32 123> 416 ret <2 x i1> %y 417} 418 419define i32 @test22(i32 %V) { 420; CHECK-LABEL: @test22( 421; CHECK-NEXT: switch i32 [[V:%.*]], label [[DEFAULT:%.*]] [ 422; CHECK-NEXT: i32 10, label [[LAB1:%.*]] 423; CHECK-NEXT: i32 20, label [[LAB2:%.*]] 424; CHECK-NEXT: ] 425; CHECK: Default: 426; CHECK-NEXT: ret i32 123 427; CHECK: Lab1: 428; CHECK-NEXT: ret i32 12312 429; CHECK: Lab2: 430; CHECK-NEXT: ret i32 1231231 431; 432 %V2 = add i32 %V, 10 433 switch i32 %V2, label %Default [ 434 i32 20, label %Lab1 435 i32 30, label %Lab2 436 ] 437 438Default: ; preds = %0 439 ret i32 123 440 441Lab1: ; preds = %0 442 ret i32 12312 443 444Lab2: ; preds = %0 445 ret i32 1231231 446} 447 448define i32 @test23(i1 %C, i32 %a) { 449; CHECK-LABEL: @test23( 450; CHECK-NEXT: entry: 451; CHECK-NEXT: br i1 [[C:%.*]], label [[ENDIF:%.*]], label [[ELSE:%.*]] 452; CHECK: else: 453; CHECK-NEXT: br label [[ENDIF]] 454; CHECK: endif: 455; CHECK-NEXT: [[B_0:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ 2, [[ELSE]] ] 456; CHECK-NEXT: ret i32 [[B_0]] 457; 458entry: 459 br i1 %C, label %endif, label %else 460 461else: ; preds = %entry 462 br label %endif 463 464endif: ; preds = %else, %entry 465 %b.0 = phi i32 [ 0, %entry ], [ 1, %else ] 466 %tmp.4 = add i32 %b.0, 1 467 ret i32 %tmp.4 468} 469 470define i32 @test24(i32 %A) { 471; CHECK-LABEL: @test24( 472; CHECK-NEXT: [[B:%.*]] = shl i32 [[A:%.*]], 1 473; CHECK-NEXT: ret i32 [[B]] 474; 475 %B = add i32 %A, 1 476 %C = shl i32 %B, 1 477 %D = sub i32 %C, 2 478 ret i32 %D 479} 480 481define i64 @test25(i64 %Y) { 482; CHECK-LABEL: @test25( 483; CHECK-NEXT: [[TMP_8:%.*]] = shl i64 [[Y:%.*]], 3 484; CHECK-NEXT: ret i64 [[TMP_8]] 485; 486 %tmp.4 = shl i64 %Y, 2 487 %tmp.12 = shl i64 %Y, 2 488 %tmp.8 = add i64 %tmp.4, %tmp.12 489 ret i64 %tmp.8 490} 491 492define i32 @test26(i32 %A, i32 %B) { 493; CHECK-LABEL: @test26( 494; CHECK-NEXT: ret i32 [[A:%.*]] 495; 496 %C = add i32 %A, %B 497 %D = sub i32 %C, %B 498 ret i32 %D 499} 500 501; Fold add through select. 502define i32 @test27(i1 %C, i32 %X, i32 %Y) { 503; CHECK-LABEL: @test27( 504; CHECK-NEXT: [[C_UPGRD_1_V:%.*]] = select i1 [[C:%.*]], i32 [[X:%.*]], i32 123 505; CHECK-NEXT: ret i32 [[C_UPGRD_1_V]] 506; 507 %A = add i32 %X, %Y 508 %B = add i32 %Y, 123 509 %C.upgrd.1 = select i1 %C, i32 %A, i32 %B 510 %D = sub i32 %C.upgrd.1, %Y 511 ret i32 %D 512} 513 514define i32 @test28(i32 %X) { 515; CHECK-LABEL: @test28( 516; CHECK-NEXT: [[Z:%.*]] = sub i32 -1192, [[X:%.*]] 517; CHECK-NEXT: ret i32 [[Z]] 518; 519 %Y = add i32 %X, 1234 520 %Z = sub i32 42, %Y 521 ret i32 %Z 522} 523 524define i32 @test29(i32 %x, i32 %y) { 525; CHECK-LABEL: @test29( 526; CHECK-NEXT: [[TMP_2:%.*]] = sub i32 [[X:%.*]], [[Y:%.*]] 527; CHECK-NEXT: [[TMP_7:%.*]] = and i32 [[X]], 63 528; CHECK-NEXT: [[TMP_9:%.*]] = and i32 [[TMP_2]], -64 529; CHECK-NEXT: [[TMP_10:%.*]] = or i32 [[TMP_7]], [[TMP_9]] 530; CHECK-NEXT: ret i32 [[TMP_10]] 531; 532 %tmp.2 = sub i32 %x, %y 533 %tmp.2.mask = and i32 %tmp.2, 63 534 %tmp.6 = add i32 %tmp.2.mask, %y 535 %tmp.7 = and i32 %tmp.6, 63 536 %tmp.9 = and i32 %tmp.2, -64 537 %tmp.10 = or i32 %tmp.7, %tmp.9 538 ret i32 %tmp.10 539} 540 541; Add of sign bit -> xor of sign bit. 542define i64 @test30(i64 %x) { 543; CHECK-LABEL: @test30( 544; CHECK-NEXT: ret i64 [[X:%.*]] 545; 546 %tmp.2 = xor i64 %x, -9223372036854775808 547 %tmp.4 = add i64 %tmp.2, -9223372036854775808 548 ret i64 %tmp.4 549} 550 551define i32 @test31(i32 %A) { 552; CHECK-LABEL: @test31( 553; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[A:%.*]], 5 554; CHECK-NEXT: ret i32 [[TMP1]] 555; 556 %B = add i32 %A, 4 557 %C = mul i32 %B, 5 558 %D = sub i32 %C, 20 559 ret i32 %D 560} 561 562define i32 @test32(i32 %A) { 563; CHECK-LABEL: @test32( 564; CHECK-NEXT: [[B:%.*]] = shl i32 [[A:%.*]], 2 565; CHECK-NEXT: ret i32 [[B]] 566; 567 %B = add i32 %A, 4 568 %C = shl i32 %B, 2 569 %D = sub i32 %C, 16 570 ret i32 %D 571} 572 573define i8 @test33(i8 %A) { 574; CHECK-LABEL: @test33( 575; CHECK-NEXT: [[C:%.*]] = or i8 [[A:%.*]], 1 576; CHECK-NEXT: ret i8 [[C]] 577; 578 %B = and i8 %A, -2 579 %C = add i8 %B, 1 580 ret i8 %C 581} 582 583define i8 @test34(i8 %A) { 584; CHECK-LABEL: @test34( 585; CHECK-NEXT: [[C:%.*]] = and i8 [[A:%.*]], 12 586; CHECK-NEXT: ret i8 [[C]] 587; 588 %B = add i8 %A, 64 589 %C = and i8 %B, 12 590 ret i8 %C 591} 592 593; If all bits affected by the add are included 594; in the mask, do the add before the mask op. 595 596define i8 @masked_add(i8 %x) { 597; CHECK-LABEL: @masked_add( 598; CHECK-NEXT: [[AND1:%.*]] = add i8 [[X:%.*]], 96 599; CHECK-NEXT: [[R:%.*]] = and i8 [[AND1]], -16 600; CHECK-NEXT: ret i8 [[R]] 601; 602 %and = and i8 %x, 240 ; 0xf0 603 %r = add i8 %and, 96 ; 0x60 604 ret i8 %r 605} 606 607define <2 x i8> @masked_add_splat(<2 x i8> %x) { 608; CHECK-LABEL: @masked_add_splat( 609; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 -64, i8 -64> 610; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[AND]], <i8 64, i8 64> 611; CHECK-NEXT: ret <2 x i8> [[R]] 612; 613 %and = and <2 x i8> %x, <i8 192, i8 192> ; 0xc0 614 %r = add <2 x i8> %and, <i8 64, i8 64> ; 0x40 615 ret <2 x i8> %r 616} 617 618define i8 @not_masked_add(i8 %x) { 619; CHECK-LABEL: @not_masked_add( 620; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 112 621; CHECK-NEXT: [[R:%.*]] = add nuw i8 [[AND]], 96 622; CHECK-NEXT: ret i8 [[R]] 623; 624 %and = and i8 %x, 112 ; 0x70 625 %r = add i8 %and, 96 ; 0x60 626 ret i8 %r 627} 628 629define i32 @test35(i32 %a) { 630; CHECK-LABEL: @test35( 631; CHECK-NEXT: ret i32 -1 632; 633 %tmpnot = xor i32 %a, -1 634 %tmp2 = add i32 %tmpnot, %a 635 ret i32 %tmp2 636} 637 638define i32 @test36(i32 %a) { 639; CHECK-LABEL: @test36( 640; CHECK-NEXT: ret i32 0 641; 642 %x = and i32 %a, -2 643 %y = and i32 %a, -126 644 %z = add i32 %x, %y 645 %q = and i32 %z, 1 ; always zero 646 ret i32 %q 647} 648 649define i1 @test37(i32 %a, i32 %b) { 650; CHECK-LABEL: @test37( 651; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[B:%.*]], 0 652; CHECK-NEXT: ret i1 [[CMP]] 653; 654 %add = add i32 %a, %b 655 %cmp = icmp eq i32 %add, %a 656 ret i1 %cmp 657} 658 659define i1 @test38(i32 %a, i32 %b) { 660; CHECK-LABEL: @test38( 661; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0 662; CHECK-NEXT: ret i1 [[CMP]] 663; 664 %add = add i32 %a, %b 665 %cmp = icmp eq i32 %add, %b 666 ret i1 %cmp 667} 668 669define i1 @test39(i32 %a, i32 %b) { 670; CHECK-LABEL: @test39( 671; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[B:%.*]], 0 672; CHECK-NEXT: ret i1 [[CMP]] 673; 674 %add = add i32 %b, %a 675 %cmp = icmp eq i32 %add, %a 676 ret i1 %cmp 677} 678 679define i1 @test40(i32 %a, i32 %b) { 680; CHECK-LABEL: @test40( 681; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0 682; CHECK-NEXT: ret i1 [[CMP]] 683; 684 %add = add i32 %b, %a 685 %cmp = icmp eq i32 %add, %b 686 ret i1 %cmp 687} 688 689; (add (zext (add nuw X, C2)), C) --> (zext (add nuw X, C2 + C)) 690 691define i64 @test41(i32 %a) { 692; CHECK-LABEL: @test41( 693; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[A:%.*]], 15 694; CHECK-NEXT: [[SUB:%.*]] = zext i32 [[TMP1]] to i64 695; CHECK-NEXT: ret i64 [[SUB]] 696; 697 %add = add nuw i32 %a, 16 698 %zext = zext i32 %add to i64 699 %sub = add i64 %zext, -1 700 ret i64 %sub 701} 702 703; (add (zext (add nuw X, C2)), C) --> (zext (add nuw X, C2 + C)) 704 705define <2 x i64> @test41vec(<2 x i32> %a) { 706; CHECK-LABEL: @test41vec( 707; CHECK-NEXT: [[TMP1:%.*]] = add nuw <2 x i32> [[A:%.*]], <i32 15, i32 15> 708; CHECK-NEXT: [[SUB:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> 709; CHECK-NEXT: ret <2 x i64> [[SUB]] 710; 711 %add = add nuw <2 x i32> %a, <i32 16, i32 16> 712 %zext = zext <2 x i32> %add to <2 x i64> 713 %sub = add <2 x i64> %zext, <i64 -1, i64 -1> 714 ret <2 x i64> %sub 715} 716 717define <2 x i64> @test41vec_and_multiuse(<2 x i32> %a) { 718; CHECK-LABEL: @test41vec_and_multiuse( 719; CHECK-NEXT: [[ADD:%.*]] = add nuw <2 x i32> [[A:%.*]], <i32 16, i32 16> 720; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[ADD]] to <2 x i64> 721; CHECK-NEXT: [[SUB:%.*]] = add nsw <2 x i64> [[ZEXT]], <i64 -1, i64 -1> 722; CHECK-NEXT: [[EXTRAUSE:%.*]] = add nsw <2 x i64> [[SUB]], [[ZEXT]] 723; CHECK-NEXT: ret <2 x i64> [[EXTRAUSE]] 724; 725 %add = add nuw <2 x i32> %a, <i32 16, i32 16> 726 %zext = zext <2 x i32> %add to <2 x i64> 727 %sub = add <2 x i64> %zext, <i64 -1, i64 -1> 728 %extrause = add <2 x i64> %zext, %sub 729 ret <2 x i64> %extrause 730} 731 732define i32 @test42(i1 %C) { 733; CHECK-LABEL: @test42( 734; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 1123, i32 133 735; CHECK-NEXT: ret i32 [[V]] 736; 737 %A = select i1 %C, i32 1000, i32 10 738 %V = add i32 123, %A 739 ret i32 %V 740} 741 742define <2 x i32> @test42vec(i1 %C) { 743; CHECK-LABEL: @test42vec( 744; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1123, i32 1123>, <2 x i32> <i32 133, i32 133> 745; CHECK-NEXT: ret <2 x i32> [[V]] 746; 747 %A = select i1 %C, <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10> 748 %V = add <2 x i32> <i32 123, i32 123>, %A 749 ret <2 x i32> %V 750} 751 752define <2 x i32> @test42vec2(i1 %C) { 753; CHECK-LABEL: @test42vec2( 754; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1123, i32 2833>, <2 x i32> <i32 133, i32 363> 755; CHECK-NEXT: ret <2 x i32> [[V]] 756; 757 %A = select i1 %C, <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30> 758 %V = add <2 x i32> <i32 123, i32 333>, %A 759 ret <2 x i32> %V 760} 761 762define i32 @test55(i1 %which) { 763; CHECK-LABEL: @test55( 764; CHECK-NEXT: entry: 765; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]] 766; CHECK: delay: 767; CHECK-NEXT: br label [[FINAL]] 768; CHECK: final: 769; CHECK-NEXT: [[A:%.*]] = phi i32 [ 1123, [[ENTRY:%.*]] ], [ 133, [[DELAY]] ] 770; CHECK-NEXT: ret i32 [[A]] 771; 772entry: 773 br i1 %which, label %final, label %delay 774 775delay: 776 br label %final 777 778final: 779 %A = phi i32 [ 1000, %entry ], [ 10, %delay ] 780 %value = add i32 123, %A 781 ret i32 %value 782} 783 784define <2 x i32> @test43vec(i1 %which) { 785; CHECK-LABEL: @test43vec( 786; CHECK-NEXT: entry: 787; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]] 788; CHECK: delay: 789; CHECK-NEXT: br label [[FINAL]] 790; CHECK: final: 791; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1123, i32 1123>, [[ENTRY:%.*]] ], [ <i32 133, i32 133>, [[DELAY]] ] 792; CHECK-NEXT: ret <2 x i32> [[A]] 793; 794entry: 795 br i1 %which, label %final, label %delay 796 797delay: 798 br label %final 799 800final: 801 %A = phi <2 x i32> [ <i32 1000, i32 1000>, %entry ], [ <i32 10, i32 10>, %delay ] 802 %value = add <2 x i32> <i32 123, i32 123>, %A 803 ret <2 x i32> %value 804} 805 806define <2 x i32> @test43vec2(i1 %which) { 807; CHECK-LABEL: @test43vec2( 808; CHECK-NEXT: entry: 809; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]] 810; CHECK: delay: 811; CHECK-NEXT: br label [[FINAL]] 812; CHECK: final: 813; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1123, i32 2833>, [[ENTRY:%.*]] ], [ <i32 133, i32 363>, [[DELAY]] ] 814; CHECK-NEXT: ret <2 x i32> [[A]] 815; 816entry: 817 br i1 %which, label %final, label %delay 818 819delay: 820 br label %final 821 822final: 823 %A = phi <2 x i32> [ <i32 1000, i32 2500>, %entry ], [ <i32 10, i32 30>, %delay ] 824 %value = add <2 x i32> <i32 123, i32 333>, %A 825 ret <2 x i32> %value 826} 827 828; E = (A + 1) + ~B = A - B 829define i32 @add_not_increment(i32 %A, i32 %B) { 830; CHECK-LABEL: @add_not_increment( 831; CHECK-NEXT: [[E:%.*]] = sub i32 [[A:%.*]], [[B:%.*]] 832; CHECK-NEXT: ret i32 [[E]] 833; 834 %C = xor i32 %B, -1 835 %D = add i32 %A, 1 836 %E = add i32 %D, %C 837 ret i32 %E 838} 839 840; E = (A + 1) + ~B = A - B 841define <2 x i32> @add_not_increment_vec(<2 x i32> %A, <2 x i32> %B) { 842; CHECK-LABEL: @add_not_increment_vec( 843; CHECK-NEXT: [[E:%.*]] = sub <2 x i32> [[A:%.*]], [[B:%.*]] 844; CHECK-NEXT: ret <2 x i32> [[E]] 845; 846 %C = xor <2 x i32> %B, <i32 -1, i32 -1> 847 %D = add <2 x i32> %A, <i32 1, i32 1> 848 %E = add <2 x i32> %D, %C 849 ret <2 x i32> %E 850} 851 852; E = ~B + (1 + A) = A - B 853define i32 @add_not_increment_commuted(i32 %A, i32 %B) { 854; CHECK-LABEL: @add_not_increment_commuted( 855; CHECK-NEXT: [[E:%.*]] = sub i32 [[A:%.*]], [[B:%.*]] 856; CHECK-NEXT: ret i32 [[E]] 857; 858 %C = xor i32 %B, -1 859 %D = add i32 %A, 1 860 %E = add i32 %C, %D 861 ret i32 %E 862} 863 864