1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -instcombine -S | FileCheck %s
3
4define i5 @XorZextXor(i3 %a) {
5; CHECK-LABEL: @XorZextXor(
6; CHECK-NEXT:    [[CAST:%.*]] = zext i3 %a to i5
7; CHECK-NEXT:    [[OP2:%.*]] = xor i5 [[CAST]], 15
8; CHECK-NEXT:    ret i5 [[OP2]]
9;
10  %op1 = xor i3 %a, 3
11  %cast = zext i3 %op1 to i5
12  %op2 = xor i5 %cast, 12
13  ret i5 %op2
14}
15
16define <2 x i32> @XorZextXorVec(<2 x i1> %a) {
17; CHECK-LABEL: @XorZextXorVec(
18; CHECK-NEXT:    [[CAST:%.*]] = zext <2 x i1> %a to <2 x i32>
19; CHECK-NEXT:    [[OP2:%.*]] = xor <2 x i32> [[CAST]], <i32 2, i32 1>
20; CHECK-NEXT:    ret <2 x i32> [[OP2]]
21;
22  %op1 = xor <2 x i1> %a, <i1 true, i1 false>
23  %cast = zext <2 x i1> %op1 to <2 x i32>
24  %op2 = xor <2 x i32> %cast, <i32 3, i32 1>
25  ret <2 x i32> %op2
26}
27
28define i5 @OrZextOr(i3 %a) {
29; CHECK-LABEL: @OrZextOr(
30; CHECK-NEXT:    [[CAST:%.*]] = zext i3 %a to i5
31; CHECK-NEXT:    [[OP2:%.*]] = or i5 [[CAST]], 11
32; CHECK-NEXT:    ret i5 [[OP2]]
33;
34  %op1 = or i3 %a, 3
35  %cast = zext i3 %op1 to i5
36  %op2 = or i5 %cast, 8
37  ret i5 %op2
38}
39
40define <2 x i32> @OrZextOrVec(<2 x i2> %a) {
41; CHECK-LABEL: @OrZextOrVec(
42; CHECK-NEXT:    [[CAST:%.*]] = zext <2 x i2> %a to <2 x i32>
43; CHECK-NEXT:    [[OP2:%.*]] = or <2 x i32> [[CAST]], <i32 3, i32 5>
44; CHECK-NEXT:    ret <2 x i32> [[OP2]]
45;
46  %op1 = or <2 x i2> %a, <i2 2, i2 0>
47  %cast = zext <2 x i2> %op1 to <2 x i32>
48  %op2 = or <2 x i32> %cast, <i32 1, i32 5>
49  ret <2 x i32> %op2
50}
51
52; Unlike the rest, this case is handled by SimplifyDemandedBits / ShrinkDemandedConstant.
53
54define i5 @AndZextAnd(i3 %a) {
55; CHECK-LABEL: @AndZextAnd(
56; CHECK-NEXT:    [[TMP1:%.*]] = and i3 %a, 2
57; CHECK-NEXT:    [[OP2:%.*]] = zext i3 [[TMP1]] to i5
58; CHECK-NEXT:    ret i5 [[OP2]]
59;
60  %op1 = and i3 %a, 3
61  %cast = zext i3 %op1 to i5
62  %op2 = and i5 %cast, 14
63  ret i5 %op2
64}
65
66define <2 x i32> @AndZextAndVec(<2 x i8> %a) {
67; CHECK-LABEL: @AndZextAndVec(
68; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i8> %a, <i8 5, i8 0>
69; CHECK-NEXT:    [[OP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
70; CHECK-NEXT:    ret <2 x i32> [[OP2]]
71;
72  %op1 = and <2 x i8> %a, <i8 7, i8 0>
73  %cast = zext <2 x i8> %op1 to <2 x i32>
74  %op2 = and <2 x i32> %cast, <i32 261, i32 1>
75  ret <2 x i32> %op2
76}
77
78