1; Show that we know how to translate lsr.
2
3; NOTE: We use -O2 to get rid of memory stores.
4
5; REQUIRES: allow_dump
6
7; Compile using standalone assembler.
8; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
9; RUN:   | FileCheck %s --check-prefix=ASM
10
11; Show bytes in assembled standalone code.
12; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
13; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
14
15; Compile using integrated assembler.
16; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
17; RUN:   | FileCheck %s --check-prefix=IASM
18
19; Show bytes in assembled integrated code.
20; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
21; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
22
23define internal i32 @LshrAmt(i32 %a) {
24; ASM-LABEL:LshrAmt:
25; DIS-LABEL:00000000 <LshrAmt>:
26; IASM-LABEL:LshrAmt:
27
28entry:
29; ASM-NEXT:.LLshrAmt$entry:
30; IASM-NEXT:.LLshrAmt$entry:
31
32  %v = lshr i32 %a, 23
33
34; ASM-NEXT:     lsr     r0, r0, #23
35; DIS-NEXT:   0:        e1a00ba0
36; IASM-NOT:     lsr
37
38  ret i32 %v
39}
40
41define internal i32 @LshrReg(i32 %a, i32 %b) {
42; ASM-LABEL:LshrReg:
43; DIS-LABEL:00000010 <LshrReg>:
44; IASM-LABEL:LshrReg:
45
46entry:
47; ASM-NEXT:.LLshrReg$entry:
48; IASM-NEXT:.LLshrReg$entry:
49
50  %v = lshr i32 %a, %b
51
52; ASM-NEXT:     lsr     r0, r0, r1
53; DIS-NEXT:  10:        e1a00130
54; IASM-NOT:     lsr
55
56  ret i32 %v
57}
58
59define internal <4 x i32> @LshrVec(<4 x i32> %a, <4 x i32> %b) {
60; ASM-LABEL:LshrVec:
61; DIS-LABEL:00000020 <LshrVec>:
62; IASM-LABEL:LshrVec:
63
64entry:
65; ASM-NEXT:.LLshrVec$entry:
66; IASM-NEXT:.LLshrVec$entry:
67
68  %v = lshr <4 x i32> %a, %b
69
70; ASM:          vneg.s32  q1, q1
71; ASM-NEXT:     vshl.u32 q0, q0, q1
72; DIS:      20:          f3b923c2
73; DIS:      24:          f3220440
74; IASM-NOT:     vneg
75; IASM-NOT:     vshl
76
77  ret <4 x i32> %v
78}
79
80define internal <8 x i16> @LshrVeci16(<8 x i16> %a, <8 x i16> %b) {
81; ASM-LABEL:LshrVeci16:
82
83entry:
84
85  %v = lshr <8 x i16> %a, %b
86
87; ASM:          vneg.s16  q1, q1
88; ASM-NEXT:     vshl.u16 q0, q0, q1
89; DIS:      30:          f3b523c2
90; DIS:      34:          f3120440
91; IASM-NOT:     vneg
92; IASM-NOT:     vshl
93
94  ret <8 x i16> %v
95}
96
97define internal <16 x i8> @LshrVeci8(<16 x i8> %a, <16 x i8> %b) {
98; ASM-LABEL:LshrVeci8:
99
100entry:
101
102  %v = lshr <16 x i8> %a, %b
103
104; ASM:          vneg.s8  q1, q1
105; ASM-NEXT:     vshl.u8 q0, q0, q1
106; DIS:      40:         f3b123c2
107; DIS:      44:         f3020440
108; IASM-NOT:     vneg
109; IASM-NOT:     vshl
110
111  ret <16 x i8> %v
112}
113