1; Show that we know how to translate vshl and vshr with immediate shift amounts.
2; We abuse sign extension of vectors of i1 because that's the only way to force
3; Subzero to emit these instructions.
4
5; NOTE: We use -O2 to get rid of memory stores.
6
7; REQUIRES: allow_dump
8
9; Compile using standalone assembler.
10; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
11; RUN:   | FileCheck %s --check-prefix=ASM
12
13; Show bytes in assembled standalone code.
14; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
15; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
16
17; Compile using integrated assembler.
18; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
19; RUN:   | FileCheck %s --check-prefix=IASM
20
21; Show bytes in assembled integrated code.
22; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
23; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
24
25define internal <4 x i32> @SextV4I1(<4 x i32> %a) {
26; ASM-LABEL:SextV4I1
27; DIS-LABEL:00000000 <SextV4I1>:
28; IASM-LABEL:SextV4I1:
29
30  %trunc = trunc <4 x i32> %a to <4 x i1>
31  %sext = sext <4 x i1> %trunc to <4 x i32>
32  ret <4 x i32> %sext
33; ASM:         vshl.u32 {{.*}}, #31
34; ASM-NEXT:    vshr.s32 {{.*}}, #31
35; DIS:      0: f2bf0550
36; DIS-NEXT: 4: f2a10050
37; IASM-NOT:    vshl
38; IASM-NOT:    vshr
39}
40
41define internal <8 x i16> @SextV8I1(<8 x i16> %a) {
42; ASM-LABEL:SextV8I1
43; DIS-LABEL:00000010 <SextV8I1>:
44; IASM-LABEL:SextV8I1:
45
46  %trunc = trunc <8 x i16> %a to <8 x i1>
47  %sext = sext <8 x i1> %trunc to <8 x i16>
48  ret <8 x i16> %sext
49; ASM:          vshl.u16 {{.*}}, #15
50; ASM-NEXT:     vshr.s16 {{.*}}, #15
51; DIS:      10: f29f0550
52; DIS-NEXT: 14: f2910050
53; IASM-NOT:     vshl
54; IASM-NOT:     vshr
55}
56
57define internal <16 x i8> @SextV16I1(<16 x i8> %a) {
58; ASM-LABEL:SextV16I1
59; DIS-LABEL:00000020 <SextV16I1>:
60; IASM-LABEL:SextV16I1:
61
62  %trunc = trunc <16 x i8> %a to <16 x i1>
63  %sext = sext <16 x i1> %trunc to <16 x i8>
64  ret <16 x i8> %sext
65; ASM:          vshl.u8 {{.*}}, #7
66; ASM-NEXT:     vshr.s8 {{.*}}, #7
67; DIS:      20: f28f0550
68; DIS-NEXT: 24: f2890050
69; IASM-NOT:     vshl
70; IASM-NOT:     vshr
71}
72