1; This file tests casting / conversion operations that apply to vector types. 2; bitcast operations are in vector-bitcast.ll. 3 4; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -O2 \ 5; RUN: | FileCheck %s --check-prefix=X8632 --check-prefix=CHECK 6; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -Om1 \ 7; RUN: | FileCheck %s --check-prefix=X8632 --check-prefix=CHECK 8 9; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -O2 \ 10; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK 11; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -Om1 \ 12; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK 13 14; RUN: %if --need=target_MIPS32 --need=allow_dump \ 15; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \ 16; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \ 17; RUN: | %if --need=target_MIPS32 --need=allow_dump \ 18; RUN: --command FileCheck --check-prefix MIPS32 %s 19 20; sext operations 21 22define internal <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) { 23entry: 24 %res = sext <16 x i1> %arg to <16 x i8> 25 ret <16 x i8> %res 26 27; CHECK-LABEL: test_sext_v16i1_to_v16i8 28; X8632: pxor 29; X8632: pcmpeqb 30; X8632: psubb 31; X8632: pand 32; X8632: pxor 33; X8632: pcmpgtb 34; ARM32: vshl.s8 35; ARM32-NEXT: vshr.s8 36; MIPS32: move t2,a0 37; MIPS32: andi t2,t2,0xff 38; MIPS32: andi t2,t2,0x1 39; MIPS32: sll t2,t2,0x1f 40; MIPS32: sra t2,t2,0x1f 41; MIPS32: andi t2,t2,0xff 42; MIPS32: srl v0,v0,0x8 43; MIPS32: sll v0,v0,0x8 44; MIPS32: or t2,t2,v0 45; MIPS32: move v0,a0 46; MIPS32: srl v0,v0,0x8 47; MIPS32: andi v0,v0,0xff 48; MIPS32: andi v0,v0,0x1 49; MIPS32: sll v0,v0,0x1f 50; MIPS32: sra v0,v0,0x1f 51; MIPS32: andi v0,v0,0xff 52; MIPS32: sll v0,v0,0x8 53; MIPS32: lui t3,0xffff 54; MIPS32: ori t3,t3,0xff 55; MIPS32: and t2,t2,t3 56; MIPS32: or v0,v0,t2 57; MIPS32: move t2,a0 58; MIPS32: srl t2,t2,0x10 59; MIPS32: andi t2,t2,0xff 60; MIPS32: andi t2,t2,0x1 61; MIPS32: sll t2,t2,0x1f 62; MIPS32: sra t2,t2,0x1f 63; MIPS32: andi t2,t2,0xff 64; MIPS32: sll t2,t2,0x10 65; MIPS32: lui t3,0xff00 66; MIPS32: ori t3,t3,0xffff 67; MIPS32: and v0,v0,t3 68; MIPS32: or t2,t2,v0 69; MIPS32: srl a0,a0,0x18 70; MIPS32: andi a0,a0,0x1 71; MIPS32: sll a0,a0,0x1f 72; MIPS32: sra a0,a0,0x1f 73; MIPS32: sll a0,a0,0x18 74; MIPS32: sll t2,t2,0x8 75; MIPS32: srl t2,t2,0x8 76; MIPS32: or a0,a0,t2 77; MIPS32: move v0,a1 78; MIPS32: andi v0,v0,0xff 79; MIPS32: andi v0,v0,0x1 80; MIPS32: sll v0,v0,0x1f 81; MIPS32: sra v0,v0,0x1f 82; MIPS32: andi v0,v0,0xff 83; MIPS32: srl v1,v1,0x8 84; MIPS32: sll v1,v1,0x8 85; MIPS32: or v0,v0,v1 86; MIPS32: move v1,a1 87; MIPS32: srl v1,v1,0x8 88; MIPS32: andi v1,v1,0xff 89; MIPS32: andi v1,v1,0x1 90; MIPS32: sll v1,v1,0x1f 91; MIPS32: sra v1,v1,0x1f 92; MIPS32: andi v1,v1,0xff 93; MIPS32: sll v1,v1,0x8 94; MIPS32: lui t2,0xffff 95; MIPS32: ori t2,t2,0xff 96; MIPS32: and v0,v0,t2 97; MIPS32: or v1,v1,v0 98; MIPS32: move v0,a1 99; MIPS32: srl v0,v0,0x10 100; MIPS32: andi v0,v0,0xff 101; MIPS32: andi v0,v0,0x1 102; MIPS32: sll v0,v0,0x1f 103; MIPS32: sra v0,v0,0x1f 104; MIPS32: andi v0,v0,0xff 105; MIPS32: sll v0,v0,0x10 106; MIPS32: lui t2,0xff00 107; MIPS32: ori t2,t2,0xffff 108; MIPS32: and v1,v1,t2 109; MIPS32: or v0,v0,v1 110; MIPS32: srl a1,a1,0x18 111; MIPS32: andi a1,a1,0x1 112; MIPS32: sll a1,a1,0x1f 113; MIPS32: sra a1,a1,0x1f 114; MIPS32: sll a1,a1,0x18 115; MIPS32: sll v0,v0,0x8 116; MIPS32: srl v0,v0,0x8 117; MIPS32: or a1,a1,v0 118; MIPS32: move v0,a2 119; MIPS32: andi v0,v0,0xff 120; MIPS32: andi v0,v0,0x1 121; MIPS32: sll v0,v0,0x1f 122; MIPS32: sra v0,v0,0x1f 123; MIPS32: andi v0,v0,0xff 124; MIPS32: srl t0,t0,0x8 125; MIPS32: sll t0,t0,0x8 126; MIPS32: or v0,v0,t0 127; MIPS32: move v1,a2 128; MIPS32: srl v1,v1,0x8 129; MIPS32: andi v1,v1,0xff 130; MIPS32: andi v1,v1,0x1 131; MIPS32: sll v1,v1,0x1f 132; MIPS32: sra v1,v1,0x1f 133; MIPS32: andi v1,v1,0xff 134; MIPS32: sll v1,v1,0x8 135; MIPS32: lui t0,0xffff 136; MIPS32: ori t0,t0,0xff 137; MIPS32: and v0,v0,t0 138; MIPS32: or v1,v1,v0 139; MIPS32: move v0,a2 140; MIPS32: srl v0,v0,0x10 141; MIPS32: andi v0,v0,0xff 142; MIPS32: andi v0,v0,0x1 143; MIPS32: sll v0,v0,0x1f 144; MIPS32: sra v0,v0,0x1f 145; MIPS32: andi v0,v0,0xff 146; MIPS32: sll v0,v0,0x10 147; MIPS32: lui t0,0xff00 148; MIPS32: ori t0,t0,0xffff 149; MIPS32: and v1,v1,t0 150; MIPS32: or v0,v0,v1 151; MIPS32: srl a2,a2,0x18 152; MIPS32: andi a2,a2,0x1 153; MIPS32: sll a2,a2,0x1f 154; MIPS32: sra a2,a2,0x1f 155; MIPS32: sll a2,a2,0x18 156; MIPS32: sll v0,v0,0x8 157; MIPS32: srl v0,v0,0x8 158; MIPS32: or a2,a2,v0 159; MIPS32: move v0,a3 160; MIPS32: andi v0,v0,0xff 161; MIPS32: andi v0,v0,0x1 162; MIPS32: sll v0,v0,0x1f 163; MIPS32: sra v0,v0,0x1f 164; MIPS32: andi v0,v0,0xff 165; MIPS32: srl t1,t1,0x8 166; MIPS32: sll t1,t1,0x8 167; MIPS32: or v0,v0,t1 168; MIPS32: move v1,a3 169; MIPS32: srl v1,v1,0x8 170; MIPS32: andi v1,v1,0xff 171; MIPS32: andi v1,v1,0x1 172; MIPS32: sll v1,v1,0x1f 173; MIPS32: sra v1,v1,0x1f 174; MIPS32: andi v1,v1,0xff 175; MIPS32: sll v1,v1,0x8 176; MIPS32: lui t0,0xffff 177; MIPS32: ori t0,t0,0xff 178; MIPS32: and v0,v0,t0 179; MIPS32: or v1,v1,v0 180; MIPS32: move v0,a3 181; MIPS32: srl v0,v0,0x10 182; MIPS32: andi v0,v0,0xff 183; MIPS32: andi v0,v0,0x1 184; MIPS32: sll v0,v0,0x1f 185; MIPS32: sra v0,v0,0x1f 186; MIPS32: andi v0,v0,0xff 187; MIPS32: sll v0,v0,0x10 188; MIPS32: lui t0,0xff00 189; MIPS32: ori t0,t0,0xffff 190; MIPS32: and v1,v1,t0 191; MIPS32: or v0,v0,v1 192; MIPS32: srl a3,a3,0x18 193; MIPS32: andi a3,a3,0x1 194; MIPS32: sll a3,a3,0x1f 195; MIPS32: sra a3,a3,0x1f 196; MIPS32: sll a3,a3,0x18 197; MIPS32: sll v0,v0,0x8 198; MIPS32: srl v0,v0,0x8 199; MIPS32: or a3,a3,v0 200} 201 202define internal <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) { 203entry: 204 %res = sext <8 x i1> %arg to <8 x i16> 205 ret <8 x i16> %res 206 207; CHECK-LABEL: test_sext_v8i1_to_v8i16 208; X8632: psllw {{.*}},0xf 209; X8632: psraw {{.*}},0xf 210; ARM32: vshl.s16 211; ARM32-NEXT: vshr.s16 212; MIPS32: move v0,zero 213; MIPS32: move v1,zero 214; MIPS32: move t0,zero 215; MIPS32: move t1,zero 216; MIPS32: move t2,a0 217; MIPS32: andi t2,t2,0xffff 218; MIPS32: andi t2,t2,0x1 219; MIPS32: sll t2,t2,0x1f 220; MIPS32: sra t2,t2,0x1f 221; MIPS32: andi t2,t2,0xffff 222; MIPS32: srl v0,v0,0x10 223; MIPS32: sll v0,v0,0x10 224; MIPS32: or t2,t2,v0 225; MIPS32: srl a0,a0,0x10 226; MIPS32: andi a0,a0,0x1 227; MIPS32: sll a0,a0,0x1f 228; MIPS32: sra a0,a0,0x1f 229; MIPS32: sll a0,a0,0x10 230; MIPS32: sll t2,t2,0x10 231; MIPS32: srl t2,t2,0x10 232; MIPS32: or a0,a0,t2 233; MIPS32: move v0,a1 234; MIPS32: andi v0,v0,0xffff 235; MIPS32: andi v0,v0,0x1 236; MIPS32: sll v0,v0,0x1f 237; MIPS32: sra v0,v0,0x1f 238; MIPS32: andi v0,v0,0xffff 239; MIPS32: srl v1,v1,0x10 240; MIPS32: sll v1,v1,0x10 241; MIPS32: or v0,v0,v1 242; MIPS32: srl a1,a1,0x10 243; MIPS32: andi a1,a1,0x1 244; MIPS32: sll a1,a1,0x1f 245; MIPS32: sra a1,a1,0x1f 246; MIPS32: sll a1,a1,0x10 247; MIPS32: sll v0,v0,0x10 248; MIPS32: srl v0,v0,0x10 249; MIPS32: or a1,a1,v0 250; MIPS32: move v0,a2 251; MIPS32: andi v0,v0,0xffff 252; MIPS32: andi v0,v0,0x1 253; MIPS32: sll v0,v0,0x1f 254; MIPS32: sra v0,v0,0x1f 255; MIPS32: andi v0,v0,0xffff 256; MIPS32: srl t0,t0,0x10 257; MIPS32: sll t0,t0,0x10 258; MIPS32: or v0,v0,t0 259; MIPS32: srl a2,a2,0x10 260; MIPS32: andi a2,a2,0x1 261; MIPS32: sll a2,a2,0x1f 262; MIPS32: sra a2,a2,0x1f 263; MIPS32: sll a2,a2,0x10 264; MIPS32: sll v0,v0,0x10 265; MIPS32: srl v0,v0,0x10 266; MIPS32: or a2,a2,v0 267; MIPS32: move v0,a3 268; MIPS32: andi v0,v0,0xffff 269; MIPS32: andi v0,v0,0x1 270; MIPS32: sll v0,v0,0x1f 271; MIPS32: sra v0,v0,0x1f 272; MIPS32: andi v0,v0,0xffff 273; MIPS32: srl t1,t1,0x10 274; MIPS32: sll t1,t1,0x10 275; MIPS32: or v0,v0,t1 276; MIPS32: srl a3,a3,0x10 277; MIPS32: andi a3,a3,0x1 278; MIPS32: sll a3,a3,0x1f 279; MIPS32: sra a3,a3,0x1f 280; MIPS32: sll a3,a3,0x10 281; MIPS32: sll v0,v0,0x10 282; MIPS32: srl v0,v0,0x10 283; MIPS32: or a3,a3,v0 284} 285 286define internal <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) { 287entry: 288 %res = sext <4 x i1> %arg to <4 x i32> 289 ret <4 x i32> %res 290 291; CHECK-LABEL: test_sext_v4i1_to_v4i32 292; X8632: pslld {{.*}},0x1f 293; X8632: psrad {{.*}},0x1f 294; ARM32: vshl.s32 295; ARM32-NEXT: vshr.s32 296; MIPS32: andi a0,a0,0x1 297; MIPS32: sll a0,a0,0x1f 298; MIPS32: sra a0,a0,0x1f 299; MIPS32: andi a1,a1,0x1 300; MIPS32: sll a1,a1,0x1f 301; MIPS32: sra a1,a1,0x1f 302; MIPS32: andi a2,a2,0x1 303; MIPS32: sll a2,a2,0x1f 304; MIPS32: sra a2,a2,0x1f 305; MIPS32: andi a3,a3,0x1 306; MIPS32: sll a3,a3,0x1f 307; MIPS32: sra a3,a3,0x1f 308} 309 310; zext operations 311 312define internal <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) { 313entry: 314 %res = zext <16 x i1> %arg to <16 x i8> 315 ret <16 x i8> %res 316 317; CHECK-LABEL: test_zext_v16i1_to_v16i8 318; X8632: pxor 319; X8632: pcmpeqb 320; X8632: psubb 321; X8632: pand 322; ARM32: vmov.i8 [[S:.*]], #1 323; ARM32-NEXT: vand {{.*}}, [[S]] 324; MIPS32: move t2,a0 325; MIPS32: andi t2,t2,0xff 326; MIPS32: andi t2,t2,0x1 327; MIPS32: andi t2,t2,0x1 328; MIPS32: andi t2,t2,0xff 329; MIPS32: srl v0,v0,0x8 330; MIPS32: sll v0,v0,0x8 331; MIPS32: or t2,t2,v0 332; MIPS32: move v0,a0 333; MIPS32: srl v0,v0,0x8 334; MIPS32: andi v0,v0,0xff 335; MIPS32: andi v0,v0,0x1 336; MIPS32: andi v0,v0,0x1 337; MIPS32: andi v0,v0,0xff 338; MIPS32: sll v0,v0,0x8 339; MIPS32: lui t3,0xffff 340; MIPS32: ori t3,t3,0xff 341; MIPS32: and t2,t2,t3 342; MIPS32: or v0,v0,t2 343; MIPS32: move t2,a0 344; MIPS32: srl t2,t2,0x10 345; MIPS32: andi t2,t2,0xff 346; MIPS32: andi t2,t2,0x1 347; MIPS32: andi t2,t2,0x1 348; MIPS32: andi t2,t2,0xff 349; MIPS32: sll t2,t2,0x10 350; MIPS32: lui t3,0xff00 351; MIPS32: ori t3,t3,0xffff 352; MIPS32: and v0,v0,t3 353; MIPS32: or t2,t2,v0 354; MIPS32: srl a0,a0,0x18 355; MIPS32: andi a0,a0,0x1 356; MIPS32: andi a0,a0,0x1 357; MIPS32: sll a0,a0,0x18 358; MIPS32: sll t2,t2,0x8 359; MIPS32: srl t2,t2,0x8 360; MIPS32: or a0,a0,t2 361; MIPS32: move v0,a1 362; MIPS32: andi v0,v0,0xff 363; MIPS32: andi v0,v0,0x1 364; MIPS32: andi v0,v0,0x1 365; MIPS32: andi v0,v0,0xff 366; MIPS32: srl v1,v1,0x8 367; MIPS32: sll v1,v1,0x8 368; MIPS32: or v0,v0,v1 369; MIPS32: move v1,a1 370; MIPS32: srl v1,v1,0x8 371; MIPS32: andi v1,v1,0xff 372; MIPS32: andi v1,v1,0x1 373; MIPS32: andi v1,v1,0x1 374; MIPS32: andi v1,v1,0xff 375; MIPS32: sll v1,v1,0x8 376; MIPS32: lui t2,0xffff 377; MIPS32: ori t2,t2,0xff 378; MIPS32: and v0,v0,t2 379; MIPS32: or v1,v1,v0 380; MIPS32: move v0,a1 381; MIPS32: srl v0,v0,0x10 382; MIPS32: andi v0,v0,0xff 383; MIPS32: andi v0,v0,0x1 384; MIPS32: andi v0,v0,0x1 385; MIPS32: andi v0,v0,0xff 386; MIPS32: sll v0,v0,0x10 387; MIPS32: lui t2,0xff00 388; MIPS32: ori t2,t2,0xffff 389; MIPS32: and v1,v1,t2 390; MIPS32: or v0,v0,v1 391; MIPS32: srl a1,a1,0x18 392; MIPS32: andi a1,a1,0x1 393; MIPS32: andi a1,a1,0x1 394; MIPS32: sll a1,a1,0x18 395; MIPS32: sll v0,v0,0x8 396; MIPS32: srl v0,v0,0x8 397; MIPS32: or a1,a1,v0 398; MIPS32: move v0,a2 399; MIPS32: andi v0,v0,0xff 400; MIPS32: andi v0,v0,0x1 401; MIPS32: andi v0,v0,0x1 402; MIPS32: andi v0,v0,0xff 403; MIPS32: srl t0,t0,0x8 404; MIPS32: sll t0,t0,0x8 405; MIPS32: or v0,v0,t0 406; MIPS32: move v1,a2 407; MIPS32: srl v1,v1,0x8 408; MIPS32: andi v1,v1,0xff 409; MIPS32: andi v1,v1,0x1 410; MIPS32: andi v1,v1,0x1 411; MIPS32: andi v1,v1,0xff 412; MIPS32: sll v1,v1,0x8 413; MIPS32: lui t0,0xffff 414; MIPS32: ori t0,t0,0xff 415; MIPS32: and v0,v0,t0 416; MIPS32: or v1,v1,v0 417; MIPS32: move v0,a2 418; MIPS32: srl v0,v0,0x10 419; MIPS32: andi v0,v0,0xff 420; MIPS32: andi v0,v0,0x1 421; MIPS32: andi v0,v0,0x1 422; MIPS32: andi v0,v0,0xff 423; MIPS32: sll v0,v0,0x10 424; MIPS32: lui t0,0xff00 425; MIPS32: ori t0,t0,0xffff 426; MIPS32: and v1,v1,t0 427; MIPS32: or v0,v0,v1 428; MIPS32: srl a2,a2,0x18 429; MIPS32: andi a2,a2,0x1 430; MIPS32: andi a2,a2,0x1 431; MIPS32: sll a2,a2,0x18 432; MIPS32: sll v0,v0,0x8 433; MIPS32: srl v0,v0,0x8 434; MIPS32: or a2,a2,v0 435; MIPS32: move v0,a3 436; MIPS32: andi v0,v0,0xff 437; MIPS32: andi v0,v0,0x1 438; MIPS32: andi v0,v0,0x1 439; MIPS32: andi v0,v0,0xff 440; MIPS32: srl t1,t1,0x8 441; MIPS32: sll t1,t1,0x8 442; MIPS32: or v0,v0,t1 443; MIPS32: move v1,a3 444; MIPS32: srl v1,v1,0x8 445; MIPS32: andi v1,v1,0xff 446; MIPS32: andi v1,v1,0x1 447; MIPS32: andi v1,v1,0x1 448; MIPS32: andi v1,v1,0xff 449; MIPS32: sll v1,v1,0x8 450; MIPS32: lui t0,0xffff 451; MIPS32: ori t0,t0,0xff 452; MIPS32: and v0,v0,t0 453; MIPS32: or v1,v1,v0 454; MIPS32: move v0,a3 455; MIPS32: srl v0,v0,0x10 456; MIPS32: andi v0,v0,0xff 457; MIPS32: andi v0,v0,0x1 458; MIPS32: andi v0,v0,0x1 459; MIPS32: andi v0,v0,0xff 460; MIPS32: sll v0,v0,0x10 461; MIPS32: lui t0,0xff00 462; MIPS32: ori t0,t0,0xffff 463; MIPS32: and v1,v1,t0 464; MIPS32: or v0,v0,v1 465; MIPS32: srl a3,a3,0x18 466; MIPS32: andi a3,a3,0x1 467; MIPS32: andi a3,a3,0x1 468; MIPS32: sll a3,a3,0x18 469; MIPS32: sll v0,v0,0x8 470; MIPS32: srl v0,v0,0x8 471; MIPS32: or a3,a3,v0 472} 473 474define internal <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) { 475entry: 476 %res = zext <8 x i1> %arg to <8 x i16> 477 ret <8 x i16> %res 478 479; CHECK-LABEL: test_zext_v8i1_to_v8i16 480; X8632: pxor 481; X8632: pcmpeqw 482; X8632: psubw 483; X8632: pand 484; ARM32: vmov.i16 [[S:.*]], #1 485; ARM32-NEXT: vand {{.*}}, [[S]] 486; MIPS32: move t2,a0 487; MIPS32: andi t2,t2,0xffff 488; MIPS32: andi t2,t2,0x1 489; MIPS32: andi t2,t2,0x1 490; MIPS32: andi t2,t2,0xffff 491; MIPS32: srl v0,v0,0x10 492; MIPS32: sll v0,v0,0x10 493; MIPS32: or t2,t2,v0 494; MIPS32: srl a0,a0,0x10 495; MIPS32: andi a0,a0,0x1 496; MIPS32: andi a0,a0,0x1 497; MIPS32: sll a0,a0,0x10 498; MIPS32: sll t2,t2,0x10 499; MIPS32: srl t2,t2,0x10 500; MIPS32: or a0,a0,t2 501; MIPS32: move v0,a1 502; MIPS32: andi v0,v0,0xffff 503; MIPS32: andi v0,v0,0x1 504; MIPS32: andi v0,v0,0x1 505; MIPS32: andi v0,v0,0xffff 506; MIPS32: srl v1,v1,0x10 507; MIPS32: sll v1,v1,0x10 508; MIPS32: or v0,v0,v1 509; MIPS32: srl a1,a1,0x10 510; MIPS32: andi a1,a1,0x1 511; MIPS32: andi a1,a1,0x1 512; MIPS32: sll a1,a1,0x10 513; MIPS32: sll v0,v0,0x10 514; MIPS32: srl v0,v0,0x10 515; MIPS32: or a1,a1,v0 516; MIPS32: move v0,a2 517; MIPS32: andi v0,v0,0xffff 518; MIPS32: andi v0,v0,0x1 519; MIPS32: andi v0,v0,0x1 520; MIPS32: andi v0,v0,0xffff 521; MIPS32: srl t0,t0,0x10 522; MIPS32: sll t0,t0,0x10 523; MIPS32: or v0,v0,t0 524; MIPS32: srl a2,a2,0x10 525; MIPS32: andi a2,a2,0x1 526; MIPS32: andi a2,a2,0x1 527; MIPS32: sll a2,a2,0x10 528; MIPS32: sll v0,v0,0x10 529; MIPS32: srl v0,v0,0x10 530; MIPS32: or a2,a2,v0 531; MIPS32: move v0,a3 532; MIPS32: andi v0,v0,0xffff 533; MIPS32: andi v0,v0,0x1 534; MIPS32: andi v0,v0,0x1 535; MIPS32: andi v0,v0,0xffff 536; MIPS32: srl t1,t1,0x10 537; MIPS32: sll t1,t1,0x10 538; MIPS32: or v0,v0,t1 539; MIPS32: srl a3,a3,0x10 540; MIPS32: andi a3,a3,0x1 541; MIPS32: andi a3,a3,0x1 542; MIPS32: sll a3,a3,0x10 543; MIPS32: sll v0,v0,0x10 544; MIPS32: srl v0,v0,0x10 545; MIPS32: or a3,a3,v0 546} 547 548define internal <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) { 549entry: 550 %res = zext <4 x i1> %arg to <4 x i32> 551 ret <4 x i32> %res 552 553; CHECK-LABEL: test_zext_v4i1_to_v4i32 554; X8632: pxor 555; X8632: pcmpeqd 556; X8632: psubd 557; X8632: pand 558; ARM32: vmov.i32 [[S:.*]], #1 559; ARM32-NEXT: vand {{.*}}, [[S]] 560; MIPS32: andi a0,a0,0x1 561; MIPS32: andi a0,a0,0x1 562; MIPS32: andi a1,a1,0x1 563; MIPS32: andi a1,a1,0x1 564; MIPS32: andi a2,a2,0x1 565; MIPS32: andi a2,a2,0x1 566; MIPS32: andi a3,a3,0x1 567; MIPS32: andi a3,a3,0x1 568} 569 570; trunc operations 571 572define internal <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) { 573entry: 574 %res = trunc <16 x i8> %arg to <16 x i1> 575 ret <16 x i1> %res 576 577; CHECK-LABEL: test_trunc_v16i8_to_v16i1 578; X8632: pxor 579; X8632: pcmpeqb 580; X8632: psubb 581; X8632: pand 582; MIPS32: move t2,a0 583; MIPS32: andi t2,t2,0xff 584; MIPS32: andi t2,t2,0x1 585; MIPS32: andi t2,t2,0xff 586; MIPS32: srl v0,v0,0x8 587; MIPS32: sll v0,v0,0x8 588; MIPS32: or t2,t2,v0 589; MIPS32: move v0,a0 590; MIPS32: srl v0,v0,0x8 591; MIPS32: andi v0,v0,0xff 592; MIPS32: andi v0,v0,0x1 593; MIPS32: andi v0,v0,0xff 594; MIPS32: sll v0,v0,0x8 595; MIPS32: lui t3,0xffff 596; MIPS32: ori t3,t3,0xff 597; MIPS32: and t2,t2,t3 598; MIPS32: or v0,v0,t2 599; MIPS32: move t2,a0 600; MIPS32: srl t2,t2,0x10 601; MIPS32: andi t2,t2,0xff 602; MIPS32: andi t2,t2,0x1 603; MIPS32: andi t2,t2,0xff 604; MIPS32: sll t2,t2,0x10 605; MIPS32: lui t3,0xff00 606; MIPS32: ori t3,t3,0xffff 607; MIPS32: and v0,v0,t3 608; MIPS32: or t2,t2,v0 609; MIPS32: srl a0,a0,0x18 610; MIPS32: andi a0,a0,0x1 611; MIPS32: sll a0,a0,0x18 612; MIPS32: sll t2,t2,0x8 613; MIPS32: srl t2,t2,0x8 614; MIPS32: or a0,a0,t2 615; MIPS32: move v0,a1 616; MIPS32: andi v0,v0,0xff 617; MIPS32: andi v0,v0,0x1 618; MIPS32: andi v0,v0,0xff 619; MIPS32: srl v1,v1,0x8 620; MIPS32: sll v1,v1,0x8 621; MIPS32: or v0,v0,v1 622; MIPS32: move v1,a1 623; MIPS32: srl v1,v1,0x8 624; MIPS32: andi v1,v1,0xff 625; MIPS32: andi v1,v1,0x1 626; MIPS32: andi v1,v1,0xff 627; MIPS32: sll v1,v1,0x8 628; MIPS32: lui t2,0xffff 629; MIPS32: ori t2,t2,0xff 630; MIPS32: and v0,v0,t2 631; MIPS32: or v1,v1,v0 632; MIPS32: move v0,a1 633; MIPS32: srl v0,v0,0x10 634; MIPS32: andi v0,v0,0xff 635; MIPS32: andi v0,v0,0x1 636; MIPS32: andi v0,v0,0xff 637; MIPS32: sll v0,v0,0x10 638; MIPS32: lui t2,0xff00 639; MIPS32: ori t2,t2,0xffff 640; MIPS32: and v1,v1,t2 641; MIPS32: or v0,v0,v1 642; MIPS32: srl a1,a1,0x18 643; MIPS32: andi a1,a1,0x1 644; MIPS32: sll a1,a1,0x18 645; MIPS32: sll v0,v0,0x8 646; MIPS32: srl v0,v0,0x8 647; MIPS32: or a1,a1,v0 648; MIPS32: move v0,a2 649; MIPS32: andi v0,v0,0xff 650; MIPS32: andi v0,v0,0x1 651; MIPS32: andi v0,v0,0xff 652; MIPS32: srl t0,t0,0x8 653; MIPS32: sll t0,t0,0x8 654; MIPS32: or v0,v0,t0 655; MIPS32: move v1,a2 656; MIPS32: srl v1,v1,0x8 657; MIPS32: andi v1,v1,0xff 658; MIPS32: andi v1,v1,0x1 659; MIPS32: andi v1,v1,0xff 660; MIPS32: sll v1,v1,0x8 661; MIPS32: lui t0,0xffff 662; MIPS32: ori t0,t0,0xff 663; MIPS32: and v0,v0,t0 664; MIPS32: or v1,v1,v0 665; MIPS32: move v0,a2 666; MIPS32: srl v0,v0,0x10 667; MIPS32: andi v0,v0,0xff 668; MIPS32: andi v0,v0,0x1 669; MIPS32: andi v0,v0,0xff 670; MIPS32: sll v0,v0,0x10 671; MIPS32: lui t0,0xff00 672; MIPS32: ori t0,t0,0xffff 673; MIPS32: and v1,v1,t0 674; MIPS32: or v0,v0,v1 675; MIPS32: srl a2,a2,0x18 676; MIPS32: andi a2,a2,0x1 677; MIPS32: sll a2,a2,0x18 678; MIPS32: sll v0,v0,0x8 679; MIPS32: srl v0,v0,0x8 680; MIPS32: or a2,a2,v0 681; MIPS32: move v0,a3 682; MIPS32: andi v0,v0,0xff 683; MIPS32: andi v0,v0,0x1 684; MIPS32: andi v0,v0,0xff 685; MIPS32: srl t1,t1,0x8 686; MIPS32: sll t1,t1,0x8 687; MIPS32: or v0,v0,t1 688; MIPS32: move v1,a3 689; MIPS32: srl v1,v1,0x8 690; MIPS32: andi v1,v1,0xff 691; MIPS32: andi v1,v1,0x1 692; MIPS32: andi v1,v1,0xff 693; MIPS32: sll v1,v1,0x8 694; MIPS32: lui t0,0xffff 695; MIPS32: ori t0,t0,0xff 696; MIPS32: and v0,v0,t0 697; MIPS32: or v1,v1,v0 698; MIPS32: move v0,a3 699; MIPS32: srl v0,v0,0x10 700; MIPS32: andi v0,v0,0xff 701; MIPS32: andi v0,v0,0x1 702; MIPS32: andi v0,v0,0xff 703; MIPS32: sll v0,v0,0x10 704; MIPS32: lui t0,0xff00 705; MIPS32: ori t0,t0,0xffff 706; MIPS32: and v1,v1,t0 707; MIPS32: or v0,v0,v1 708; MIPS32: srl a3,a3,0x18 709; MIPS32: andi a3,a3,0x1 710; MIPS32: sll a3,a3,0x18 711; MIPS32: sll v0,v0,0x8 712; MIPS32: srl v0,v0,0x8 713; MIPS32: or a3,a3,v0 714} 715 716define internal <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) { 717entry: 718 %res = trunc <8 x i16> %arg to <8 x i1> 719 ret <8 x i1> %res 720 721; CHECK-LABEL: test_trunc_v8i16_to_v8i1 722; X8632: pxor 723; X8632: pcmpeqw 724; X8632: psubw 725; X8632: pand 726; MIPS32: move t2,a0 727; MIPS32: andi t2,t2,0xffff 728; MIPS32: andi t2,t2,0xffff 729; MIPS32: srl v0,v0,0x10 730; MIPS32: sll v0,v0,0x10 731; MIPS32: or t2,t2,v0 732; MIPS32: srl a0,a0,0x10 733; MIPS32: sll a0,a0,0x10 734; MIPS32: sll t2,t2,0x10 735; MIPS32: srl t2,t2,0x10 736; MIPS32: or a0,a0,t2 737; MIPS32: move v0,a1 738; MIPS32: andi v0,v0,0xffff 739; MIPS32: andi v0,v0,0xffff 740; MIPS32: srl v1,v1,0x10 741; MIPS32: sll v1,v1,0x10 742; MIPS32: or v0,v0,v1 743; MIPS32: srl a1,a1,0x10 744; MIPS32: sll a1,a1,0x10 745; MIPS32: sll v0,v0,0x10 746; MIPS32: srl v0,v0,0x10 747; MIPS32: or a1,a1,v0 748; MIPS32: move v0,a2 749; MIPS32: andi v0,v0,0xffff 750; MIPS32: andi v0,v0,0xffff 751; MIPS32: srl t0,t0,0x10 752; MIPS32: sll t0,t0,0x10 753; MIPS32: or v0,v0,t0 754; MIPS32: srl a2,a2,0x10 755; MIPS32: sll a2,a2,0x10 756; MIPS32: sll v0,v0,0x10 757; MIPS32: srl v0,v0,0x10 758; MIPS32: or a2,a2,v0 759; MIPS32: move v0,a3 760; MIPS32: andi v0,v0,0xffff 761; MIPS32: andi v0,v0,0xffff 762; MIPS32: srl t1,t1,0x10 763; MIPS32: sll t1,t1,0x10 764; MIPS32: or v0,v0,t1 765; MIPS32: srl a3,a3,0x10 766; MIPS32: sll a3,a3,0x10 767; MIPS32: sll v0,v0,0x10 768; MIPS32: srl v0,v0,0x10 769; MIPS32: or a3,a3,v0 770} 771 772define internal <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) { 773entry: 774 %res = trunc <4 x i32> %arg to <4 x i1> 775 ret <4 x i1> %res 776 777; CHECK-LABEL: test_trunc_v4i32_to_v4i1 778; X8632: pxor 779; X8632: pcmpeqd 780; X8632: psubd 781; X8632: pand 782; MIPS32: move v0,a0 783; MIPS32: move v1,a1 784; MIPS32: move a0,a2 785; MIPS32: move a1,a3 786} 787 788; fpto[us]i operations 789 790define internal <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) { 791entry: 792 %res = fptosi <4 x float> %arg to <4 x i32> 793 ret <4 x i32> %res 794 795; CHECK-LABEL: test_fptosi_v4f32_to_v4i32 796; X8632: cvttps2dq 797; ARM32: vcvt.s32.f32 798; MIPS32: trunc.w.s $f0,$f0 799; MIPS32: trunc.w.s $f0,$f0 800; MIPS32: trunc.w.s $f0,$f0 801; MIPS32: trunc.w.s $f0,$f0 802} 803 804define internal <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) { 805entry: 806 %res = fptoui <4 x float> %arg to <4 x i32> 807 ret <4 x i32> %res 808 809; CHECK-LABEL: test_fptoui_v4f32_to_v4i32 810; X8632: call {{.*}} R_{{.*}} __Sz_fptoui_4xi32_f32 811; ARM32: vcvt.u32.f32 812; MIPS32: trunc.w.s $f0,$f0 813; MIPS32: trunc.w.s $f0,$f0 814; MIPS32: trunc.w.s $f0,$f0 815; MIPS32: trunc.w.s $f0,$f0 816} 817 818; [su]itofp operations 819 820define internal <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) { 821entry: 822 %res = sitofp <4 x i32> %arg to <4 x float> 823 ret <4 x float> %res 824 825; CHECK-LABEL: test_sitofp_v4i32_to_v4f32 826; X8632: cvtdq2ps 827; ARM32: vcvt.f32.s32 828; MIPS32: cvt.s.w $f0,$f0 829; MIPS32: cvt.s.w $f0,$f0 830; MIPS32: cvt.s.w $f0,$f0 831; MIPS32: cvt.s.w $f0,$f0 832 833} 834 835define internal <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { 836entry: 837 %res = uitofp <4 x i32> %arg to <4 x float> 838 ret <4 x float> %res 839 840; CHECK-LABEL: test_uitofp_v4i32_to_v4f32 841; X8632: call {{.*}} R_{{.*}} __Sz_uitofp_4xi32_4xf32 842; ARM32: vcvt.f32.u32 843; MIPS32: cvt.s.w $f0,$f0 844; MIPS32: cvt.s.w $f0,$f0 845; MIPS32: cvt.s.w $f0,$f0 846; MIPS32: cvt.s.w $f0,$f0 847} 848