1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/arch/clock.h>
8 #include <asm/io.h>
9 #include <asm/arch/fsl_serdes.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ls102xa_soc.h>
12 #include <asm/arch/ls102xa_stream_id.h>
13 #include <fsl_csu.h>
14
15 struct liodn_id_table sec_liodn_tbl[] = {
16 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
17 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
18 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
19 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
20 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
21 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
22 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
23 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
24 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
25 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
26 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
27 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
28 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
29 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
30 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
31 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
32 };
33
34 struct smmu_stream_id dev_stream_id[] = {
35 { 0x100, 0x01, "ETSEC MAC1" },
36 { 0x104, 0x02, "ETSEC MAC2" },
37 { 0x108, 0x03, "ETSEC MAC3" },
38 { 0x10c, 0x04, "PEX1" },
39 { 0x110, 0x05, "PEX2" },
40 { 0x114, 0x06, "qDMA" },
41 { 0x118, 0x07, "SATA" },
42 { 0x11c, 0x08, "USB3" },
43 { 0x120, 0x09, "QE" },
44 { 0x124, 0x0a, "eSDHC" },
45 { 0x128, 0x0b, "eMA" },
46 { 0x14c, 0x0c, "2D-ACE" },
47 { 0x150, 0x0d, "USB2" },
48 { 0x18c, 0x0e, "DEBUG" },
49 };
50
get_soc_major_rev(void)51 unsigned int get_soc_major_rev(void)
52 {
53 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
54 unsigned int svr, major;
55
56 svr = in_be32(&gur->svr);
57 major = SVR_MAJ(svr);
58
59 return major;
60 }
61
erratum_a009008(void)62 static void erratum_a009008(void)
63 {
64 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
65 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
66
67 clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
68 0xF << 6,
69 SCFG_USB_TXVREFTUNE << 6);
70 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
71 }
72
erratum_a009798(void)73 static void erratum_a009798(void)
74 {
75 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
76 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
77
78 clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
79 SCFG_USB_SQRXTUNE_MASK << 23);
80 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
81 }
82
erratum_a008997(void)83 static void erratum_a008997(void)
84 {
85 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
86 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
87
88 clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
89 SCFG_USB_PCSTXSWINGFULL_MASK,
90 SCFG_USB_PCSTXSWINGFULL_VAL);
91 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
92 }
93
erratum_a009007(void)94 static void erratum_a009007(void)
95 {
96 #ifdef CONFIG_SYS_FSL_ERRATUM_A009007
97 void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
98
99 out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
100 out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
101 out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
102 out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
103 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
104 }
105
s_init(void)106 void s_init(void)
107 {
108 }
109
110 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315(void)111 void erratum_a010315(void)
112 {
113 int i;
114
115 for (i = PCIE1; i <= PCIE2; i++)
116 if (!is_serdes_configured(i)) {
117 debug("PCIe%d: disabled all R/W permission!\n", i);
118 set_pcie_ns_access(i, 0);
119 }
120 }
121 #endif
122
arch_soc_init(void)123 int arch_soc_init(void)
124 {
125 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
126 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
127 CONFIG_SYS_CCI400_OFFSET);
128 unsigned int major;
129
130 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
131 enable_layerscape_ns_access();
132 #endif
133
134 #ifdef CONFIG_FSL_QSPI
135 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
136 #endif
137
138 #ifdef CONFIG_VIDEO_FSL_DCU_FB
139 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
140 #endif
141
142 /* Configure Little endian for SAI, ASRC and SPDIF */
143 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
144
145 /*
146 * Enable snoop requests and DVM message requests for
147 * All the slave insterfaces.
148 */
149 out_le32(&cci->slave[0].snoop_ctrl,
150 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
151 out_le32(&cci->slave[1].snoop_ctrl,
152 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
153 out_le32(&cci->slave[2].snoop_ctrl,
154 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
155 out_le32(&cci->slave[4].snoop_ctrl,
156 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
157
158 major = get_soc_major_rev();
159 if (major == SOC_MAJOR_VER_1_0) {
160 /*
161 * Set CCI-400 Slave interface S1, S2 Shareable Override
162 * Register All transactions are treated as non-shareable
163 */
164 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
165 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
166
167 /* Workaround for the issue that DDR could not respond to
168 * barrier transaction which is generated by executing DSB/ISB
169 * instruction. Set CCI-400 control override register to
170 * terminate the barrier transaction. After DDR is initialized,
171 * allow barrier transaction to DDR again */
172 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
173 }
174
175 /* Enable all the snoop signal for various masters */
176 out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
177 SCFG_SNPCNFGCR_DCU_RD_WR |
178 SCFG_SNPCNFGCR_SATA_RD_WR |
179 SCFG_SNPCNFGCR_USB3_RD_WR |
180 SCFG_SNPCNFGCR_DBG_RD_WR |
181 SCFG_SNPCNFGCR_EDMA_SNP);
182
183 /*
184 * Memory controller require a register write before being enabled.
185 * Affects: DDR
186 * Register: EDDRTQCFG
187 * Description: Memory controller performance is not optimal with
188 * default internal target queue register values.
189 * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
190 */
191 out_be32(&scfg->eddrtqcfg, 0x63b20042);
192
193 /* Erratum */
194 erratum_a009008();
195 erratum_a009798();
196 erratum_a008997();
197 erratum_a009007();
198
199 return 0;
200 }
201
ls102xa_smmu_stream_id_init(void)202 int ls102xa_smmu_stream_id_init(void)
203 {
204 ls1021x_config_caam_stream_id(sec_liodn_tbl,
205 ARRAY_SIZE(sec_liodn_tbl));
206
207 ls102xa_config_smmu_stream_id(dev_stream_id,
208 ARRAY_SIZE(dev_stream_id));
209
210 return 0;
211 }
212