1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 *
5 * Copyright 2016 Google, Inc
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <ram.h>
13 #include <regmap.h>
14 #include <reset.h>
15 #include <asm/io.h>
16 #include <asm/arch/scu_ast2500.h>
17 #include <asm/arch/sdram_ast2500.h>
18 #include <asm/arch/wdt.h>
19 #include <linux/err.h>
20 #include <linux/kernel.h>
21 #include <dt-bindings/clock/ast2500-scu.h>
22
23 /* These configuration parameters are taken from Aspeed SDK */
24 #define DDR4_MR46_MODE 0x08000000
25 #define DDR4_MR5_MODE 0x400
26 #define DDR4_MR13_MODE 0x101
27 #define DDR4_MR02_MODE 0x410
28 #define DDR4_TRFC 0x45457188
29
30 #define PHY_CFG_SIZE 15
31
32 static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
33 static const struct {
34 u32 index[PHY_CFG_SIZE];
35 u32 value[PHY_CFG_SIZE];
36 } ddr4_phy_config = {
37 .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
38 .value = {
39 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
40 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
41 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
42 },
43 };
44
45 #define SDRAM_MAX_SIZE (1024 * 1024 * 1024)
46 #define SDRAM_MIN_SIZE (128 * 1024 * 1024)
47
48 DECLARE_GLOBAL_DATA_PTR;
49
50 /*
51 * Bandwidth configuration parameters for different SDRAM requests.
52 * These are hardcoded settings taken from Aspeed SDK.
53 */
54 static const u32 ddr_max_grant_params[4] = {
55 0x88448844, 0x24422288, 0x22222222, 0x22222222
56 };
57
58 /*
59 * These registers are not documented by Aspeed at all.
60 * All writes and reads are taken pretty much as is from SDK.
61 */
62 struct ast2500_ddr_phy {
63 u32 phy[117];
64 };
65
66 struct dram_info {
67 struct ram_info info;
68 struct clk ddr_clk;
69 struct ast2500_sdrammc_regs *regs;
70 struct ast2500_scu *scu;
71 struct ast2500_ddr_phy *phy;
72 ulong clock_rate;
73 };
74
ast2500_sdrammc_init_phy(struct ast2500_ddr_phy * phy)75 static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
76 {
77 writel(0, &phy->phy[2]);
78 writel(0, &phy->phy[6]);
79 writel(0, &phy->phy[8]);
80 writel(0, &phy->phy[10]);
81 writel(0, &phy->phy[12]);
82 writel(0, &phy->phy[42]);
83 writel(0, &phy->phy[44]);
84
85 writel(0x86000000, &phy->phy[16]);
86 writel(0x00008600, &phy->phy[17]);
87 writel(0x80000000, &phy->phy[18]);
88 writel(0x80808080, &phy->phy[19]);
89
90 return 0;
91 }
92
ast2500_ddr_phy_init_process(struct dram_info * info)93 static void ast2500_ddr_phy_init_process(struct dram_info *info)
94 {
95 struct ast2500_sdrammc_regs *regs = info->regs;
96
97 writel(0, ®s->phy_ctrl[0]);
98 writel(0x4040, &info->phy->phy[51]);
99
100 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]);
101 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
102 ;
103 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE,
104 ®s->phy_ctrl[0]);
105 }
106
ast2500_sdrammc_set_vref(struct dram_info * info,u32 vref)107 static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
108 {
109 writel(0, &info->regs->phy_ctrl[0]);
110 writel((vref << 8) | 0x6, &info->phy->phy[48]);
111 ast2500_ddr_phy_init_process(info);
112 }
113
ast2500_ddr_cbr_test(struct dram_info * info)114 static int ast2500_ddr_cbr_test(struct dram_info *info)
115 {
116 struct ast2500_sdrammc_regs *regs = info->regs;
117 int i;
118 const u32 test_params = SDRAM_TEST_EN
119 | SDRAM_TEST_ERRSTOP
120 | SDRAM_TEST_TWO_MODES;
121 int ret = 0;
122
123 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) |
124 (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing);
125 writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr);
126 writel(0xff00ff00, ®s->test_init_val);
127 writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) |
128 SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl);
129
130 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE))
131 ;
132
133 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
134 ret = -EIO;
135 } else {
136 for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
137 writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params,
138 ®s->ecc_test_ctrl);
139 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE))
140 ;
141 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
142 ret = -EIO;
143 break;
144 }
145 }
146 }
147
148 writel(0, ®s->refresh_timing);
149 writel(0, ®s->ecc_test_ctrl);
150
151 return ret;
152 }
153
ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info * info)154 static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
155 {
156 int i;
157 int vref_min = 0xff;
158 int vref_max = 0;
159 int range_size = 0;
160
161 for (i = 1; i < 0x40; ++i) {
162 int res;
163
164 ast2500_sdrammc_set_vref(info, i);
165 res = ast2500_ddr_cbr_test(info);
166 if (res < 0) {
167 if (range_size > 0)
168 break;
169 } else {
170 ++range_size;
171 vref_min = min(vref_min, i);
172 vref_max = max(vref_max, i);
173 }
174 }
175
176 /* Pick average setting */
177 ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);
178
179 return 0;
180 }
181
ast2500_sdrammc_get_vga_mem_size(struct dram_info * info)182 static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
183 {
184 size_t vga_mem_size_base = 8 * 1024 * 1024;
185 u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
186 >> SCU_HWSTRAP_VGAMEM_SHIFT;
187
188 return vga_mem_size_base << vga_hwconf;
189 }
190
191 /*
192 * Find out RAM size and save it in dram_info
193 *
194 * The procedure is taken from Aspeed SDK
195 */
ast2500_sdrammc_calc_size(struct dram_info * info)196 static void ast2500_sdrammc_calc_size(struct dram_info *info)
197 {
198 /* The controller supports 128/256/512/1024 MB ram */
199 size_t ram_size = SDRAM_MIN_SIZE;
200 const int write_test_offset = 0x100000;
201 u32 test_pattern = 0xdeadbeef;
202 u32 cap_param = SDRAM_CONF_CAP_1024M;
203 u32 refresh_timing_param = DDR4_TRFC;
204 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
205
206 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
207 ram_size >>= 1) {
208 writel(test_pattern, write_addr_base + (ram_size >> 1));
209 test_pattern = (test_pattern >> 4) | (test_pattern << 28);
210 }
211
212 /* One last write to overwrite all wrapped values */
213 writel(test_pattern, write_addr_base);
214
215 /* Reset the pattern and see which value was really written */
216 test_pattern = 0xdeadbeef;
217 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
218 ram_size >>= 1) {
219 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
220 break;
221
222 --cap_param;
223 refresh_timing_param >>= 8;
224 test_pattern = (test_pattern >> 4) | (test_pattern << 28);
225 }
226
227 clrsetbits_le32(&info->regs->ac_timing[1],
228 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
229 ((refresh_timing_param & SDRAM_AC_TRFC_MASK)
230 << SDRAM_AC_TRFC_SHIFT));
231
232 info->info.base = CONFIG_SYS_SDRAM_BASE;
233 info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
234 clrsetbits_le32(&info->regs->config,
235 (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
236 ((cap_param & SDRAM_CONF_CAP_MASK)
237 << SDRAM_CONF_CAP_SHIFT));
238 }
239
ast2500_sdrammc_init_ddr4(struct dram_info * info)240 static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
241 {
242 int i;
243 const u32 power_control = SDRAM_PCR_CKE_EN
244 | (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
245 | (2 << SDRAM_PCR_TCKE_PW_SHIFT)
246 | SDRAM_PCR_RESETN_DIS
247 | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN;
248 const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
249 #ifdef CONFIG_DUALX8_RAM
250 | SDRAM_CONF_DUALX8
251 #endif
252 | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4;
253 int ret;
254
255 writel(conf, &info->regs->config);
256 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
257 writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);
258
259 writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
260 writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
261 writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
262 writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);
263
264 for (i = 0; i < PHY_CFG_SIZE; ++i) {
265 writel(ddr4_phy_config.value[i],
266 &info->phy->phy[ddr4_phy_config.index[i]]);
267 }
268
269 writel(power_control, &info->regs->power_control);
270
271 ast2500_ddr_phy_init_process(info);
272
273 ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
274 if (ret < 0) {
275 debug("Vref calibration failed!\n");
276 return ret;
277 }
278
279 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
280 | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
281 &info->regs->refresh_timing);
282
283 setbits_le32(&info->regs->power_control,
284 SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON);
285
286 ast2500_sdrammc_calc_size(info);
287
288 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
289 while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
290 ;
291 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);
292
293 writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
294
295 /* Enable all requests except video & display */
296 writel(SDRAM_REQ_USB20_EHCI1
297 | SDRAM_REQ_USB20_EHCI2
298 | SDRAM_REQ_CPU
299 | SDRAM_REQ_AHB2
300 | SDRAM_REQ_AHB
301 | SDRAM_REQ_MAC0
302 | SDRAM_REQ_MAC1
303 | SDRAM_REQ_PCIE
304 | SDRAM_REQ_XDMA
305 | SDRAM_REQ_ENCRYPTION
306 | SDRAM_REQ_VIDEO_FLAG
307 | SDRAM_REQ_VIDEO_LOW_PRI_WRITE
308 | SDRAM_REQ_2D_RW
309 | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);
310
311 return 0;
312 }
313
ast2500_sdrammc_unlock(struct dram_info * info)314 static void ast2500_sdrammc_unlock(struct dram_info *info)
315 {
316 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
317 while (!readl(&info->regs->protection_key))
318 ;
319 }
320
ast2500_sdrammc_lock(struct dram_info * info)321 static void ast2500_sdrammc_lock(struct dram_info *info)
322 {
323 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
324 while (readl(&info->regs->protection_key))
325 ;
326 }
327
ast2500_sdrammc_probe(struct udevice * dev)328 static int ast2500_sdrammc_probe(struct udevice *dev)
329 {
330 struct reset_ctl reset_ctl;
331 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
332 struct ast2500_sdrammc_regs *regs = priv->regs;
333 int i;
334 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
335
336 if (ret) {
337 debug("DDR:No CLK\n");
338 return ret;
339 }
340
341 priv->scu = ast_get_scu();
342 if (IS_ERR(priv->scu)) {
343 debug("%s(): can't get SCU\n", __func__);
344 return PTR_ERR(priv->scu);
345 }
346
347 clk_set_rate(&priv->ddr_clk, priv->clock_rate);
348 ret = reset_get_by_index(dev, 0, &reset_ctl);
349 if (ret) {
350 debug("%s(): Failed to get reset signal\n", __func__);
351 return ret;
352 }
353
354 ret = reset_assert(&reset_ctl);
355 if (ret) {
356 debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
357 return ret;
358 }
359
360 ast2500_sdrammc_unlock(priv);
361
362 writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS,
363 ®s->power_control);
364 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key);
365
366 /* Mask all requests except CPU and AHB during PHY init */
367 writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask);
368
369 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
370 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]);
371
372 setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL);
373
374 ast2500_sdrammc_init_phy(priv->phy);
375 if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
376 ast2500_sdrammc_init_ddr4(priv);
377 } else {
378 debug("Unsupported DRAM3\n");
379 return -EINVAL;
380 }
381
382 clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL);
383 ast2500_sdrammc_lock(priv);
384
385 return 0;
386 }
387
ast2500_sdrammc_ofdata_to_platdata(struct udevice * dev)388 static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
389 {
390 struct dram_info *priv = dev_get_priv(dev);
391 struct regmap *map;
392 int ret;
393
394 ret = regmap_init_mem(dev_ofnode(dev), &map);
395 if (ret)
396 return ret;
397
398 priv->regs = regmap_get_range(map, 0);
399 priv->phy = regmap_get_range(map, 1);
400
401 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
402 "clock-frequency", 0);
403
404 if (!priv->clock_rate) {
405 debug("DDR Clock Rate not defined\n");
406 return -EINVAL;
407 }
408
409 return 0;
410 }
411
ast2500_sdrammc_get_info(struct udevice * dev,struct ram_info * info)412 static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
413 {
414 struct dram_info *priv = dev_get_priv(dev);
415
416 *info = priv->info;
417
418 return 0;
419 }
420
421 static struct ram_ops ast2500_sdrammc_ops = {
422 .get_info = ast2500_sdrammc_get_info,
423 };
424
425 static const struct udevice_id ast2500_sdrammc_ids[] = {
426 { .compatible = "aspeed,ast2500-sdrammc" },
427 { }
428 };
429
430 U_BOOT_DRIVER(sdrammc_ast2500) = {
431 .name = "aspeed_ast2500_sdrammc",
432 .id = UCLASS_RAM,
433 .of_match = ast2500_sdrammc_ids,
434 .ops = &ast2500_sdrammc_ops,
435 .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
436 .probe = ast2500_sdrammc_probe,
437 .priv_auto_alloc_size = sizeof(struct dram_info),
438 };
439