1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/gx.h> 11 #include <asm/arch/eth.h> 12 #include <phy.h> 13 14 /* Configure the Ethernet MAC with the requested interface mode 15 * with some optional flags. 16 */ meson_gx_eth_init(phy_interface_t mode,unsigned int flags)17void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) 18 { 19 switch (mode) { 20 case PHY_INTERFACE_MODE_RGMII: 21 case PHY_INTERFACE_MODE_RGMII_ID: 22 case PHY_INTERFACE_MODE_RGMII_RXID: 23 case PHY_INTERFACE_MODE_RGMII_TXID: 24 /* Set RGMII mode */ 25 setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | 26 GX_ETH_REG_0_TX_PHASE(1) | 27 GX_ETH_REG_0_TX_RATIO(4) | 28 GX_ETH_REG_0_PHY_CLK_EN | 29 GX_ETH_REG_0_CLK_EN); 30 break; 31 32 case PHY_INTERFACE_MODE_RMII: 33 /* Set RMII mode */ 34 out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | 35 GX_ETH_REG_0_CLK_EN); 36 37 /* Use GXL RMII Internal PHY */ 38 if (IS_ENABLED(CONFIG_MESON_GXL) && 39 (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { 40 writel(0x10110181, GX_ETH_REG_2); 41 writel(0xe40908ff, GX_ETH_REG_3); 42 } 43 44 break; 45 46 default: 47 printf("Invalid Ethernet interface mode\n"); 48 return; 49 } 50 51 /* Enable power gate */ 52 clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); 53 } 54