1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 */
7
8 #include <config.h>
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13
14 #if defined(CONFIG_ARCH_MVEBU)
15 /* Use common XOR definitions for A3x and AXP */
16 #include "../../../drivers/ddr/marvell/axp/xor.h"
17 #include "../../../drivers/ddr/marvell/axp/xor_regs.h"
18 #endif
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 struct sdram_bank {
23 u32 win_bar;
24 u32 win_sz;
25 };
26
27 struct sdram_addr_dec {
28 struct sdram_bank sdram_bank[4];
29 };
30
31 #define REG_CPUCS_WIN_ENABLE (1 << 0)
32 #define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
33 #define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
34 #define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
35
36 #define SDRAM_SIZE_MAX 0xc0000000
37
38 #define SCRUB_MAGIC 0xbeefdead
39
40 #define SCRB_XOR_UNIT 0
41 #define SCRB_XOR_CHAN 1
42 #define SCRB_XOR_WIN 0
43
44 #define XEBARX_BASE_OFFS 16
45
46 /*
47 * mvebu_sdram_bar - reads SDRAM Base Address Register
48 */
mvebu_sdram_bar(enum memory_bank bank)49 u32 mvebu_sdram_bar(enum memory_bank bank)
50 {
51 struct sdram_addr_dec *base =
52 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
53 u32 result = 0;
54 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
55
56 if ((!enable) || (bank > BANK3))
57 return 0;
58
59 result = readl(&base->sdram_bank[bank].win_bar);
60 return result;
61 }
62
63 /*
64 * mvebu_sdram_bs_set - writes SDRAM Bank size
65 */
mvebu_sdram_bs_set(enum memory_bank bank,u32 size)66 static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
67 {
68 struct sdram_addr_dec *base =
69 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
70 /* Read current register value */
71 u32 reg = readl(&base->sdram_bank[bank].win_sz);
72
73 /* Clear window size */
74 reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
75
76 /* Set new window size */
77 reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
78
79 writel(reg, &base->sdram_bank[bank].win_sz);
80 }
81
82 /*
83 * mvebu_sdram_bs - reads SDRAM Bank size
84 */
mvebu_sdram_bs(enum memory_bank bank)85 u32 mvebu_sdram_bs(enum memory_bank bank)
86 {
87 struct sdram_addr_dec *base =
88 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
89 u32 result = 0;
90 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
91
92 if ((!enable) || (bank > BANK3))
93 return 0;
94 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
95 result += 0x01000000;
96 return result;
97 }
98
mvebu_sdram_size_adjust(enum memory_bank bank)99 void mvebu_sdram_size_adjust(enum memory_bank bank)
100 {
101 u32 size;
102
103 /* probe currently equipped RAM size */
104 size = get_ram_size((void *)mvebu_sdram_bar(bank),
105 mvebu_sdram_bs(bank));
106
107 /* adjust SDRAM window size accordingly */
108 mvebu_sdram_bs_set(bank, size);
109 }
110
111 #if defined(CONFIG_ARCH_MVEBU)
112 static u32 xor_ctrl_save;
113 static u32 xor_base_save;
114 static u32 xor_mask_save;
115
mv_xor_init2(u32 cs)116 static void mv_xor_init2(u32 cs)
117 {
118 u32 reg, base, size, base2;
119 u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
120
121 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
122 SCRB_XOR_CHAN));
123 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
124 SCRB_XOR_WIN));
125 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
126 SCRB_XOR_WIN));
127
128 /* Enable Window x for each CS */
129 reg = 0x1;
130 reg |= (0x3 << 16);
131 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
132
133 base = 0;
134 size = mvebu_sdram_bs(cs) - 1;
135 if (size) {
136 base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
137 bank_attr[cs];
138 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
139 base2);
140
141 base += size + 1;
142 size = (size / (64 << 10)) << 16;
143 /* Window x - size - 256 MB */
144 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
145 }
146
147 mv_xor_hal_init(0);
148
149 return;
150 }
151
mv_xor_finish2(void)152 static void mv_xor_finish2(void)
153 {
154 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
155 xor_ctrl_save);
156 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
157 xor_base_save);
158 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
159 xor_mask_save);
160 }
161
dram_ecc_scrubbing(void)162 static void dram_ecc_scrubbing(void)
163 {
164 int cs;
165 u32 size, temp;
166 u32 total_mem = 0;
167 u64 total;
168 u32 start_addr;
169
170 /*
171 * The DDR training code from the bin_hdr / SPL already
172 * scrubbed the DDR till 0x1000000. And the main U-Boot
173 * is loaded to an address < 0x1000000. So we need to
174 * skip this range to not re-scrub this area again.
175 */
176 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
177 temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
178 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
179
180 for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
181 size = mvebu_sdram_bs(cs);
182 if (size == 0)
183 continue;
184
185 total = (u64)size;
186 total_mem += (u32)(total / (1 << 30));
187 start_addr = 0;
188 mv_xor_init2(cs);
189
190 /* Skip first 16 MiB */
191 if (0 == cs) {
192 start_addr = 0x1000000;
193 size -= start_addr;
194 }
195
196 mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
197 SCRUB_MAGIC, SCRUB_MAGIC);
198
199 /* Wait for previous transfer completion */
200 while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
201 ;
202
203 mv_xor_finish2();
204 }
205
206 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
207 temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
208 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
209 }
210
ecc_enabled(void)211 static int ecc_enabled(void)
212 {
213 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
214 return 1;
215
216 return 0;
217 }
218
219 /* Return the width of the DRAM bus, or 0 for unknown. */
bus_width(void)220 static int bus_width(void)
221 {
222 int full_width = 0;
223
224 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
225 full_width = 1;
226
227 switch (mvebu_soc_family()) {
228 case MVEBU_SOC_AXP:
229 return full_width ? 64 : 32;
230 break;
231 case MVEBU_SOC_A375:
232 case MVEBU_SOC_A38X:
233 case MVEBU_SOC_MSYS:
234 return full_width ? 32 : 16;
235 default:
236 return 0;
237 }
238 }
239
cycle_mode(void)240 static int cycle_mode(void)
241 {
242 int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
243
244 return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;
245 }
246
247 #else
dram_ecc_scrubbing(void)248 static void dram_ecc_scrubbing(void)
249 {
250 }
251
ecc_enabled(void)252 static int ecc_enabled(void)
253 {
254 return 0;
255 }
256 #endif
257
dram_init(void)258 int dram_init(void)
259 {
260 u64 size = 0;
261 int i;
262
263 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
264 /*
265 * It is assumed that all memory banks are consecutive
266 * and without gaps.
267 * If the gap is found, ram_size will be reported for
268 * consecutive memory only
269 */
270 if (mvebu_sdram_bar(i) != size)
271 break;
272
273 /*
274 * Don't report more than 3GiB of SDRAM, otherwise there is no
275 * address space left for the internal registers etc.
276 */
277 size += mvebu_sdram_bs(i);
278 if (size > SDRAM_SIZE_MAX)
279 size = SDRAM_SIZE_MAX;
280 }
281
282 for (; i < CONFIG_NR_DRAM_BANKS; i++) {
283 /* If above loop terminated prematurely, we need to set
284 * remaining banks' start address & size as 0. Otherwise other
285 * u-boot functions and Linux kernel gets wrong values which
286 * could result in crash */
287 gd->bd->bi_dram[i].start = 0;
288 gd->bd->bi_dram[i].size = 0;
289 }
290
291
292 if (ecc_enabled())
293 dram_ecc_scrubbing();
294
295 gd->ram_size = size;
296
297 return 0;
298 }
299
300 /*
301 * If this function is not defined here,
302 * board.c alters dram bank zero configuration defined above.
303 */
dram_init_banksize(void)304 int dram_init_banksize(void)
305 {
306 u64 size = 0;
307 int i;
308
309 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
310 gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
311 gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
312
313 /* Clip the banksize to 1GiB if it exceeds the max size */
314 size += gd->bd->bi_dram[i].size;
315 if (size > SDRAM_SIZE_MAX)
316 mvebu_sdram_bs_set(i, 0x40000000);
317 }
318
319 return 0;
320 }
321
322 #if defined(CONFIG_ARCH_MVEBU)
board_add_ram_info(int use_default)323 void board_add_ram_info(int use_default)
324 {
325 struct sar_freq_modes sar_freq;
326 int mode;
327 int width;
328
329 get_sar_freq(&sar_freq);
330 printf(" (%d MHz, ", sar_freq.d_clk);
331
332 width = bus_width();
333 if (width)
334 printf("%d-bit, ", width);
335
336 mode = cycle_mode();
337 /* Mode 0 = Single cycle
338 * Mode 1 = Two cycles (2T)
339 * Mode 2 = Three cycles (3T)
340 */
341 if (mode == 1)
342 printf("2T, ");
343 if (mode == 2)
344 printf("3T, ");
345
346 if (ecc_enabled())
347 printf("ECC");
348 else
349 printf("ECC not");
350 printf(" enabled)");
351 }
352 #endif
353