1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <ns16550.h>
11 #include <usb.h>
12 #include <asm/io.h>
13 #include <asm/arch-tegra/ap.h>
14 #include <asm/arch-tegra/board.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <asm/arch-tegra/sys_proto.h>
18 #include <asm/arch-tegra/uart.h>
19 #include <asm/arch-tegra/warmboot.h>
20 #include <asm/arch-tegra/gpu.h>
21 #include <asm/arch-tegra/usb.h>
22 #include <asm/arch-tegra/xusb-padctl.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/funcmux.h>
25 #include <asm/arch/pinmux.h>
26 #include <asm/arch/pmu.h>
27 #include <asm/arch/tegra.h>
28 #ifdef CONFIG_TEGRA_CLOCK_SCALING
29 #include <asm/arch/emc.h>
30 #endif
31 #include "emc.h"
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #ifdef CONFIG_SPL_BUILD
36 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
37 U_BOOT_DEVICE(tegra_gpios) = {
38 "gpio_tegra"
39 };
40 #endif
41
pinmux_init(void)42 __weak void pinmux_init(void) {}
pin_mux_usb(void)43 __weak void pin_mux_usb(void) {}
pin_mux_spi(void)44 __weak void pin_mux_spi(void) {}
pin_mux_mmc(void)45 __weak void pin_mux_mmc(void) {}
gpio_early_init_uart(void)46 __weak void gpio_early_init_uart(void) {}
pin_mux_display(void)47 __weak void pin_mux_display(void) {}
start_cpu_fan(void)48 __weak void start_cpu_fan(void) {}
49
50 #if defined(CONFIG_TEGRA_NAND)
pin_mux_nand(void)51 __weak void pin_mux_nand(void)
52 {
53 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
54 }
55 #endif
56
57 /*
58 * Routine: power_det_init
59 * Description: turn off power detects
60 */
power_det_init(void)61 static void power_det_init(void)
62 {
63 #if defined(CONFIG_TEGRA20)
64 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
65
66 /* turn off power detects */
67 writel(0, &pmc->pmc_pwr_det_latch);
68 writel(0, &pmc->pmc_pwr_det);
69 #endif
70 }
71
tegra_board_id(void)72 __weak int tegra_board_id(void)
73 {
74 return -1;
75 }
76
77 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)78 int checkboard(void)
79 {
80 int board_id = tegra_board_id();
81
82 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
83 if (board_id != -1)
84 printf(", ID: %d\n", board_id);
85 printf("\n");
86
87 return 0;
88 }
89 #endif /* CONFIG_DISPLAY_BOARDINFO */
90
tegra_lcd_pmic_init(int board_it)91 __weak int tegra_lcd_pmic_init(int board_it)
92 {
93 return 0;
94 }
95
nvidia_board_init(void)96 __weak int nvidia_board_init(void)
97 {
98 return 0;
99 }
100
101 /*
102 * Routine: board_init
103 * Description: Early hardware init.
104 */
board_init(void)105 int board_init(void)
106 {
107 __maybe_unused int err;
108 __maybe_unused int board_id;
109
110 /* Do clocks and UART first so that printf() works */
111 clock_init();
112 clock_verify();
113
114 tegra_gpu_config();
115
116 #ifdef CONFIG_TEGRA_SPI
117 pin_mux_spi();
118 #endif
119
120 #ifdef CONFIG_MMC_SDHCI_TEGRA
121 pin_mux_mmc();
122 #endif
123
124 /* Init is handled automatically in the driver-model case */
125 #if defined(CONFIG_DM_VIDEO)
126 pin_mux_display();
127 #endif
128 /* boot param addr */
129 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
130
131 power_det_init();
132
133 #ifdef CONFIG_SYS_I2C_TEGRA
134 # ifdef CONFIG_TEGRA_PMU
135 if (pmu_set_nominal())
136 debug("Failed to select nominal voltages\n");
137 # ifdef CONFIG_TEGRA_CLOCK_SCALING
138 err = board_emc_init();
139 if (err)
140 debug("Memory controller init failed: %d\n", err);
141 # endif
142 # endif /* CONFIG_TEGRA_PMU */
143 #endif /* CONFIG_SYS_I2C_TEGRA */
144
145 #ifdef CONFIG_USB_EHCI_TEGRA
146 pin_mux_usb();
147 #endif
148
149 #if defined(CONFIG_DM_VIDEO)
150 board_id = tegra_board_id();
151 err = tegra_lcd_pmic_init(board_id);
152 if (err) {
153 debug("Failed to set up LCD PMIC\n");
154 return err;
155 }
156 #endif
157
158 #ifdef CONFIG_TEGRA_NAND
159 pin_mux_nand();
160 #endif
161
162 tegra_xusb_padctl_init();
163
164 #ifdef CONFIG_TEGRA_LP0
165 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
166 warmboot_save_sdram_params();
167
168 /* prepare the WB code to LP0 location */
169 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
170 #endif
171 return nvidia_board_init();
172 }
173
174 #ifdef CONFIG_BOARD_EARLY_INIT_F
__gpio_early_init(void)175 static void __gpio_early_init(void)
176 {
177 }
178
179 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
180
board_early_init_f(void)181 int board_early_init_f(void)
182 {
183 if (!clock_early_init_done())
184 clock_early_init();
185
186 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
187 #define USBCMD_FS2 (1 << 15)
188 {
189 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
190 writel(USBCMD_FS2, &usbctlr->usb_cmd);
191 }
192 #endif
193
194 /* Do any special system timer/TSC setup */
195 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
196 if (!tegra_cpu_is_non_secure())
197 #endif
198 arch_timer_init();
199
200 pinmux_init();
201 board_init_uart_f();
202
203 /* Initialize periph GPIOs */
204 gpio_early_init();
205 gpio_early_init_uart();
206
207 return 0;
208 }
209 #endif /* EARLY_INIT */
210
board_late_init(void)211 int board_late_init(void)
212 {
213 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
214 if (tegra_cpu_is_non_secure()) {
215 printf("CPU is in NS mode\n");
216 env_set("cpu_ns_mode", "1");
217 } else {
218 env_set("cpu_ns_mode", "");
219 }
220 #endif
221 start_cpu_fan();
222
223 return 0;
224 }
225
226 /*
227 * In some SW environments, a memory carve-out exists to house a secure
228 * monitor, a trusted OS, and/or various statically allocated media buffers.
229 *
230 * This carveout exists at the highest possible address that is within a
231 * 32-bit physical address space.
232 *
233 * This function returns the total size of this carve-out. At present, the
234 * returned value is hard-coded for simplicity. In the future, it may be
235 * possible to determine the carve-out size:
236 * - By querying some run-time information source, such as:
237 * - A structure passed to U-Boot by earlier boot software.
238 * - SoC registers.
239 * - A call into the secure monitor.
240 * - In the per-board U-Boot configuration header, based on knowledge of the
241 * SW environment that U-Boot is being built for.
242 *
243 * For now, we support two configurations in U-Boot:
244 * - 32-bit ports without any form of carve-out.
245 * - 64 bit ports which are assumed to use a carve-out of a conservatively
246 * hard-coded size.
247 */
carveout_size(void)248 static ulong carveout_size(void)
249 {
250 #ifdef CONFIG_ARM64
251 return SZ_512M;
252 #else
253 return 0;
254 #endif
255 }
256
257 /*
258 * Determine the amount of usable RAM below 4GiB, taking into account any
259 * carve-out that may be assigned.
260 */
usable_ram_size_below_4g(void)261 static ulong usable_ram_size_below_4g(void)
262 {
263 ulong total_size_below_4g;
264 ulong usable_size_below_4g;
265
266 /*
267 * The total size of RAM below 4GiB is the lesser address of:
268 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
269 * (b) The size RAM physically present in the system.
270 */
271 if (gd->ram_size < SZ_2G)
272 total_size_below_4g = gd->ram_size;
273 else
274 total_size_below_4g = SZ_2G;
275
276 /* Calculate usable RAM by subtracting out any carve-out size */
277 usable_size_below_4g = total_size_below_4g - carveout_size();
278
279 return usable_size_below_4g;
280 }
281
282 /*
283 * Represent all available RAM in either one or two banks.
284 *
285 * The first bank describes any usable RAM below 4GiB.
286 * The second bank describes any RAM above 4GiB.
287 *
288 * This split is driven by the following requirements:
289 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
290 * property for memory below and above the 4GiB boundary. The layout of that
291 * DT property is directly driven by the entries in the U-Boot bank array.
292 * - The potential existence of a carve-out at the end of RAM below 4GiB can
293 * only be represented using multiple banks.
294 *
295 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
296 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
297 * command-line.
298 *
299 * This does mean that the DT U-Boot passes to the Linux kernel will not
300 * include this RAM in /memory/reg at all. An alternative would be to include
301 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
302 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
303 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
304 * mapping, so either way is acceptable.
305 *
306 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
307 * start address of that bank cannot be represented in the 32-bit .size
308 * field.
309 */
dram_init_banksize(void)310 int dram_init_banksize(void)
311 {
312 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
313 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
314
315 #ifdef CONFIG_PCI
316 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
317 #endif
318
319 #ifdef CONFIG_PHYS_64BIT
320 if (gd->ram_size > SZ_2G) {
321 gd->bd->bi_dram[1].start = 0x100000000;
322 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
323 } else
324 #endif
325 {
326 gd->bd->bi_dram[1].start = 0;
327 gd->bd->bi_dram[1].size = 0;
328 }
329
330 return 0;
331 }
332
333 /*
334 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
335 * 32-bits of the physical address space. Cap the maximum usable RAM area
336 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
337 * boundary that most devices can address. Also, don't let U-Boot use any
338 * carve-out, as mentioned above.
339 *
340 * This function is called before dram_init_banksize(), so we can't simply
341 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
342 */
board_get_usable_ram_top(ulong total_size)343 ulong board_get_usable_ram_top(ulong total_size)
344 {
345 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
346 }
347