1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 */
5
6 /*
7 * CPU specific code for the MPC83xx family.
8 *
9 * Derived from the MPC8260 and MPC85xx.
10 */
11
12 #include <common.h>
13 #include <watchdog.h>
14 #include <command.h>
15 #include <mpc83xx.h>
16 #include <asm/processor.h>
17 #include <linux/libfdt.h>
18 #include <tsec.h>
19 #include <netdev.h>
20 #include <fsl_esdhc.h>
21 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
22 #include <linux/immap_qe.h>
23 #include <asm/io.h>
24 #endif
25
26 DECLARE_GLOBAL_DATA_PTR;
27
checkcpu(void)28 int checkcpu(void)
29 {
30 volatile immap_t *immr;
31 ulong clock = gd->cpu_clk;
32 u32 pvr = get_pvr();
33 u32 spridr;
34 char buf[32];
35 int ret;
36 int i;
37
38 const struct cpu_type {
39 char name[15];
40 u32 partid;
41 } cpu_type_list [] = {
42 CPU_TYPE_ENTRY(8308),
43 CPU_TYPE_ENTRY(8309),
44 CPU_TYPE_ENTRY(8311),
45 CPU_TYPE_ENTRY(8313),
46 CPU_TYPE_ENTRY(8314),
47 CPU_TYPE_ENTRY(8315),
48 CPU_TYPE_ENTRY(8321),
49 CPU_TYPE_ENTRY(8323),
50 CPU_TYPE_ENTRY(8343),
51 CPU_TYPE_ENTRY(8347_TBGA_),
52 CPU_TYPE_ENTRY(8347_PBGA_),
53 CPU_TYPE_ENTRY(8349),
54 CPU_TYPE_ENTRY(8358_TBGA_),
55 CPU_TYPE_ENTRY(8358_PBGA_),
56 CPU_TYPE_ENTRY(8360),
57 CPU_TYPE_ENTRY(8377),
58 CPU_TYPE_ENTRY(8378),
59 CPU_TYPE_ENTRY(8379),
60 };
61
62 immr = (immap_t *)CONFIG_SYS_IMMR;
63
64 ret = prt_83xx_rsr();
65 if (ret)
66 return ret;
67
68 puts("CPU: ");
69
70 switch (pvr & 0xffff0000) {
71 case PVR_E300C1:
72 printf("e300c1, ");
73 break;
74
75 case PVR_E300C2:
76 printf("e300c2, ");
77 break;
78
79 case PVR_E300C3:
80 printf("e300c3, ");
81 break;
82
83 case PVR_E300C4:
84 printf("e300c4, ");
85 break;
86
87 default:
88 printf("Unknown core, ");
89 }
90
91 spridr = immr->sysconf.spridr;
92
93 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
94 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
95 puts("MPC");
96 puts(cpu_type_list[i].name);
97 if (IS_E_PROCESSOR(spridr))
98 puts("E");
99 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
100 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
101 REVID_MAJOR(spridr) >= 2)
102 puts("A");
103 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
104 REVID_MINOR(spridr));
105 break;
106 }
107
108 if (i == ARRAY_SIZE(cpu_type_list))
109 printf("(SPRIDR %08x unknown), ", spridr);
110
111 printf(" at %s MHz, ", strmhz(buf, clock));
112
113 printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
114
115 return 0;
116 }
117
118 int
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])119 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
120 {
121 ulong msr;
122 #ifndef MPC83xx_RESET
123 ulong addr;
124 #endif
125
126 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
127
128 puts("Resetting the board.\n");
129
130 #ifdef MPC83xx_RESET
131
132 /* Interrupts and MMU off */
133 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
134
135 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
136 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
137
138 /* enable Reset Control Reg */
139 immap->reset.rpr = 0x52535445;
140 __asm__ __volatile__ ("sync");
141 __asm__ __volatile__ ("isync");
142
143 /* confirm Reset Control Reg is enabled */
144 while(!((immap->reset.rcer) & RCER_CRE));
145
146 udelay(200);
147
148 /* perform reset, only one bit */
149 immap->reset.rcr = RCR_SWHR;
150
151 #else /* ! MPC83xx_RESET */
152
153 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
154
155 /* Interrupts and MMU off */
156 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
157
158 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
159 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
160
161 /*
162 * Trying to execute the next instruction at a non-existing address
163 * should cause a machine check, resulting in reset
164 */
165 addr = CONFIG_SYS_RESET_ADDRESS;
166
167 ((void (*)(void)) addr) ();
168 #endif /* MPC83xx_RESET */
169
170 return 1;
171 }
172
173
174 /*
175 * Get timebase clock frequency (like cpu_clk in Hz)
176 */
177
get_tbclk(void)178 unsigned long get_tbclk(void)
179 {
180 return (gd->bus_clk + 3L) / 4L;
181 }
182
183
184 #if defined(CONFIG_WATCHDOG)
watchdog_reset(void)185 void watchdog_reset (void)
186 {
187 int re_enable = disable_interrupts();
188
189 /* Reset the 83xx watchdog */
190 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
191 immr->wdt.swsrr = 0x556c;
192 immr->wdt.swsrr = 0xaa39;
193
194 if (re_enable)
195 enable_interrupts ();
196 }
197 #endif
198
199 /*
200 * Initializes on-chip ethernet controllers.
201 * to override, implement board_eth_init()
202 */
cpu_eth_init(bd_t * bis)203 int cpu_eth_init(bd_t *bis)
204 {
205 #if defined(CONFIG_UEC_ETH)
206 uec_standard_init(bis);
207 #endif
208
209 #if defined(CONFIG_TSEC_ENET)
210 tsec_standard_init(bis);
211 #endif
212 return 0;
213 }
214
215 /*
216 * Initializes on-chip MMC controllers.
217 * to override, implement board_mmc_init()
218 */
cpu_mmc_init(bd_t * bis)219 int cpu_mmc_init(bd_t *bis)
220 {
221 #ifdef CONFIG_FSL_ESDHC
222 return fsl_esdhc_mmc_init(bis);
223 #else
224 return 0;
225 #endif
226 }
227