1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 5 */ 6 7#include <asm/arch-baytrail/fsp/fsp_configs.h> 8#include <dt-bindings/gpio/x86-gpio.h> 9#include <dt-bindings/interrupt-router/intel-irq.h> 10 11#include "skeleton.dtsi" 12#include "rtc.dtsi" 13#include "tsc_timer.dtsi" 14 15/ { 16 config { 17 silent_console = <0>; 18 }; 19 20 pch_pinctrl { 21 compatible = "intel,x86-pinctrl"; 22 reg = <0 0>; 23 24 /* Add UART1 PAD configuration (SIO HS-UART) */ 25 uart1_txd@0 { 26 pad-offset = <0x10>; 27 mode-func = <1>; 28 }; 29 30 uart1_rxd@0 { 31 pad-offset = <0x20>; 32 mode-func = <1>; 33 }; 34 35 /* 36 * As of today, the latest version FSP (gold4) for BayTrail 37 * misses the PAD configuration of the SD controller's Card 38 * Detect signal. The default PAD value for the CD pin sets 39 * the pin to work in GPIO mode, which causes card detect 40 * status cannot be reflected by the Present State register 41 * in the SD controller (bit 16 & bit 18 are always zero). 42 * 43 * Configure this pin to function 1 (SD controller). 44 */ 45 sdmmc3_cd@0 { 46 pad-offset = <0x3a0>; 47 mode-func = <1>; 48 }; 49 50 xhci_hub_reset: usb_ulpi_stp@0 { 51 gpio-offset = <0xa0 10>; 52 pad-offset = <0x23b0>; 53 mode-func = <0>; 54 mode-gpio; 55 output-value = <1>; 56 direction = <PIN_OUTPUT>; 57 }; 58 }; 59 60 chosen { 61 stdout-path = "/serial"; 62 }; 63 64 cpus { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 cpu@0 { 69 device_type = "cpu"; 70 compatible = "intel,baytrail-cpu"; 71 reg = <0>; 72 intel,apic-id = <0>; 73 }; 74 75 cpu@1 { 76 device_type = "cpu"; 77 compatible = "intel,baytrail-cpu"; 78 reg = <1>; 79 intel,apic-id = <2>; 80 }; 81 82 cpu@2 { 83 device_type = "cpu"; 84 compatible = "intel,baytrail-cpu"; 85 reg = <2>; 86 intel,apic-id = <4>; 87 }; 88 89 cpu@3 { 90 device_type = "cpu"; 91 compatible = "intel,baytrail-cpu"; 92 reg = <3>; 93 intel,apic-id = <6>; 94 }; 95 }; 96 97 pci { 98 compatible = "intel,pci-baytrail", "pci-x86"; 99 #address-cells = <3>; 100 #size-cells = <2>; 101 u-boot,dm-pre-reloc; 102 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 103 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 104 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 105 106 pciuart0: uart@1e,3 { 107 compatible = "pci8086,0f0a.00", 108 "pci8086,0f0a", 109 "pciclass,070002", 110 "pciclass,0700", 111 "ns16550"; 112 u-boot,dm-pre-reloc; 113 reg = <0x0200f310 0x0 0x0 0x0 0x0>; 114 reg-shift = <2>; 115 clock-frequency = <58982400>; 116 current-speed = <115200>; 117 }; 118 119 pch@1f,0 { 120 reg = <0x0000f800 0 0 0 0>; 121 compatible = "pci8086,0f1c", "intel,pch9"; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 125 irq-router { 126 compatible = "intel,irq-router"; 127 intel,pirq-config = "ibase"; 128 intel,ibase-offset = <0x50>; 129 intel,actl-addr = <0>; 130 intel,pirq-link = <8 8>; 131 intel,pirq-mask = <0xdee0>; 132 intel,pirq-routing = < 133 /* BayTrail PCI devices */ 134 PCI_BDF(0, 2, 0) INTA PIRQA 135 PCI_BDF(0, 3, 0) INTA PIRQA 136 PCI_BDF(0, 16, 0) INTA PIRQA 137 PCI_BDF(0, 17, 0) INTA PIRQA 138 PCI_BDF(0, 18, 0) INTA PIRQA 139 PCI_BDF(0, 19, 0) INTA PIRQA 140 PCI_BDF(0, 20, 0) INTA PIRQA 141 PCI_BDF(0, 21, 0) INTA PIRQA 142 PCI_BDF(0, 22, 0) INTA PIRQA 143 PCI_BDF(0, 23, 0) INTA PIRQA 144 PCI_BDF(0, 24, 0) INTA PIRQA 145 PCI_BDF(0, 24, 1) INTC PIRQC 146 PCI_BDF(0, 24, 2) INTD PIRQD 147 PCI_BDF(0, 24, 3) INTB PIRQB 148 PCI_BDF(0, 24, 4) INTA PIRQA 149 PCI_BDF(0, 24, 5) INTC PIRQC 150 PCI_BDF(0, 24, 6) INTD PIRQD 151 PCI_BDF(0, 24, 7) INTB PIRQB 152 PCI_BDF(0, 26, 0) INTA PIRQA 153 PCI_BDF(0, 27, 0) INTA PIRQA 154 PCI_BDF(0, 28, 0) INTA PIRQA 155 PCI_BDF(0, 28, 1) INTB PIRQB 156 PCI_BDF(0, 28, 2) INTC PIRQC 157 PCI_BDF(0, 28, 3) INTD PIRQD 158 PCI_BDF(0, 29, 0) INTA PIRQA 159 PCI_BDF(0, 30, 0) INTA PIRQA 160 PCI_BDF(0, 30, 1) INTD PIRQD 161 PCI_BDF(0, 30, 2) INTB PIRQB 162 PCI_BDF(0, 30, 3) INTC PIRQC 163 PCI_BDF(0, 30, 4) INTD PIRQD 164 PCI_BDF(0, 30, 5) INTB PIRQB 165 PCI_BDF(0, 31, 3) INTB PIRQB 166 167 /* 168 * PCIe root ports downstream 169 * interrupts 170 */ 171 PCI_BDF(1, 0, 0) INTA PIRQA 172 PCI_BDF(1, 0, 0) INTB PIRQB 173 PCI_BDF(1, 0, 0) INTC PIRQC 174 PCI_BDF(1, 0, 0) INTD PIRQD 175 PCI_BDF(2, 0, 0) INTA PIRQB 176 PCI_BDF(2, 0, 0) INTB PIRQC 177 PCI_BDF(2, 0, 0) INTC PIRQD 178 PCI_BDF(2, 0, 0) INTD PIRQA 179 PCI_BDF(3, 0, 0) INTA PIRQC 180 PCI_BDF(3, 0, 0) INTB PIRQD 181 PCI_BDF(3, 0, 0) INTC PIRQA 182 PCI_BDF(3, 0, 0) INTD PIRQB 183 PCI_BDF(4, 0, 0) INTA PIRQD 184 PCI_BDF(4, 0, 0) INTB PIRQA 185 PCI_BDF(4, 0, 0) INTC PIRQB 186 PCI_BDF(4, 0, 0) INTD PIRQC 187 >; 188 }; 189 190 spi: spi { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 compatible = "intel,ich9-spi"; 194 spi-flash@0 { 195 #address-cells = <1>; 196 #size-cells = <1>; 197 reg = <0>; 198 compatible = "stmicro,n25q064a", 199 "spi-flash"; 200 memory-map = <0xff800000 0x00800000>; 201 rw-mrc-cache { 202 label = "rw-mrc-cache"; 203 reg = <0x006f0000 0x00010000>; 204 }; 205 }; 206 }; 207 208 gpioa { 209 compatible = "intel,ich6-gpio"; 210 u-boot,dm-pre-reloc; 211 reg = <0 0x20>; 212 bank-name = "A"; 213 use-lvl-write-cache; 214 }; 215 216 gpiob { 217 compatible = "intel,ich6-gpio"; 218 u-boot,dm-pre-reloc; 219 reg = <0x20 0x20>; 220 bank-name = "B"; 221 use-lvl-write-cache; 222 }; 223 224 gpioc { 225 compatible = "intel,ich6-gpio"; 226 u-boot,dm-pre-reloc; 227 reg = <0x40 0x20>; 228 bank-name = "C"; 229 use-lvl-write-cache; 230 }; 231 232 gpiod { 233 compatible = "intel,ich6-gpio"; 234 u-boot,dm-pre-reloc; 235 reg = <0x60 0x20>; 236 bank-name = "D"; 237 use-lvl-write-cache; 238 }; 239 240 gpioe { 241 compatible = "intel,ich6-gpio"; 242 u-boot,dm-pre-reloc; 243 reg = <0x80 0x20>; 244 bank-name = "E"; 245 use-lvl-write-cache; 246 }; 247 248 gpiof { 249 compatible = "intel,ich6-gpio"; 250 u-boot,dm-pre-reloc; 251 reg = <0xA0 0x20>; 252 bank-name = "F"; 253 use-lvl-write-cache; 254 }; 255 }; 256 }; 257 258 fsp { 259 compatible = "intel,baytrail-fsp"; 260 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>; 261 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; 262 fsp,mrc-init-spd-addr1 = <0xa0>; 263 fsp,mrc-init-spd-addr2 = <0xa2>; 264 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>; 265 fsp,enable-sdio; 266 fsp,enable-sdcard; 267 fsp,enable-hsuart0; 268 fsp,enable-hsuart1; 269 fsp,enable-spi; 270 fsp,enable-sata; 271 fsp,sata-mode = <SATA_MODE_AHCI>; 272#ifdef CONFIG_USB_XHCI_HCD 273 fsp,enable-xhci; 274#endif 275 fsp,lpe-mode = <LPE_MODE_PCI>; 276 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; 277 fsp,enable-dma0; 278 fsp,enable-dma1; 279 fsp,enable-i2c0; 280 fsp,enable-i2c1; 281 fsp,enable-i2c2; 282 fsp,enable-i2c3; 283 fsp,enable-i2c4; 284 fsp,enable-i2c5; 285 fsp,enable-i2c6; 286 fsp,enable-pwm0; 287 fsp,enable-pwm1; 288 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>; 289 fsp,aperture-size = <APERTURE_SIZE_256MB>; 290 fsp,gtt-size = <GTT_SIZE_2MB>; 291 fsp,scc-mode = <SCC_MODE_PCI>; 292 fsp,os-selection = <OS_SELECTION_LINUX>; 293 fsp,emmc45-ddr50-enabled; 294 fsp,emmc45-retune-timer-value = <8>; 295 fsp,enable-igd; 296 fsp,enable-memory-down; 297 fsp,memory-down-params { 298 compatible = "intel,baytrail-fsp-mdp"; 299 fsp,dram-speed = <DRAM_SPEED_1333MTS>; 300 fsp,dram-type = <DRAM_TYPE_DDR3L>; 301 fsp,dimm-0-enable; 302 fsp,dimm-width = <DIMM_WIDTH_X16>; 303 fsp,dimm-density = <DIMM_DENSITY_8GBIT>; 304 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>; 305 fsp,dimm-sides = <DIMM_SIDES_1RANKS>; 306 307 /* These following values might need a re-visit */ 308 fsp,dimm-tcl = <8>; 309 fsp,dimm-trpt-rcd = <8>; 310 fsp,dimm-twr = <8>; 311 fsp,dimm-twtr = <4>; 312 fsp,dimm-trrd = <6>; 313 fsp,dimm-trtp = <4>; 314 fsp,dimm-tfaw = <22>; 315 }; 316 }; 317 318 microcode { 319 update@0 { 320#include "microcode/m0130673325.dtsi" 321 }; 322 update@1 { 323#include "microcode/m0130679907.dtsi" 324 }; 325 }; 326}; 327