1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014 Google, Inc
4 *
5 * From Coreboot src/lib/ramtest.c
6 */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/post.h>
11
write_phys(unsigned long addr,u32 value)12 static void write_phys(unsigned long addr, u32 value)
13 {
14 #if CONFIG_SSE2
15 asm volatile(
16 "movnti %1, (%0)"
17 : /* outputs */
18 : "r" (addr), "r" (value) /* inputs */
19 : /* clobbers */
20 );
21 #else
22 writel(value, addr);
23 #endif
24 }
25
read_phys(unsigned long addr)26 static u32 read_phys(unsigned long addr)
27 {
28 return readl(addr);
29 }
30
phys_memory_barrier(void)31 static void phys_memory_barrier(void)
32 {
33 #if CONFIG_SSE2
34 /* Needed for movnti */
35 asm volatile(
36 "sfence"
37 :
38 :
39 : "memory"
40 );
41 #else
42 asm volatile(""
43 :
44 :
45 : "memory");
46 #endif
47 }
48
quick_ram_check(void)49 void quick_ram_check(void)
50 {
51 int fail = 0;
52 u32 backup;
53
54 backup = read_phys(CONFIG_RAMBASE);
55 write_phys(CONFIG_RAMBASE, 0x55555555);
56 phys_memory_barrier();
57 if (read_phys(CONFIG_RAMBASE) != 0x55555555)
58 fail = 1;
59 write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
60 phys_memory_barrier();
61 if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
62 fail = 1;
63 write_phys(CONFIG_RAMBASE, 0x00000000);
64 phys_memory_barrier();
65 if (read_phys(CONFIG_RAMBASE) != 0x00000000)
66 fail = 1;
67 write_phys(CONFIG_RAMBASE, 0xffffffff);
68 phys_memory_barrier();
69 if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
70 fail = 1;
71
72 write_phys(CONFIG_RAMBASE, backup);
73 if (fail) {
74 post_code(POST_RAM_FAILURE);
75 panic("RAM INIT FAILURE!\n");
76 }
77 phys_memory_barrier();
78 }
79