1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Microchip Corporation
4 * Wenyou Yang <wenyou.yang@microchip.com>
5 */
6
7 #include <common.h>
8 #include <debug_uart.h>
9 #include <dm.h>
10 #include <i2c.h>
11 #include <nand.h>
12 #include <version.h>
13 #include <asm/io.h>
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/atmel_pio4.h>
16 #include <asm/arch/atmel_mpddrc.h>
17 #include <asm/arch/atmel_sdhci.h>
18 #include <asm/arch/clk.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/sama5d2.h>
21 #include <asm/arch/sama5d2_smc.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #ifdef CONFIG_NAND_ATMEL
board_nand_hw_init(void)26 static void board_nand_hw_init(void)
27 {
28 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
29
30 at91_periph_clk_enable(ATMEL_ID_HSMC);
31
32 /* Configure SMC CS3 for NAND */
33 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
34 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
35 &smc->cs[3].setup);
36 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) |
37 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
38 &smc->cs[3].pulse);
39 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5),
40 &smc->cs[3].cycle);
41 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
42 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
43 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
44 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
45 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
46 AT91_SMC_MODE_EXNW_DISABLE |
47 AT91_SMC_MODE_DBW_8 |
48 AT91_SMC_MODE_TDF_CYCLE(3),
49 &smc->cs[3].mode);
50
51 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME); /* D0 */
52 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME); /* D1 */
53 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME); /* D2 */
54 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME); /* D3 */
55 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME); /* D4 */
56 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME); /* D5 */
57 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME); /* D6 */
58 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME); /* D7 */
59 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */
60 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
61 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, ATMEL_PIO_PUEN_MASK); /* NCS */
62 atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, ATMEL_PIO_PUEN_MASK); /* RDY */
63 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, ATMEL_PIO_PUEN_MASK); /* ALE */
64 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, ATMEL_PIO_PUEN_MASK); /* CLE */
65 }
66 #endif
67
board_usb_hw_init(void)68 static void board_usb_hw_init(void)
69 {
70 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
71 }
72
73 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_uart0_hw_init(void)74 static void board_uart0_hw_init(void)
75 {
76 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
77 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
78
79 at91_periph_clk_enable(ATMEL_ID_UART0);
80 }
81
board_debug_uart_init(void)82 void board_debug_uart_init(void)
83 {
84 board_uart0_hw_init();
85 }
86 #endif
87
88 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)89 int board_early_init_f(void)
90 {
91 #ifdef CONFIG_DEBUG_UART
92 debug_uart_init();
93 #endif
94 return 0;
95 }
96 #endif
97
board_init(void)98 int board_init(void)
99 {
100 /* address of boot parameters */
101 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
102
103 #ifdef CONFIG_NAND_ATMEL
104 board_nand_hw_init();
105 #endif
106 #ifdef CONFIG_CMD_USB
107 board_usb_hw_init();
108 #endif
109 return 0;
110 }
111
dram_init(void)112 int dram_init(void)
113 {
114 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
115 CONFIG_SYS_SDRAM_SIZE);
116 return 0;
117 }
118
119 #define AT24MAC_MAC_OFFSET 0xfa
120
121 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)122 int misc_init_r(void)
123 {
124 #ifdef CONFIG_I2C_EEPROM
125 at91_set_ethaddr(AT24MAC_MAC_OFFSET);
126 #endif
127 return 0;
128 }
129 #endif
130