1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Atmel Corporation
4 * Bo Shen <voice.shen@atmel.com>
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/sama5d3_smc.h>
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/at91_rstc.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/clk.h>
14 #include <debug_uart.h>
15 #include <spl.h>
16 #include <asm/arch/atmel_mpddrc.h>
17 #include <asm/arch/at91_wdt.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #ifdef CONFIG_NAND_ATMEL
sama5d3_xplained_nand_hw_init(void)22 void sama5d3_xplained_nand_hw_init(void)
23 {
24 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
25
26 at91_periph_clk_enable(ATMEL_ID_SMC);
27
28 /* Configure SMC CS3 for NAND/SmartMedia */
29 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
30 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
31 &smc->cs[3].setup);
32 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
33 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
34 &smc->cs[3].pulse);
35 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
36 &smc->cs[3].cycle);
37 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
38 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
39 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
40 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
41 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
42 AT91_SMC_MODE_EXNW_DISABLE |
43 #ifdef CONFIG_SYS_NAND_DBW_16
44 AT91_SMC_MODE_DBW_16 |
45 #else /* CONFIG_SYS_NAND_DBW_8 */
46 AT91_SMC_MODE_DBW_8 |
47 #endif
48 AT91_SMC_MODE_TDF_CYCLE(3),
49 &smc->cs[3].mode);
50 }
51 #endif
52
53 #ifdef CONFIG_CMD_USB
sama5d3_xplained_usb_hw_init(void)54 static void sama5d3_xplained_usb_hw_init(void)
55 {
56 at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
57 at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
58 }
59 #endif
60
61 #ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3_xplained_mci0_hw_init(void)62 static void sama5d3_xplained_mci0_hw_init(void)
63 {
64 at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
65 }
66 #endif
67
68 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)69 void board_debug_uart_init(void)
70 {
71 at91_seriald_hw_init();
72 }
73 #endif
74
75 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)76 int board_early_init_f(void)
77 {
78 #ifdef CONFIG_DEBUG_UART
79 debug_uart_init();
80 #endif
81 return 0;
82 }
83 #endif
84
board_init(void)85 int board_init(void)
86 {
87 /* adress of boot parameters */
88 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
89
90 #ifdef CONFIG_NAND_ATMEL
91 sama5d3_xplained_nand_hw_init();
92 #endif
93 #ifdef CONFIG_CMD_USB
94 sama5d3_xplained_usb_hw_init();
95 #endif
96 #ifdef CONFIG_GENERIC_ATMEL_MCI
97 sama5d3_xplained_mci0_hw_init();
98 #endif
99 return 0;
100 }
101
dram_init(void)102 int dram_init(void)
103 {
104 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
105 CONFIG_SYS_SDRAM_SIZE);
106
107 return 0;
108 }
109
110 /* SPL */
111 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)112 void spl_board_init(void)
113 {
114 #ifdef CONFIG_SD_BOOT
115 #ifdef CONFIG_GENERIC_ATMEL_MCI
116 sama5d3_xplained_mci0_hw_init();
117 #endif
118 #elif CONFIG_NAND_BOOT
119 sama5d3_xplained_nand_hw_init();
120 #endif
121 }
122
ddr2_conf(struct atmel_mpddrc_config * ddr2)123 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
124 {
125 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
126
127 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
128 ATMEL_MPDDRC_CR_NR_ROW_14 |
129 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
130 ATMEL_MPDDRC_CR_ENRDM_ON |
131 ATMEL_MPDDRC_CR_NB_8BANKS |
132 ATMEL_MPDDRC_CR_NDQS_DISABLED |
133 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
134 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
135 /*
136 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
137 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
138 */
139 ddr2->rtr = 0x411;
140
141 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
142 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
143 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
144 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
145 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
146 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
147 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
148 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
149
150 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
151 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
152 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
153 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
154
155 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
156 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
157 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
158 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
159 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
160 }
161
mem_init(void)162 void mem_init(void)
163 {
164 struct atmel_mpddrc_config ddr2;
165
166 ddr2_conf(&ddr2);
167
168 /* Enable MPDDR clock */
169 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
170 at91_system_clk_enable(AT91_PMC_DDR);
171
172 /* DDRAM2 Controller initialize */
173 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
174 }
175
at91_pmc_init(void)176 void at91_pmc_init(void)
177 {
178 u32 tmp;
179
180 tmp = AT91_PMC_PLLAR_29 |
181 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
182 AT91_PMC_PLLXR_MUL(43) |
183 AT91_PMC_PLLXR_DIV(1);
184 at91_plla_init(tmp);
185
186 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
187
188 tmp = AT91_PMC_MCKR_MDIV_4 |
189 AT91_PMC_MCKR_CSS_PLLA;
190 at91_mck_init(tmp);
191 }
192 #endif
193