1 /*
2 * mux.c
3 *
4 * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <common.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/mux.h>
21 #include <asm/io.h>
22 #include <i2c.h>
23 #include "board.h"
24
25 static struct module_pin_mux uart0_pin_mux[] = {
26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
28 {-1},
29 };
30
31 static struct module_pin_mux uart1_pin_mux[] = {
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
34 {-1},
35 };
36
37 static struct module_pin_mux uart2_pin_mux[] = {
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
40 {-1},
41 };
42
43 static struct module_pin_mux uart3_pin_mux[] = {
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
46 {-1},
47 };
48
49 static struct module_pin_mux uart4_pin_mux[] = {
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
52 {-1},
53 };
54
55 static struct module_pin_mux uart5_pin_mux[] = {
56 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
57 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
58 {-1},
59 };
60
61 static struct module_pin_mux mmc0_pin_mux[] = {
62 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
63 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
64 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
65 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
66 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
67 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
68 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
69 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
70 {-1},
71 };
72
73 static struct module_pin_mux mmc1_pin_mux[] = {
74 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
75 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
76 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
77 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
78 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
79 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
80 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
81 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
82 {-1},
83 };
84
85 static struct module_pin_mux i2c0_pin_mux[] = {
86 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
87 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
88 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
89 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
90 {-1},
91 };
92
93 static struct module_pin_mux i2c1_pin_mux[] = {
94 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
95 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
96 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
97 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
98 {-1},
99 };
100
101 static struct module_pin_mux rgmii1_pin_mux[] = {
102 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
103 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
104 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
105 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
106 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
107 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
108 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
109 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
110 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
111 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
112 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
113 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
114 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
115 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
116 {-1},
117 };
118
119 static struct module_pin_mux mii1_pin_mux[] = {
120 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
121 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
122 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
123 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
124 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
125 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
126 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
127 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
128 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
129 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
130 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
131 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
132 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
133 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
134 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
135 {-1},
136 };
137
138
enable_uart0_pin_mux(void)139 void enable_uart0_pin_mux(void)
140 {
141 configure_module_pin_mux(uart0_pin_mux);
142 }
143
enable_uart1_pin_mux(void)144 void enable_uart1_pin_mux(void)
145 {
146 configure_module_pin_mux(uart1_pin_mux);
147 }
148
enable_uart2_pin_mux(void)149 void enable_uart2_pin_mux(void)
150 {
151 configure_module_pin_mux(uart2_pin_mux);
152 }
153
enable_uart3_pin_mux(void)154 void enable_uart3_pin_mux(void)
155 {
156 configure_module_pin_mux(uart3_pin_mux);
157 }
158
enable_uart4_pin_mux(void)159 void enable_uart4_pin_mux(void)
160 {
161 configure_module_pin_mux(uart4_pin_mux);
162 }
163
enable_uart5_pin_mux(void)164 void enable_uart5_pin_mux(void)
165 {
166 configure_module_pin_mux(uart5_pin_mux);
167 }
168
enable_i2c0_pin_mux(void)169 void enable_i2c0_pin_mux(void)
170 {
171 configure_module_pin_mux(i2c0_pin_mux);
172 }
173
174
175 /* CPLD registers */
176 #define I2C_CPLD_ADDR 0x35
177 #define CFG_REG 0x10
178
179
enable_board_pin_mux(enum board_type board)180 void enable_board_pin_mux(enum board_type board)
181 {
182 configure_module_pin_mux(i2c1_pin_mux);
183 if (board == BAV335A)
184 configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */
185 else
186 configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */
187
188 configure_module_pin_mux(mmc0_pin_mux);
189 configure_module_pin_mux(mmc1_pin_mux);
190 }
191