1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * Author: Timur Tabi <timur@freescale.com>
5 */
6
7 /*
8 * This file handles the board muxing between the Fman Ethernet MACs and
9 * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
12 * XGMII PHY is provided via the XAUI riser card. Since there is only one
13 * Fman device on a P3041 and P5020, we only support one SGMII card and one
14 * RGMII card.
15 *
16 * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
17 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
18 * always the same (0). The value for SGMII depends on which slot the riser is
19 * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
20 * the value is based on which slot the XAUI is inserted in.
21 *
22 * The SERDES configuration is used to determine where the SGMII and XAUI cards
23 * exist, and also which Fman MACs are routed to which PHYs. So for a given
24 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
25 * to PHYs dynamically.
26 *
27 *
28 * This file also updates the device tree in three ways:
29 *
30 * 1) The status of each virtual MDIO node that is referenced by an Ethernet
31 * node is set to "okay".
32 *
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
34 * appropriate PHY node.
35 *
36 * 3) The "mux value" for each virtual MDIO node is set to the correct value,
37 * if necessary. Some virtual MDIO nodes do not have configurable mux
38 * values, so those values are hard-coded in the DTS. On the HYDRA board,
39 * the virtual MDIO node for the SGMII card needs to be updated.
40 *
41 * For all this to work, the device tree needs to have the following:
42 *
43 * 1) An alias for each PHY node that an Ethernet node could be routed to.
44 *
45 * 2) An alias for each real and virtual MDIO node that is disabled by default
46 * and might need to be enabled, and also might need to have its mux-value
47 * updated.
48 */
49
50 #include <common.h>
51 #include <netdev.h>
52 #include <asm/fsl_serdes.h>
53 #include <fm_eth.h>
54 #include <fsl_mdio.h>
55 #include <malloc.h>
56 #include <fdt_support.h>
57 #include <fsl_dtsec.h>
58
59 #include "../common/ngpixis.h"
60 #include "../common/fman.h"
61
62 #ifdef CONFIG_FMAN_ENET
63
64 #define BRDCFG1_EMI1_SEL_MASK 0x78
65 #define BRDCFG1_EMI1_SEL_SLOT1 0x10
66 #define BRDCFG1_EMI1_SEL_SLOT2 0x20
67 #define BRDCFG1_EMI1_SEL_SLOT5 0x30
68 #define BRDCFG1_EMI1_SEL_SLOT6 0x40
69 #define BRDCFG1_EMI1_SEL_SLOT7 0x50
70 #define BRDCFG1_EMI1_SEL_RGMII 0x00
71 #define BRDCFG1_EMI1_EN 0x08
72 #define BRDCFG1_EMI2_SEL_MASK 0x06
73 #define BRDCFG1_EMI2_SEL_SLOT1 0x00
74 #define BRDCFG1_EMI2_SEL_SLOT2 0x02
75
76 #define BRDCFG2_REG_GPIO_SEL 0x20
77
78 #define PHY_BASE_ADDR 0x00
79
80 /*
81 * BRDCFG1 mask and value for each MAC
82 *
83 * This array contains the BRDCFG1 values (in mask/val format) that route the
84 * MDIO bus to a particular RGMII or SGMII PHY.
85 */
86 struct {
87 u8 mask;
88 u8 val;
89 } mdio_mux[NUM_FM_PORTS];
90
91 /*
92 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
93 * that the mapping must be determined dynamically, or that the lane maps to
94 * something other than a board slot
95 */
96 static u8 lane_to_slot[] = {
97 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
98 };
99
100 /*
101 * Set the board muxing for a given MAC
102 *
103 * The MDIO layer calls this function every time it wants to talk to a PHY.
104 */
hydra_mux_mdio(u8 mask,u8 val)105 void hydra_mux_mdio(u8 mask, u8 val)
106 {
107 clrsetbits_8(&pixis->brdcfg1, mask, val);
108 }
109
110 struct hydra_mdio {
111 u8 mask;
112 u8 val;
113 struct mii_dev *realbus;
114 };
115
hydra_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)116 static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
117 int regnum)
118 {
119 struct hydra_mdio *priv = bus->priv;
120
121 hydra_mux_mdio(priv->mask, priv->val);
122
123 return priv->realbus->read(priv->realbus, addr, devad, regnum);
124 }
125
hydra_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)126 static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
127 int regnum, u16 value)
128 {
129 struct hydra_mdio *priv = bus->priv;
130
131 hydra_mux_mdio(priv->mask, priv->val);
132
133 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
134 }
135
hydra_mdio_reset(struct mii_dev * bus)136 static int hydra_mdio_reset(struct mii_dev *bus)
137 {
138 struct hydra_mdio *priv = bus->priv;
139
140 return priv->realbus->reset(priv->realbus);
141 }
142
hydra_mdio_set_mux(char * name,u8 mask,u8 val)143 static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
144 {
145 struct mii_dev *bus = miiphy_get_dev_by_name(name);
146 struct hydra_mdio *priv = bus->priv;
147
148 priv->mask = mask;
149 priv->val = val;
150 }
151
hydra_mdio_init(char * realbusname,char * fakebusname)152 static int hydra_mdio_init(char *realbusname, char *fakebusname)
153 {
154 struct hydra_mdio *hmdio;
155 struct mii_dev *bus = mdio_alloc();
156
157 if (!bus) {
158 printf("Failed to allocate Hydra MDIO bus\n");
159 return -1;
160 }
161
162 hmdio = malloc(sizeof(*hmdio));
163 if (!hmdio) {
164 printf("Failed to allocate Hydra private data\n");
165 free(bus);
166 return -1;
167 }
168
169 bus->read = hydra_mdio_read;
170 bus->write = hydra_mdio_write;
171 bus->reset = hydra_mdio_reset;
172 strcpy(bus->name, fakebusname);
173
174 hmdio->realbus = miiphy_get_dev_by_name(realbusname);
175
176 if (!hmdio->realbus) {
177 printf("No bus with name %s\n", realbusname);
178 free(bus);
179 free(hmdio);
180 return -1;
181 }
182
183 bus->priv = hmdio;
184
185 return mdio_register(bus);
186 }
187
188 /*
189 * Given an alias or a path for a node, set the mux value of that node.
190 *
191 * If 'alias' is not a valid alias, then it is treated as a full path to the
192 * node. No error checking is performed.
193 *
194 * This function is normally called to set the fsl,hydra-mdio-muxval property
195 * of a virtual MDIO node.
196 */
fdt_set_mdio_mux(void * fdt,const char * alias,u32 mux)197 static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
198 {
199 const char *path = fdt_get_alias(fdt, alias);
200
201 if (!path)
202 path = alias;
203
204 do_fixup_by_path(fdt, path, "reg",
205 &mux, sizeof(mux), 1);
206 do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
207 &mux, sizeof(mux), 1);
208 }
209
210 /*
211 * Given the following ...
212 *
213 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
214 * compatible string and 'addr' physical address)
215 *
216 * 2) An Fman port
217 *
218 * ... update the phy-handle property of the Ethernet node to point to the
219 * right PHY. This assumes that we already know the PHY for each port. That
220 * information is stored in mdio_mux[].
221 *
222 * The offset of the Fman Ethernet node is also passed in for convenience, but
223 * it is not used, and we recalculate the offset anyway.
224 *
225 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
226 * Inside the Fman, "ports" are things that connect to MACs. We only call them
227 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
228 * and ports are the same thing.
229 *
230 * Note that this code would be cleaner if had a function called
231 * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
232 * array. That's because all we're doing is figuring out the PHY address for
233 * a given Fman MAC and writing it to the device tree. Well, we already did
234 * the hard work to figure that out in board_eth_init(), so it's silly to
235 * repeat that here.
236 */
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)237 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
238 enum fm_port port, int offset)
239 {
240 unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
241 char phy[16];
242
243 if (port == FM1_10GEC1) {
244 /* XAUI */
245 int lane = serdes_get_first_lane(XAUI_FM1);
246 if (lane >= 0) {
247 /* The XAUI PHY is identified by the slot */
248 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
249 fdt_set_phy_handle(fdt, compat, addr, phy);
250 }
251 return;
252 }
253
254 if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
255 /* RGMII */
256 /* The RGMII PHY is identified by the MAC connected to it */
257 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
258 fdt_set_phy_handle(fdt, compat, addr, phy);
259 return;
260 }
261
262 /* If it's not RGMII or XGMII, it must be SGMII */
263 if (mux) {
264 /* The SGMII PHY is identified by the MAC connected to it */
265 sprintf(phy, "phy_sgmii_%x",
266 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
267 fdt_set_phy_handle(fdt, compat, addr, phy);
268 }
269 }
270
271 #define PIXIS_SW2_LANE_23_SEL 0x80
272 #define PIXIS_SW2_LANE_45_SEL 0x40
273 #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
274 #define PIXIS_SW2_LANE_67_SEL_5 0x00
275 #define PIXIS_SW2_LANE_67_SEL_6 0x20
276 #define PIXIS_SW2_LANE_67_SEL_7 0x10
277 #define PIXIS_SW2_LANE_8_SEL 0x08
278 #define PIXIS_SW2_LANE_1617_SEL 0x04
279
280 /*
281 * Initialize the lane_to_slot[] array.
282 *
283 * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
284 * slots is hard-coded. On the Hydra board, however, the mapping is controlled
285 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
286 * initialized.
287 */
initialize_lane_to_slot(void)288 static void initialize_lane_to_slot(void)
289 {
290 u8 sw2 = in_8(&PIXIS_SW(2));
291
292 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
293 lane_to_slot[3] = lane_to_slot[2];
294
295 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
296 lane_to_slot[5] = lane_to_slot[4];
297
298 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
299 case PIXIS_SW2_LANE_67_SEL_5:
300 lane_to_slot[6] = 5;
301 break;
302 case PIXIS_SW2_LANE_67_SEL_6:
303 lane_to_slot[6] = 6;
304 break;
305 case PIXIS_SW2_LANE_67_SEL_7:
306 lane_to_slot[6] = 7;
307 break;
308 }
309 lane_to_slot[7] = lane_to_slot[6];
310
311 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
312
313 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
314 lane_to_slot[17] = lane_to_slot[16];
315 }
316
317 #endif /* #ifdef CONFIG_FMAN_ENET */
318
319 /*
320 * Configure the status for the virtual MDIO nodes
321 *
322 * Rather than create the virtual MDIO nodes from scratch for each active
323 * virtual MDIO, we expect the DTS to have the nodes defined already, and we
324 * only enable the ones that are actually active.
325 *
326 * We assume that the DTS already hard-codes the status for all the
327 * virtual MDIO nodes to "disabled", so all we need to do is enable the
328 * active ones.
329 *
330 * For SGMII, we also need to set the mux value in the node.
331 */
fdt_fixup_board_enet(void * fdt)332 void fdt_fixup_board_enet(void *fdt)
333 {
334 #ifdef CONFIG_FMAN_ENET
335 unsigned int i;
336 int lane;
337
338 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
339 int idx = i - FM1_DTSEC1;
340
341 switch (fm_info_get_enet_if(i)) {
342 case PHY_INTERFACE_MODE_SGMII:
343 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
344 if (lane >= 0) {
345 fdt_status_okay_by_alias(fdt, "emi1_sgmii");
346 /* Also set the MUX value */
347 fdt_set_mdio_mux(fdt, "emi1_sgmii",
348 mdio_mux[i].val);
349 }
350 break;
351 case PHY_INTERFACE_MODE_RGMII:
352 fdt_status_okay_by_alias(fdt, "emi1_rgmii");
353 break;
354 default:
355 break;
356 }
357 }
358
359 lane = serdes_get_first_lane(XAUI_FM1);
360 if (lane >= 0)
361 fdt_status_okay_by_alias(fdt, "emi2_xgmii");
362 #endif
363 }
364
board_eth_init(bd_t * bis)365 int board_eth_init(bd_t *bis)
366 {
367 #ifdef CONFIG_FMAN_ENET
368 struct fsl_pq_mdio_info dtsec_mdio_info;
369 struct tgec_mdio_info tgec_mdio_info;
370 unsigned int i, slot;
371 int lane;
372 struct mii_dev *bus;
373
374 printf("Initializing Fman\n");
375
376 initialize_lane_to_slot();
377
378 /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
379 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
380
381 memset(mdio_mux, 0, sizeof(mdio_mux));
382
383 dtsec_mdio_info.regs =
384 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
385 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
386
387 /* Register the real 1G MDIO bus */
388 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
389
390 tgec_mdio_info.regs =
391 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
392 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
393
394 /* Register the real 10G MDIO bus */
395 fm_tgec_mdio_init(bis, &tgec_mdio_info);
396
397 /* Register the three virtual MDIO front-ends */
398 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
399 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
400
401 /*
402 * Program the DTSEC PHY addresses assuming that they are all SGMII.
403 * For any DTSEC that's RGMII, we'll override its PHY address later.
404 * We assume that DTSEC5 is only used for RGMII.
405 */
406 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
407 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
408 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
409 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
410
411 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
412 int idx = i - FM1_DTSEC1;
413
414 switch (fm_info_get_enet_if(i)) {
415 case PHY_INTERFACE_MODE_SGMII:
416 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
417 if (lane < 0)
418 break;
419 slot = lane_to_slot[lane];
420 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
421 switch (slot) {
422 case 1:
423 /* Always DTSEC5 on Bank 3 */
424 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
425 BRDCFG1_EMI1_EN;
426 break;
427 case 2:
428 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
429 BRDCFG1_EMI1_EN;
430 break;
431 case 5:
432 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
433 BRDCFG1_EMI1_EN;
434 break;
435 case 6:
436 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
437 BRDCFG1_EMI1_EN;
438 break;
439 case 7:
440 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
441 BRDCFG1_EMI1_EN;
442 break;
443 };
444
445 hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
446 mdio_mux[i].mask, mdio_mux[i].val);
447 fm_info_set_mdio(i,
448 miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
449 break;
450 case PHY_INTERFACE_MODE_RGMII:
451 /*
452 * If DTSEC4 is RGMII, then it's routed via via EC1 to
453 * the first on-board RGMII port. If DTSEC5 is RGMII,
454 * then it's routed via via EC2 to the second on-board
455 * RGMII port. The other DTSECs cannot be routed to
456 * RGMII.
457 */
458 fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
459 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
460 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
461 BRDCFG1_EMI1_EN;
462 hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
463 mdio_mux[i].mask, mdio_mux[i].val);
464 fm_info_set_mdio(i,
465 miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
466 break;
467 case PHY_INTERFACE_MODE_NONE:
468 fm_info_set_phy_address(i, 0);
469 break;
470 default:
471 printf("Fman1: DTSEC%u set to unknown interface %i\n",
472 idx + 1, fm_info_get_enet_if(i));
473 fm_info_set_phy_address(i, 0);
474 break;
475 }
476 }
477
478 bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
479 set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
480
481 /*
482 * For 10G, we only support one XAUI card per Fman. If present, then we
483 * force its routing and never touch those bits again, which removes the
484 * need for Linux to do any muxing. This works because of the way
485 * BRDCFG1 is defined, but it's a bit hackish.
486 *
487 * The PHY address for the XAUI card depends on which slot it's in. The
488 * macros we use imply that the PHY address is based on which FM, but
489 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
490 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
491 * check the actual slot and just use the macros as-is, even though
492 * the P3041 and P5020 only have one Fman.
493 */
494 lane = serdes_get_first_lane(XAUI_FM1);
495 if (lane >= 0) {
496 slot = lane_to_slot[lane];
497 if (slot == 1) {
498 /* XAUI card is in slot 1 */
499 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
500 BRDCFG1_EMI2_SEL_SLOT1);
501 fm_info_set_phy_address(FM1_10GEC1,
502 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
503 } else {
504 /* XAUI card is in slot 2 */
505 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
506 BRDCFG1_EMI2_SEL_SLOT2);
507 fm_info_set_phy_address(FM1_10GEC1,
508 CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
509 }
510 }
511
512 fm_info_set_mdio(FM1_10GEC1,
513 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
514
515 cpu_eth_init(bis);
516 #endif
517
518 return pci_eth_init(bis);
519 }
520