1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017-2018 NXP
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/fsl_serdes.h>
11 #ifdef CONFIG_FSL_LS_PPA
12 #include <asm/arch/ppa.h>
13 #endif
14 #include <asm/arch/mmu.h>
15 #include <asm/arch/soc.h>
16 #include <fsl_esdhc.h>
17 #include <hwconfig.h>
18 #include <environment.h>
19 #include <fsl_mmdc.h>
20 #include <netdev.h>
21 #include <fsl_sec.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
get_board_version(void)25 static inline int get_board_version(void)
26 {
27 struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
28 int val;
29
30 val = in_be32(&pgpio->gpdat);
31
32 return val;
33 }
34
checkboard(void)35 int checkboard(void)
36 {
37 #ifdef CONFIG_TARGET_LS1012AFRDM
38 puts("Board: LS1012AFRDM ");
39 #else
40 int rev;
41
42 rev = get_board_version();
43
44 puts("Board: FRWY-LS1012A ");
45
46 puts("Version");
47
48 switch (rev) {
49 case BOARD_REV_A:
50 puts(": RevA ");
51 break;
52 case BOARD_REV_B:
53 puts(": RevB ");
54 break;
55 default:
56 puts(": unknown");
57 break;
58 }
59 #endif
60
61 return 0;
62 }
63
64 #ifdef CONFIG_TARGET_LS1012AFRWY
esdhc_status_fixup(void * blob,const char * compat)65 int esdhc_status_fixup(void *blob, const char *compat)
66 {
67 char esdhc0_path[] = "/soc/esdhc@1560000";
68 char esdhc1_path[] = "/soc/esdhc@1580000";
69
70 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
71 sizeof("okay"), 1);
72
73 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
74 sizeof("disabled"), 1);
75 return 0;
76 }
77 #endif
78
dram_init(void)79 int dram_init(void)
80 {
81 #ifdef CONFIG_TARGET_LS1012AFRWY
82 int board_rev;
83 #endif
84 struct fsl_mmdc_info mparam = {
85 0x04180000, /* mdctl */
86 0x00030035, /* mdpdc */
87 0x12554000, /* mdotc */
88 0xbabf7954, /* mdcfg0 */
89 0xdb328f64, /* mdcfg1 */
90 0x01ff00db, /* mdcfg2 */
91 0x00001680, /* mdmisc */
92 0x0f3c8000, /* mdref */
93 0x00002000, /* mdrwd */
94 0x00bf1023, /* mdor */
95 0x0000003f, /* mdasp */
96 0x0000022a, /* mpodtctrl */
97 0xa1390003, /* mpzqhwctrl */
98 };
99
100 #ifdef CONFIG_TARGET_LS1012AFRWY
101 board_rev = get_board_version();
102
103 if (board_rev & BOARD_REV_B) {
104 mparam.mdctl = 0x05180000;
105 gd->ram_size = SYS_SDRAM_SIZE_1024;
106 } else {
107 gd->ram_size = SYS_SDRAM_SIZE_512;
108 }
109 #else
110 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
111 #endif
112 mmdc_init(&mparam);
113
114 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
115 /* This will break-before-make MMU for DDR */
116 update_early_mmu_table();
117 #endif
118
119 return 0;
120 }
121
board_early_init_f(void)122 int board_early_init_f(void)
123 {
124 fsl_lsch2_early_init_f();
125
126 return 0;
127 }
128
board_init(void)129 int board_init(void)
130 {
131 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
132 CONFIG_SYS_CCI400_OFFSET);
133
134 /*
135 * Set CCI-400 control override register to enable barrier
136 * transaction
137 */
138 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
139
140 #ifdef CONFIG_ENV_IS_NOWHERE
141 gd->env_addr = (ulong)&default_environment[0];
142 #endif
143
144 #ifdef CONFIG_FSL_CAAM
145 sec_init();
146 #endif
147
148 #ifdef CONFIG_FSL_LS_PPA
149 ppa_init();
150 #endif
151 return 0;
152 }
153
ft_board_setup(void * blob,bd_t * bd)154 int ft_board_setup(void *blob, bd_t *bd)
155 {
156 arch_fixup_fdt(blob);
157
158 ft_cpu_setup(blob, bd);
159
160 return 0;
161 }
162