1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <fdt_support.h>
9 #include <fsl_ddr_sdram.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ppa.h>
14 #include <asm/arch/fdt.h>
15 #include <asm/arch/mmu.h>
16 #include <asm/arch/soc.h>
17 #include <ahci.h>
18 #include <hwconfig.h>
19 #include <mmc.h>
20 #include <scsi.h>
21 #include <fm_eth.h>
22 #include <fsl_csu.h>
23 #include <fsl_esdhc.h>
24 #include <fsl_ifc.h>
25 #include <fsl_sec.h>
26 #include <spl.h>
27
28 #include "../common/vid.h"
29 #include "../common/qixis.h"
30 #include "ls1046aqds_qixis.h"
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 enum {
35 MUX_TYPE_GPIO,
36 };
37
checkboard(void)38 int checkboard(void)
39 {
40 char buf[64];
41 #ifndef CONFIG_SD_BOOT
42 u8 sw;
43 #endif
44
45 puts("Board: LS1046AQDS, boot from ");
46
47 #ifdef CONFIG_SD_BOOT
48 puts("SD\n");
49 #else
50 sw = QIXIS_READ(brdcfg[0]);
51 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52
53 if (sw < 0x8)
54 printf("vBank: %d\n", sw);
55 else if (sw == 0x8)
56 puts("PromJet\n");
57 else if (sw == 0x9)
58 puts("NAND\n");
59 else if (sw == 0xF)
60 printf("QSPI\n");
61 else
62 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
63 #endif
64
65 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
66 QIXIS_READ(id), QIXIS_READ(arch));
67
68 printf("FPGA: v%d (%s), build %d\n",
69 (int)QIXIS_READ(scver), qixis_read_tag(buf),
70 (int)qixis_read_minor());
71
72 return 0;
73 }
74
if_board_diff_clk(void)75 bool if_board_diff_clk(void)
76 {
77 u8 diff_conf = QIXIS_READ(brdcfg[11]);
78
79 return diff_conf & 0x40;
80 }
81
get_board_sys_clk(void)82 unsigned long get_board_sys_clk(void)
83 {
84 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
85
86 switch (sysclk_conf & 0x0f) {
87 case QIXIS_SYSCLK_64:
88 return 64000000;
89 case QIXIS_SYSCLK_83:
90 return 83333333;
91 case QIXIS_SYSCLK_100:
92 return 100000000;
93 case QIXIS_SYSCLK_125:
94 return 125000000;
95 case QIXIS_SYSCLK_133:
96 return 133333333;
97 case QIXIS_SYSCLK_150:
98 return 150000000;
99 case QIXIS_SYSCLK_160:
100 return 160000000;
101 case QIXIS_SYSCLK_166:
102 return 166666666;
103 }
104
105 return 66666666;
106 }
107
get_board_ddr_clk(void)108 unsigned long get_board_ddr_clk(void)
109 {
110 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
111
112 if (if_board_diff_clk())
113 return get_board_sys_clk();
114 switch ((ddrclk_conf & 0x30) >> 4) {
115 case QIXIS_DDRCLK_100:
116 return 100000000;
117 case QIXIS_DDRCLK_125:
118 return 125000000;
119 case QIXIS_DDRCLK_133:
120 return 133333333;
121 }
122
123 return 66666666;
124 }
125
126 #ifdef CONFIG_LPUART
get_lpuart_clk(void)127 u32 get_lpuart_clk(void)
128 {
129 return gd->bus_clk;
130 }
131 #endif
132
select_i2c_ch_pca9547(u8 ch)133 int select_i2c_ch_pca9547(u8 ch)
134 {
135 int ret;
136
137 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
138 if (ret) {
139 puts("PCA: failed to select proper channel\n");
140 return ret;
141 }
142
143 return 0;
144 }
145
dram_init(void)146 int dram_init(void)
147 {
148 /*
149 * When resuming from deep sleep, the I2C channel may not be
150 * in the default channel. So, switch to the default channel
151 * before accessing DDR SPD.
152 */
153 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
154 fsl_initdram();
155 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
156 /* This will break-before-make MMU for DDR */
157 update_early_mmu_table();
158 #endif
159
160 return 0;
161 }
162
i2c_multiplexer_select_vid_channel(u8 channel)163 int i2c_multiplexer_select_vid_channel(u8 channel)
164 {
165 return select_i2c_ch_pca9547(channel);
166 }
167
board_early_init_f(void)168 int board_early_init_f(void)
169 {
170 #ifdef CONFIG_HAS_FSL_XHCI_USB
171 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
172 u32 usb_pwrfault;
173 #endif
174 #ifdef CONFIG_LPUART
175 u8 uart;
176 #endif
177
178 #ifdef CONFIG_SYS_I2C_EARLY_INIT
179 i2c_early_init_f();
180 #endif
181 fsl_lsch2_early_init_f();
182
183 #ifdef CONFIG_HAS_FSL_XHCI_USB
184 out_be32(&scfg->rcwpmuxcr0, 0x3333);
185 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
186 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
187 SCFG_USBPWRFAULT_USB3_SHIFT) |
188 (SCFG_USBPWRFAULT_DEDICATED <<
189 SCFG_USBPWRFAULT_USB2_SHIFT) |
190 (SCFG_USBPWRFAULT_SHARED <<
191 SCFG_USBPWRFAULT_USB1_SHIFT);
192 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
193 #endif
194
195 #ifdef CONFIG_LPUART
196 /* We use lpuart0 as system console */
197 uart = QIXIS_READ(brdcfg[14]);
198 uart &= ~CFG_UART_MUX_MASK;
199 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
200 QIXIS_WRITE(brdcfg[14], uart);
201 #endif
202
203 return 0;
204 }
205
206 #ifdef CONFIG_FSL_DEEP_SLEEP
207 /* determine if it is a warm boot */
is_warm_boot(void)208 bool is_warm_boot(void)
209 {
210 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
211 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
212
213 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
214 return 1;
215
216 return 0;
217 }
218 #endif
219
config_board_mux(int ctrl_type)220 int config_board_mux(int ctrl_type)
221 {
222 u8 reg14;
223
224 reg14 = QIXIS_READ(brdcfg[14]);
225
226 switch (ctrl_type) {
227 case MUX_TYPE_GPIO:
228 reg14 = (reg14 & (~0x6)) | 0x2;
229 break;
230 default:
231 puts("Unsupported mux interface type\n");
232 return -1;
233 }
234
235 QIXIS_WRITE(brdcfg[14], reg14);
236
237 return 0;
238 }
239
config_serdes_mux(void)240 int config_serdes_mux(void)
241 {
242 return 0;
243 }
244
245 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)246 int misc_init_r(void)
247 {
248 if (hwconfig("gpio"))
249 config_board_mux(MUX_TYPE_GPIO);
250
251 return 0;
252 }
253 #endif
254
board_init(void)255 int board_init(void)
256 {
257 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
258
259 #ifdef CONFIG_SYS_FSL_SERDES
260 config_serdes_mux();
261 #endif
262
263 if (adjust_vdd(0))
264 printf("Warning: Adjusting core voltage failed.\n");
265
266 #ifdef CONFIG_FSL_LS_PPA
267 ppa_init();
268 #endif
269
270 #ifdef CONFIG_SECURE_BOOT
271 /*
272 * In case of Secure Boot, the IBR configures the SMMU
273 * to allow only Secure transactions.
274 * SMMU must be reset in bypass mode.
275 * Set the ClientPD bit and Clear the USFCFG Bit
276 */
277 u32 val;
278 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
279 out_le32(SMMU_SCR0, val);
280 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
281 out_le32(SMMU_NSCR0, val);
282 #endif
283
284 #ifdef CONFIG_FSL_CAAM
285 sec_init();
286 #endif
287
288 return 0;
289 }
290
291 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)292 int ft_board_setup(void *blob, bd_t *bd)
293 {
294 u64 base[CONFIG_NR_DRAM_BANKS];
295 u64 size[CONFIG_NR_DRAM_BANKS];
296 u8 reg;
297
298 /* fixup DT for the two DDR banks */
299 base[0] = gd->bd->bi_dram[0].start;
300 size[0] = gd->bd->bi_dram[0].size;
301 base[1] = gd->bd->bi_dram[1].start;
302 size[1] = gd->bd->bi_dram[1].size;
303
304 fdt_fixup_memory_banks(blob, base, size, 2);
305 ft_cpu_setup(blob, bd);
306
307 #ifdef CONFIG_SYS_DPAA_FMAN
308 fdt_fixup_fman_ethernet(blob);
309 fdt_fixup_board_enet(blob);
310 #endif
311
312 reg = QIXIS_READ(brdcfg[0]);
313 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
314
315 /* Disable IFC if QSPI is enabled */
316 if (reg == 0xF)
317 do_fixup_by_compat(blob, "fsl,ifc",
318 "status", "disabled", 8 + 1, 1);
319
320 return 0;
321 }
322 #endif
323
flash_read8(void * addr)324 u8 flash_read8(void *addr)
325 {
326 return __raw_readb(addr + 1);
327 }
328
flash_write16(u16 val,void * addr)329 void flash_write16(u16 val, void *addr)
330 {
331 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
332
333 __raw_writew(shftval, addr);
334 }
335
flash_read16(void * addr)336 u16 flash_read16(void *addr)
337 {
338 u16 val = __raw_readw(addr);
339
340 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
341 }
342