1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <fsl_ddr_sdram.h>
8 #include <fsl_ddr_dimm_params.h>
9 #include <asm/arch/soc.h>
10 #include <asm/arch/clock.h>
11 #include "ddr.h"
12
13 DECLARE_GLOBAL_DATA_PTR;
14
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)15 void fsl_ddr_board_options(memctl_options_t *popts,
16 dimm_params_t *pdimm,
17 unsigned int ctrl_num)
18 {
19 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
20 u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
21 #endif
22 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
23 ulong ddr_freq;
24 int slot;
25
26 if (ctrl_num > 2) {
27 printf("Not supported controller number %d\n", ctrl_num);
28 return;
29 }
30
31 for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
32 if (pdimm[slot].n_ranks)
33 break;
34 }
35
36 if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
37 return;
38
39 /*
40 * we use identical timing for all slots. If needed, change the code
41 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
42 */
43 if (popts->registered_dimm_en)
44 pbsp = rdimms[ctrl_num];
45 else
46 pbsp = udimms[ctrl_num];
47
48
49 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
50 * freqency and n_banks specified in board_specific_parameters table.
51 */
52 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
53 while (pbsp->datarate_mhz_high) {
54 if (pbsp->n_ranks == pdimm[slot].n_ranks &&
55 (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
56 if (ddr_freq <= pbsp->datarate_mhz_high) {
57 popts->clk_adjust = pbsp->clk_adjust;
58 popts->wrlvl_start = pbsp->wrlvl_start;
59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
61 goto found;
62 }
63 pbsp_highest = pbsp;
64 }
65 pbsp++;
66 }
67
68 if (pbsp_highest) {
69 printf("Error: board specific timing not found for data rate %lu MT/s\n"
70 "Trying to use the highest speed (%u) parameters\n",
71 ddr_freq, pbsp_highest->datarate_mhz_high);
72 popts->clk_adjust = pbsp_highest->clk_adjust;
73 popts->wrlvl_start = pbsp_highest->wrlvl_start;
74 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
75 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
76 } else {
77 panic("DIMM is not supported by this board");
78 }
79 found:
80 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
81 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
82 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
83 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
84 pbsp->wrlvl_ctl_3);
85 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
86 if (ctrl_num == CONFIG_DP_DDR_CTRL) {
87 if (popts->registered_dimm_en)
88 printf("WARN: RDIMM not supported.\n");
89 /* force DDR bus width to 32 bits */
90 popts->data_bus_width = 1;
91 popts->otf_burst_chop_en = 0;
92 popts->burst_length = DDR_BL8;
93 popts->bstopre = 0; /* enable auto precharge */
94 /*
95 * Layout optimization results byte mapping
96 * Byte 0 -> Byte ECC
97 * Byte 1 -> Byte 3
98 * Byte 2 -> Byte 2
99 * Byte 3 -> Byte 1
100 * Byte ECC -> Byte 0
101 */
102 dq_mapping_0 = pdimm[slot].dq_mapping[0];
103 dq_mapping_2 = pdimm[slot].dq_mapping[2];
104 dq_mapping_3 = pdimm[slot].dq_mapping[3];
105 pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
106 pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
107 pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
108 pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
109 pdimm[slot].dq_mapping[6] = dq_mapping_2;
110 pdimm[slot].dq_mapping[7] = dq_mapping_3;
111 pdimm[slot].dq_mapping[8] = dq_mapping_0;
112 pdimm[slot].dq_mapping[9] = 0;
113 pdimm[slot].dq_mapping[10] = 0;
114 pdimm[slot].dq_mapping[11] = 0;
115 pdimm[slot].dq_mapping[12] = 0;
116 pdimm[slot].dq_mapping[13] = 0;
117 pdimm[slot].dq_mapping[14] = 0;
118 pdimm[slot].dq_mapping[15] = 0;
119 pdimm[slot].dq_mapping[16] = 0;
120 pdimm[slot].dq_mapping[17] = 0;
121 }
122 #endif
123 /* To work at higher than 1333MT/s */
124 popts->half_strength_driver_enable = 0;
125 /*
126 * Write leveling override
127 */
128 popts->wrlvl_override = 1;
129 popts->wrlvl_sample = 0x0; /* 32 clocks */
130
131 /*
132 * Rtt and Rtt_WR override
133 */
134 popts->rtt_override = 0;
135
136 /* Enable ZQ calibration */
137 popts->zq_en = 1;
138
139 /* optimize cpo for erratum A-009942 */
140 popts->cpo_sample = 0x6e;
141
142 if (ddr_freq < 2350) {
143 if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
144 /* four chip-selects */
145 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
146 DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
147 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
148 popts->twot_en = 1; /* enable 2T timing */
149 } else {
150 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
151 DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
152 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
153 DDR_CDR2_VREF_RANGE_2;
154 }
155 } else {
156 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
157 DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
158 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
159 DDR_CDR2_VREF_RANGE_2;
160 }
161 }
162
fsl_initdram(void)163 int fsl_initdram(void)
164 {
165 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
166 gd->ram_size = fsl_ddr_sdram_size();
167 #else
168 puts("Initializing DDR....using SPD\n");
169
170 gd->ram_size = fsl_ddr_sdram();
171 #endif
172
173 return 0;
174 }
175