1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * Authors: Timur Tabi <timur@freescale.com>
5 *
6 * FSL DIU Framebuffer driver
7 */
8
9 #include <common.h>
10 #include <command.h>
11 #include <linux/ctype.h>
12 #include <asm/io.h>
13 #include <stdio_dev.h>
14 #include <video_fb.h>
15 #include <fsl_diu_fb.h>
16
17 #define PMUXCR_ELBCDIU_MASK 0xc0000000
18 #define PMUXCR_ELBCDIU_NOR16 0x80000000
19 #define PMUXCR_ELBCDIU_DIU 0x40000000
20
21 /*
22 * DIU Area Descriptor
23 *
24 * Note that we need to byte-swap the value before it's written to the AD
25 * register. So even though the registers don't look like they're in the same
26 * bit positions as they are on the MPC8610, the same value is written to the
27 * AD register on the MPC8610 and on the P1022.
28 */
29 #define AD_BYTE_F 0x10000000
30 #define AD_ALPHA_C_SHIFT 25
31 #define AD_BLUE_C_SHIFT 23
32 #define AD_GREEN_C_SHIFT 21
33 #define AD_RED_C_SHIFT 19
34 #define AD_PIXEL_S_SHIFT 16
35 #define AD_COMP_3_SHIFT 12
36 #define AD_COMP_2_SHIFT 8
37 #define AD_COMP_1_SHIFT 4
38 #define AD_COMP_0_SHIFT 0
39
40 /*
41 * Variables used by the DIU/LBC switching code. It's safe to makes these
42 * global, because the DIU requires DDR, so we'll only run this code after
43 * relocation.
44 */
45 static u32 pmuxcr;
46
diu_set_pixel_clock(unsigned int pixclock)47 void diu_set_pixel_clock(unsigned int pixclock)
48 {
49 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 unsigned long speed_ccb, temp;
51 u32 pixval;
52
53 speed_ccb = get_bus_freq(0);
54 temp = 1000000000 / pixclock;
55 temp *= 1000;
56 pixval = speed_ccb / temp;
57 debug("DIU pixval = %u\n", pixval);
58
59 /* Modify PXCLK in GUTS CLKDVDR */
60 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
61 out_be32(&gur->clkdvdr, temp); /* turn off clock */
62 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
63 }
64
platform_diu_init(unsigned int xres,unsigned int yres,const char * port)65 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
66 {
67 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68 u32 pixel_format;
69
70 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
71 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
72 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
73 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
74 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
75
76 printf("DIU: Switching to %ux%u\n", xres, yres);
77
78 /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
79 clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
80 pmuxcr = in_be32(&gur->pmuxcr);
81
82 return fsl_diu_init(xres, yres, pixel_format, 0);
83 }
84