1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
4 * Copyright (C) 2017, Grinn - http://grinn-global.com/
5 */
6
7 #include <common.h>
8 #include <asm/arch/chilisom.h>
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/omap.h>
12 #include <asm/arch/mem.h>
13 #include <asm/arch/mmc_host_def.h>
14 #include <asm/arch/mux.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/emif.h>
17 #include <asm/io.h>
18 #include <cpsw.h>
19 #include <environment.h>
20 #include <errno.h>
21 #include <miiphy.h>
22 #include <serial.h>
23 #include <spl.h>
24 #include <watchdog.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 static __maybe_unused struct ctrl_dev *cdev =
29 (struct ctrl_dev *)CTRL_DEVICE_BASE;
30
31 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
32 static struct module_pin_mux uart0_pin_mux[] = {
33 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
34 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
35 {-1},
36 };
37
38 static struct module_pin_mux mmc0_pin_mux[] = {
39 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
40 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
41 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
42 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
43 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
44 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
45 {-1},
46 };
47
48 static struct module_pin_mux rmii1_pin_mux[] = {
49 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
50 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
51 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
52 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
53 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
54 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
55 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
56 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
57 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
58 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
59 {-1},
60 };
61
enable_board_pin_mux(void)62 static void enable_board_pin_mux(void)
63 {
64 chilisom_enable_pin_mux();
65
66 /* chiliboard pinmux */
67 configure_module_pin_mux(rmii1_pin_mux);
68 configure_module_pin_mux(mmc0_pin_mux);
69 }
70 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
71
72 #ifndef CONFIG_DM_SERIAL
default_serial_console(void)73 struct serial_device *default_serial_console(void)
74 {
75 return &eserial1_device;
76 }
77 #endif
78
79 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
set_uart_mux_conf(void)80 void set_uart_mux_conf(void)
81 {
82 configure_module_pin_mux(uart0_pin_mux);
83 }
84
set_mux_conf_regs(void)85 void set_mux_conf_regs(void)
86 {
87 enable_board_pin_mux();
88 }
89
am33xx_spl_board_init(void)90 void am33xx_spl_board_init(void)
91 {
92 chilisom_spl_board_init();
93 }
94 #endif
95
96 /*
97 * Basic board specific setup. Pinmux has been handled already.
98 */
board_init(void)99 int board_init(void)
100 {
101 #if defined(CONFIG_HW_WATCHDOG)
102 hw_watchdog_init();
103 #endif
104
105 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
106 gpmc_init();
107
108 return 0;
109 }
110
111 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)112 int board_late_init(void)
113 {
114 #if !defined(CONFIG_SPL_BUILD)
115 uint8_t mac_addr[6];
116 uint32_t mac_hi, mac_lo;
117
118 /* try reading mac address from efuse */
119 mac_lo = readl(&cdev->macid0l);
120 mac_hi = readl(&cdev->macid0h);
121 mac_addr[0] = mac_hi & 0xFF;
122 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
123 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
124 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
125 mac_addr[4] = mac_lo & 0xFF;
126 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
127
128 if (!env_get("ethaddr")) {
129 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
130
131 if (is_valid_ethaddr(mac_addr))
132 eth_env_set_enetaddr("ethaddr", mac_addr);
133 }
134
135 mac_lo = readl(&cdev->macid1l);
136 mac_hi = readl(&cdev->macid1h);
137 mac_addr[0] = mac_hi & 0xFF;
138 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
139 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
140 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
141 mac_addr[4] = mac_lo & 0xFF;
142 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
143
144 if (!env_get("eth1addr")) {
145 if (is_valid_ethaddr(mac_addr))
146 eth_env_set_enetaddr("eth1addr", mac_addr);
147 }
148 #endif
149
150 return 0;
151 }
152 #endif
153
154 #if !defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) && \
155 !defined(CONFIG_SPL_BUILD)
cpsw_control(int enabled)156 static void cpsw_control(int enabled)
157 {
158 /* VTP can be added here */
159
160 return;
161 }
162
163 static struct cpsw_slave_data cpsw_slaves[] = {
164 {
165 .slave_reg_ofs = 0x208,
166 .sliver_reg_ofs = 0xd80,
167 .phy_addr = 0,
168 }
169 };
170
171 static struct cpsw_platform_data cpsw_data = {
172 .mdio_base = CPSW_MDIO_BASE,
173 .cpsw_base = CPSW_BASE,
174 .mdio_div = 0xff,
175 .channels = 8,
176 .cpdma_reg_ofs = 0x800,
177 .slaves = 1,
178 .slave_data = cpsw_slaves,
179 .ale_reg_ofs = 0xd00,
180 .ale_entries = 1024,
181 .host_port_reg_ofs = 0x108,
182 .hw_stats_reg_ofs = 0x900,
183 .bd_ram_ofs = 0x2000,
184 .mac_control = (1 << 5),
185 .control = cpsw_control,
186 .host_port_num = 0,
187 .version = CPSW_CTRL_VERSION_2,
188 };
189
board_eth_init(bd_t * bis)190 int board_eth_init(bd_t *bis)
191 {
192 int rv, n = 0;
193
194 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
195 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
196
197 rv = cpsw_register(&cpsw_data);
198 if (rv < 0)
199 printf("Error %d registering CPSW switch\n", rv);
200 else
201 n += rv;
202
203 return n;
204 }
205 #endif
206