1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * mux.c
4 *
5 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
6 */
7
8 #include <common.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/mux.h>
12 #include <asm/io.h>
13 #include <i2c.h>
14 #include "board.h"
15
16 static struct module_pin_mux uart0_pin_mux[] = {
17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
19 {-1},
20 };
21
22 static struct module_pin_mux uart1_pin_mux[] = {
23 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
24 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
25 {-1},
26 };
27
28 static struct module_pin_mux uart2_pin_mux[] = {
29 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
30 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
31 {-1},
32 };
33
34 static struct module_pin_mux uart3_pin_mux[] = {
35 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
36 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
37 {-1},
38 };
39
40 static struct module_pin_mux uart4_pin_mux[] = {
41 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
42 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
43 {-1},
44 };
45
46 static struct module_pin_mux uart5_pin_mux[] = {
47 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
48 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
49 {-1},
50 };
51
52 static struct module_pin_mux mmc0_pin_mux[] = {
53 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
54 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
55 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
56 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
57 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
58 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
59 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
60 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
61 {-1},
62 };
63
64 static struct module_pin_mux mmc1_pin_mux[] = {
65 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
66 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
67 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
68 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
69 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
70 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
71 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
72 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
73 {-1},
74 };
75
76 static struct module_pin_mux i2c0_pin_mux[] = {
77 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
78 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
79 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
80 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
81 {-1},
82 };
83
84 static struct module_pin_mux i2c1_pin_mux[] = {
85 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
86 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
87 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
88 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
89 {-1},
90 };
91
92 static struct module_pin_mux mii1_pin_mux[] = {
93 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
94 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
95 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
96 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
97 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
98 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
99 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
100 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
101 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
102 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
103 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
104 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
105 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
106 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
107 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
108 {-1},
109 };
110
111
enable_uart0_pin_mux(void)112 void enable_uart0_pin_mux(void)
113 {
114 configure_module_pin_mux(uart0_pin_mux);
115 }
116
enable_uart1_pin_mux(void)117 void enable_uart1_pin_mux(void)
118 {
119 configure_module_pin_mux(uart1_pin_mux);
120 }
121
enable_uart2_pin_mux(void)122 void enable_uart2_pin_mux(void)
123 {
124 configure_module_pin_mux(uart2_pin_mux);
125 }
126
enable_uart3_pin_mux(void)127 void enable_uart3_pin_mux(void)
128 {
129 configure_module_pin_mux(uart3_pin_mux);
130 }
131
enable_uart4_pin_mux(void)132 void enable_uart4_pin_mux(void)
133 {
134 configure_module_pin_mux(uart4_pin_mux);
135 }
136
enable_uart5_pin_mux(void)137 void enable_uart5_pin_mux(void)
138 {
139 configure_module_pin_mux(uart5_pin_mux);
140 }
141
enable_i2c0_pin_mux(void)142 void enable_i2c0_pin_mux(void)
143 {
144 configure_module_pin_mux(i2c0_pin_mux);
145 }
146
enable_board_pin_mux(void)147 void enable_board_pin_mux(void)
148 {
149 configure_module_pin_mux(i2c1_pin_mux);
150 configure_module_pin_mux(mii1_pin_mux);
151 configure_module_pin_mux(mmc0_pin_mux);
152 configure_module_pin_mux(mmc1_pin_mux);
153 }
154