1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/arch/mips/bcm63xx/cpu.c:
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */
9
10 #include <common.h>
11 #include <cpu.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <asm/io.h>
15
16 #define REV_CHIPID_SHIFT 16
17 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
18 #define REV_LONG_CHIPID_SHIFT 12
19 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
20 #define REV_REVID_SHIFT 0
21 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
22
23 #define REG_BCM6328_OTP 0x62c
24 #define BCM6328_TP1_DISABLED BIT(9)
25
26 #define REG_BCM6318_STRAP_OVRDBUS 0x900
27 #define OVRDBUS_6318_FREQ_SHIFT 23
28 #define OVRDBUS_6318_FREQ_MASK (0x3 << OVRDBUS_6318_FREQ_SHIFT)
29
30 #define REG_BCM6328_MISC_STRAPBUS 0x1a40
31 #define STRAPBUS_6328_FCVO_SHIFT 7
32 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
33
34 #define REG_BCM6348_PERF_MIPSPLLCFG 0x34
35 #define MIPSPLLCFG_6348_M1CPU_SHIFT 6
36 #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
37 #define MIPSPLLCFG_6348_N2_SHIFT 15
38 #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
39 #define MIPSPLLCFG_6348_N1_SHIFT 20
40 #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
41
42 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8
43 #define DMIPSPLLCFG_6358_M1_SHIFT 0
44 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
45 #define DMIPSPLLCFG_6358_N1_SHIFT 23
46 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
47 #define DMIPSPLLCFG_6358_N2_SHIFT 29
48 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
49
50 #define REG_BCM6362_MISC_STRAPBUS 0x1814
51 #define STRAPBUS_6362_FCVO_SHIFT 1
52 #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
53
54 #define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0
55 #define DMIPSPLLCFG_6368_P1_SHIFT 0
56 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
57 #define DMIPSPLLCFG_6368_P2_SHIFT 4
58 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
59 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
60 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
61 #define REG_BCM6368_DDR_DMIPSPLLDIV 0x12a4
62 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
63 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
64
65 #define REG_BCM63268_MISC_STRAPBUS 0x1814
66 #define STRAPBUS_63268_FCVO_SHIFT 21
67 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
68
69 struct bmips_cpu_priv;
70
71 struct bmips_cpu_hw {
72 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
73 ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
74 int (*get_cpu_count)(struct bmips_cpu_priv *);
75 };
76
77 struct bmips_cpu_priv {
78 void __iomem *regs;
79 const struct bmips_cpu_hw *hw;
80 };
81
82 /* Specific CPU Ops */
bmips_short_cpu_desc(struct bmips_cpu_priv * priv,char * buf,int size)83 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
84 int size)
85 {
86 unsigned short cpu_id;
87 unsigned char cpu_rev;
88 u32 val;
89
90 val = readl_be(priv->regs);
91 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
92 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
93
94 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
95
96 return 0;
97 }
98
bmips_long_cpu_desc(struct bmips_cpu_priv * priv,char * buf,int size)99 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
100 int size)
101 {
102 unsigned int cpu_id;
103 unsigned char cpu_rev;
104 u32 val;
105
106 val = readl_be(priv->regs);
107 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
108 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
109
110 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
111
112 return 0;
113 }
114
bcm3380_get_cpu_freq(struct bmips_cpu_priv * priv)115 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
116 {
117 return 333000000;
118 }
119
bcm6318_get_cpu_freq(struct bmips_cpu_priv * priv)120 static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv)
121 {
122 unsigned int mips_pll_fcvo;
123
124 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS);
125 mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK)
126 >> OVRDBUS_6318_FREQ_SHIFT;
127
128 switch (mips_pll_fcvo) {
129 case 0:
130 return 166000000;
131 case 1:
132 return 400000000;
133 case 2:
134 return 250000000;
135 case 3:
136 return 333000000;
137 default:
138 return 0;
139 }
140 }
141
bcm6328_get_cpu_freq(struct bmips_cpu_priv * priv)142 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
143 {
144 unsigned int mips_pll_fcvo;
145
146 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
147 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
148 >> STRAPBUS_6328_FCVO_SHIFT;
149
150 switch (mips_pll_fcvo) {
151 case 0x12:
152 case 0x14:
153 case 0x19:
154 return 160000000;
155 case 0x1c:
156 return 192000000;
157 case 0x13:
158 case 0x15:
159 return 200000000;
160 case 0x1a:
161 return 384000000;
162 case 0x16:
163 return 400000000;
164 default:
165 return 320000000;
166 }
167 }
168
bcm6338_get_cpu_freq(struct bmips_cpu_priv * priv)169 static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
170 {
171 return 240000000;
172 }
173
bcm6348_get_cpu_freq(struct bmips_cpu_priv * priv)174 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
175 {
176 unsigned int tmp, n1, n2, m1;
177
178 tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
179 n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
180 n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
181 m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
182
183 return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
184 }
185
bcm6358_get_cpu_freq(struct bmips_cpu_priv * priv)186 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
187 {
188 unsigned int tmp, n1, n2, m1;
189
190 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
191 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
192 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
193 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
194
195 return (16 * 1000000 * n1 * n2) / m1;
196 }
197
bcm6362_get_cpu_freq(struct bmips_cpu_priv * priv)198 static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
199 {
200 unsigned int mips_pll_fcvo;
201
202 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
203 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
204 >> STRAPBUS_6362_FCVO_SHIFT;
205
206 switch (mips_pll_fcvo) {
207 case 0x03:
208 case 0x0b:
209 case 0x13:
210 case 0x1b:
211 return 240000000;
212 case 0x04:
213 case 0x0c:
214 case 0x14:
215 case 0x1c:
216 return 160000000;
217 case 0x05:
218 case 0x0e:
219 case 0x16:
220 case 0x1e:
221 case 0x1f:
222 return 400000000;
223 case 0x06:
224 return 440000000;
225 case 0x07:
226 case 0x17:
227 return 384000000;
228 case 0x15:
229 case 0x1d:
230 return 200000000;
231 default:
232 return 320000000;
233 }
234 }
235
bcm6368_get_cpu_freq(struct bmips_cpu_priv * priv)236 static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
237 {
238 unsigned int tmp, p1, p2, ndiv, m1;
239
240 tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
241 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
242 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
243 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
244 DMIPSPLLCFG_6368_NDIV_SHIFT;
245
246 tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
247 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
248
249 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
250 }
251
bcm63268_get_cpu_freq(struct bmips_cpu_priv * priv)252 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
253 {
254 unsigned int mips_pll_fcvo;
255
256 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
257 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
258 >> STRAPBUS_63268_FCVO_SHIFT;
259
260 switch (mips_pll_fcvo) {
261 case 0x3:
262 case 0xe:
263 return 320000000;
264 case 0xa:
265 return 333000000;
266 case 0x2:
267 case 0xb:
268 case 0xf:
269 return 400000000;
270 default:
271 return 0;
272 }
273 }
274
bcm6328_get_cpu_count(struct bmips_cpu_priv * priv)275 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
276 {
277 u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
278
279 if (val & BCM6328_TP1_DISABLED)
280 return 1;
281 else
282 return 2;
283 }
284
bcm6345_get_cpu_count(struct bmips_cpu_priv * priv)285 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
286 {
287 return 1;
288 }
289
bcm6358_get_cpu_count(struct bmips_cpu_priv * priv)290 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
291 {
292 return 2;
293 }
294
295 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
296 .get_cpu_desc = bmips_short_cpu_desc,
297 .get_cpu_freq = bcm3380_get_cpu_freq,
298 .get_cpu_count = bcm6358_get_cpu_count,
299 };
300
301 static const struct bmips_cpu_hw bmips_cpu_bcm6318 = {
302 .get_cpu_desc = bmips_short_cpu_desc,
303 .get_cpu_freq = bcm6318_get_cpu_freq,
304 .get_cpu_count = bcm6345_get_cpu_count,
305 };
306
307 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
308 .get_cpu_desc = bmips_long_cpu_desc,
309 .get_cpu_freq = bcm6328_get_cpu_freq,
310 .get_cpu_count = bcm6328_get_cpu_count,
311 };
312
313 static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
314 .get_cpu_desc = bmips_short_cpu_desc,
315 .get_cpu_freq = bcm6338_get_cpu_freq,
316 .get_cpu_count = bcm6345_get_cpu_count,
317 };
318
319 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
320 .get_cpu_desc = bmips_short_cpu_desc,
321 .get_cpu_freq = bcm6348_get_cpu_freq,
322 .get_cpu_count = bcm6345_get_cpu_count,
323 };
324
325 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
326 .get_cpu_desc = bmips_short_cpu_desc,
327 .get_cpu_freq = bcm6358_get_cpu_freq,
328 .get_cpu_count = bcm6358_get_cpu_count,
329 };
330
331 static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
332 .get_cpu_desc = bmips_short_cpu_desc,
333 .get_cpu_freq = bcm6362_get_cpu_freq,
334 .get_cpu_count = bcm6358_get_cpu_count,
335 };
336
337 static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
338 .get_cpu_desc = bmips_short_cpu_desc,
339 .get_cpu_freq = bcm6368_get_cpu_freq,
340 .get_cpu_count = bcm6358_get_cpu_count,
341 };
342
343 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
344 .get_cpu_desc = bmips_long_cpu_desc,
345 .get_cpu_freq = bcm63268_get_cpu_freq,
346 .get_cpu_count = bcm6358_get_cpu_count,
347 };
348
349 /* Generic CPU Ops */
bmips_cpu_get_desc(struct udevice * dev,char * buf,int size)350 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
351 {
352 struct bmips_cpu_priv *priv = dev_get_priv(dev);
353 const struct bmips_cpu_hw *hw = priv->hw;
354
355 return hw->get_cpu_desc(priv, buf, size);
356 }
357
bmips_cpu_get_info(struct udevice * dev,struct cpu_info * info)358 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
359 {
360 struct bmips_cpu_priv *priv = dev_get_priv(dev);
361 const struct bmips_cpu_hw *hw = priv->hw;
362
363 info->cpu_freq = hw->get_cpu_freq(priv);
364 info->features = BIT(CPU_FEAT_L1_CACHE);
365 info->features |= BIT(CPU_FEAT_MMU);
366 info->features |= BIT(CPU_FEAT_DEVICE_ID);
367
368 return 0;
369 }
370
bmips_cpu_get_count(struct udevice * dev)371 static int bmips_cpu_get_count(struct udevice *dev)
372 {
373 struct bmips_cpu_priv *priv = dev_get_priv(dev);
374 const struct bmips_cpu_hw *hw = priv->hw;
375
376 return hw->get_cpu_count(priv);
377 }
378
bmips_cpu_get_vendor(struct udevice * dev,char * buf,int size)379 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
380 {
381 snprintf(buf, size, "Broadcom");
382
383 return 0;
384 }
385
386 static const struct cpu_ops bmips_cpu_ops = {
387 .get_desc = bmips_cpu_get_desc,
388 .get_info = bmips_cpu_get_info,
389 .get_count = bmips_cpu_get_count,
390 .get_vendor = bmips_cpu_get_vendor,
391 };
392
393 /* BMIPS CPU driver */
bmips_cpu_bind(struct udevice * dev)394 int bmips_cpu_bind(struct udevice *dev)
395 {
396 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
397
398 plat->cpu_id = dev_read_u32_default(dev, "reg", -1);
399 plat->device_id = read_c0_prid();
400
401 return 0;
402 }
403
bmips_cpu_probe(struct udevice * dev)404 int bmips_cpu_probe(struct udevice *dev)
405 {
406 struct bmips_cpu_priv *priv = dev_get_priv(dev);
407 const struct bmips_cpu_hw *hw =
408 (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
409
410 priv->regs = dev_remap_addr(dev);
411 if (!priv->regs)
412 return -EINVAL;
413
414 priv->hw = hw;
415
416 return 0;
417 }
418
419 static const struct udevice_id bmips_cpu_ids[] = {
420 {
421 .compatible = "brcm,bcm3380-cpu",
422 .data = (ulong)&bmips_cpu_bcm3380,
423 }, {
424 .compatible = "brcm,bcm6318-cpu",
425 .data = (ulong)&bmips_cpu_bcm6318,
426 }, {
427 .compatible = "brcm,bcm6328-cpu",
428 .data = (ulong)&bmips_cpu_bcm6328,
429 }, {
430 .compatible = "brcm,bcm6338-cpu",
431 .data = (ulong)&bmips_cpu_bcm6338,
432 }, {
433 .compatible = "brcm,bcm6348-cpu",
434 .data = (ulong)&bmips_cpu_bcm6348,
435 }, {
436 .compatible = "brcm,bcm6358-cpu",
437 .data = (ulong)&bmips_cpu_bcm6358,
438 }, {
439 .compatible = "brcm,bcm6362-cpu",
440 .data = (ulong)&bmips_cpu_bcm6362,
441 }, {
442 .compatible = "brcm,bcm6368-cpu",
443 .data = (ulong)&bmips_cpu_bcm6368,
444 }, {
445 .compatible = "brcm,bcm63268-cpu",
446 .data = (ulong)&bmips_cpu_bcm63268,
447 },
448 { /* sentinel */ }
449 };
450
451 U_BOOT_DRIVER(bmips_cpu_drv) = {
452 .name = "bmips_cpu",
453 .id = UCLASS_CPU,
454 .of_match = bmips_cpu_ids,
455 .bind = bmips_cpu_bind,
456 .probe = bmips_cpu_probe,
457 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
458 .ops = &bmips_cpu_ops,
459 .flags = DM_FLAG_PRE_RELOC,
460 };
461
462 #ifdef CONFIG_DISPLAY_CPUINFO
print_cpuinfo(void)463 int print_cpuinfo(void)
464 {
465 struct cpu_info cpu;
466 struct udevice *dev;
467 int err;
468 char desc[100];
469
470 err = uclass_get_device(UCLASS_CPU, 0, &dev);
471 if (err)
472 return 0;
473
474 err = cpu_get_info(dev, &cpu);
475 if (err)
476 return 0;
477
478 err = cpu_get_desc(dev, desc, sizeof(desc));
479 if (err)
480 return 0;
481
482 printf("Chip ID: %s, MIPS: ", desc);
483 print_freq(cpu.cpu_freq, "\n");
484
485 return 0;
486 }
487 #endif
488