1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007-2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <malloc.h>
8 #include <asm/fsl_serdes.h>
9
10 DECLARE_GLOBAL_DATA_PTR;
11
12 /*
13 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
14 *
15 * Initialize controller and call the common driver/pci pci_hose_scan to
16 * scan for bridges and devices.
17 *
18 * Hose fields which need to be pre-initialized by board specific code:
19 * regions[]
20 * first_busno
21 *
22 * Fields updated:
23 * last_busno
24 */
25
26 #include <pci.h>
27 #include <asm/io.h>
28 #include <asm/fsl_pci.h>
29
30 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
31 #define CONFIG_SYS_PCI_MEMORY_BUS 0
32 #endif
33
34 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
35 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
36 #endif
37
38 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
39 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
40 #endif
41
42 /* Setup one inbound ATMU window.
43 *
44 * We let the caller decide what the window size should be
45 */
set_inbound_window(volatile pit_t * pi,struct pci_region * r,u64 size)46 static void set_inbound_window(volatile pit_t *pi,
47 struct pci_region *r,
48 u64 size)
49 {
50 u32 sz = (__ilog2_u64(size) - 1);
51 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
52 u32 flag = 0;
53 #else
54 u32 flag = PIWAR_LOCAL;
55 #endif
56
57 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
58
59 out_be32(&pi->pitar, r->phys_start >> 12);
60 out_be32(&pi->piwbar, r->bus_start >> 12);
61 #ifdef CONFIG_SYS_PCI_64BIT
62 out_be32(&pi->piwbear, r->bus_start >> 44);
63 #else
64 out_be32(&pi->piwbear, 0);
65 #endif
66 if (r->flags & PCI_REGION_PREFETCH)
67 flag |= PIWAR_PF;
68 out_be32(&pi->piwar, flag | sz);
69 }
70
fsl_setup_hose(struct pci_controller * hose,unsigned long addr)71 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
72 {
73 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
74
75 /* Reset hose to make sure its in a clean state */
76 memset(hose, 0, sizeof(struct pci_controller));
77
78 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
79
80 return fsl_is_pci_agent(hose);
81 }
82
fsl_pci_setup_inbound_windows(struct pci_controller * hose,u64 out_lo,u8 pcie_cap,volatile pit_t * pi)83 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
84 u64 out_lo, u8 pcie_cap,
85 volatile pit_t *pi)
86 {
87 struct pci_region *r = hose->regions + hose->region_count;
88 u64 sz = min((u64)gd->ram_size, (1ull << 32));
89
90 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
91 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
92 pci_size_t pci_sz;
93
94 /* we have no space available for inbound memory mapping */
95 if (bus_start > out_lo) {
96 printf ("no space for inbound mapping of memory\n");
97 return 0;
98 }
99
100 /* limit size */
101 if ((bus_start + sz) > out_lo) {
102 sz = out_lo - bus_start;
103 debug ("limiting size to %llx\n", sz);
104 }
105
106 pci_sz = 1ull << __ilog2_u64(sz);
107 /*
108 * we can overlap inbound/outbound windows on PCI-E since RX & TX
109 * links a separate
110 */
111 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
112 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
113 (u64)bus_start, (u64)phys_start, (u64)sz);
114 pci_set_region(r, bus_start, phys_start, sz,
115 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
116 PCI_REGION_PREFETCH);
117
118 /* if we aren't an exact power of two match, pci_sz is smaller
119 * round it up to the next power of two. We report the actual
120 * size to pci region tracking.
121 */
122 if (pci_sz != sz)
123 sz = 2ull << __ilog2_u64(sz);
124
125 set_inbound_window(pi--, r++, sz);
126 sz = 0; /* make sure we dont set the R2 window */
127 } else {
128 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
129 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
130 pci_set_region(r, bus_start, phys_start, pci_sz,
131 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
132 PCI_REGION_PREFETCH);
133 set_inbound_window(pi--, r++, pci_sz);
134
135 sz -= pci_sz;
136 bus_start += pci_sz;
137 phys_start += pci_sz;
138
139 pci_sz = 1ull << __ilog2_u64(sz);
140 if (sz) {
141 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
142 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
143 pci_set_region(r, bus_start, phys_start, pci_sz,
144 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
145 PCI_REGION_PREFETCH);
146 set_inbound_window(pi--, r++, pci_sz);
147 sz -= pci_sz;
148 bus_start += pci_sz;
149 phys_start += pci_sz;
150 }
151 }
152
153 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
154 /*
155 * On 64-bit capable systems, set up a mapping for all of DRAM
156 * in high pci address space.
157 */
158 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
159 /* round up to the next largest power of two */
160 if (gd->ram_size > pci_sz)
161 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
162 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
163 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
164 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
165 (u64)pci_sz);
166 pci_set_region(r,
167 CONFIG_SYS_PCI64_MEMORY_BUS,
168 CONFIG_SYS_PCI_MEMORY_PHYS,
169 pci_sz,
170 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
171 PCI_REGION_PREFETCH);
172 set_inbound_window(pi--, r++, pci_sz);
173 #else
174 pci_sz = 1ull << __ilog2_u64(sz);
175 if (sz) {
176 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
177 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
178 pci_set_region(r, bus_start, phys_start, pci_sz,
179 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
180 PCI_REGION_PREFETCH);
181 sz -= pci_sz;
182 bus_start += pci_sz;
183 phys_start += pci_sz;
184 set_inbound_window(pi--, r++, pci_sz);
185 }
186 #endif
187
188 #ifdef CONFIG_PHYS_64BIT
189 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
190 printf("Was not able to map all of memory via "
191 "inbound windows -- %lld remaining\n", sz);
192 #endif
193
194 hose->region_count = r - hose->regions;
195
196 return 1;
197 }
198
199 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
fsl_pcie_boot_master(pit_t * pi)200 static void fsl_pcie_boot_master(pit_t *pi)
201 {
202 /* configure inbound window for slave's u-boot image */
203 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
204 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
205 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
206 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
207 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
208 struct pci_region r_inbound;
209 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
210 - 1;
211 pci_set_region(&r_inbound,
212 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
213 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
214 sz_inbound,
215 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
216
217 set_inbound_window(pi--, &r_inbound,
218 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
219
220 /* configure inbound window for slave's u-boot image */
221 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
222 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
223 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
224 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
225 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
226 pci_set_region(&r_inbound,
227 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
228 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
229 sz_inbound,
230 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
231
232 set_inbound_window(pi--, &r_inbound,
233 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
234
235 /* configure inbound window for slave's ucode and ENV */
236 debug("PCIEBOOT - MASTER: Inbound window for slave's "
237 "ucode and ENV; "
238 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
239 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
240 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
241 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
242 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
243 - 1;
244 pci_set_region(&r_inbound,
245 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
246 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
247 sz_inbound,
248 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
249
250 set_inbound_window(pi--, &r_inbound,
251 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
252 }
253
fsl_pcie_boot_master_release_slave(int port)254 static void fsl_pcie_boot_master_release_slave(int port)
255 {
256 unsigned long release_addr;
257
258 /* now release slave's core 0 */
259 switch (port) {
260 case 1:
261 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
262 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
263 break;
264 #ifdef CONFIG_SYS_PCIE2_MEM_VIRT
265 case 2:
266 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
267 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
268 break;
269 #endif
270 #ifdef CONFIG_SYS_PCIE3_MEM_VIRT
271 case 3:
272 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
273 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
274 break;
275 #endif
276 default:
277 release_addr = 0;
278 break;
279 }
280 if (release_addr != 0) {
281 out_be32((void *)release_addr,
282 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
283 debug("PCIEBOOT - MASTER: "
284 "Release slave successfully! Now the slave should start up!\n");
285 } else {
286 debug("PCIEBOOT - MASTER: "
287 "Release slave failed!\n");
288 }
289 }
290 #endif
291
fsl_pci_init(struct pci_controller * hose,struct fsl_pci_info * pci_info)292 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
293 {
294 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
295 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
296 u16 temp16;
297 u32 temp32;
298 u32 block_rev;
299 int enabled, r, inbound = 0;
300 u16 ltssm;
301 u8 temp8, pcie_cap;
302 int pcie_cap_pos;
303 int pci_dcr;
304 int pci_dsr;
305 int pci_lsr;
306
307 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
308 int pci_lcr;
309 #endif
310
311 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
312 struct pci_region *reg = hose->regions + hose->region_count;
313 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
314
315 /* Initialize ATMU registers based on hose regions and flags */
316 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
317 volatile pit_t *pi;
318
319 u64 out_hi = 0, out_lo = -1ULL;
320 u32 pcicsrbar, pcicsrbar_sz;
321
322 pci_setup_indirect(hose, cfg_addr, cfg_data);
323
324 block_rev = in_be32(&pci->block_rev1);
325 if (PEX_IP_BLK_REV_2_2 <= block_rev) {
326 pi = &pci->pit[2]; /* 0xDC0 */
327 } else {
328 pi = &pci->pit[3]; /* 0xDE0 */
329 }
330
331 /* Handle setup of outbound windows first */
332 for (r = 0; r < hose->region_count; r++) {
333 unsigned long flags = hose->regions[r].flags;
334 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
335
336 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
337 if (flags != PCI_REGION_SYS_MEMORY) {
338 u64 start = hose->regions[r].bus_start;
339 u64 end = start + hose->regions[r].size;
340
341 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
342 out_be32(&po->potar, start >> 12);
343 #ifdef CONFIG_SYS_PCI_64BIT
344 out_be32(&po->potear, start >> 44);
345 #else
346 out_be32(&po->potear, 0);
347 #endif
348 if (hose->regions[r].flags & PCI_REGION_IO) {
349 out_be32(&po->powar, POWAR_EN | sz |
350 POWAR_IO_READ | POWAR_IO_WRITE);
351 } else {
352 out_be32(&po->powar, POWAR_EN | sz |
353 POWAR_MEM_READ | POWAR_MEM_WRITE);
354 out_lo = min(start, out_lo);
355 out_hi = max(end, out_hi);
356 }
357 po++;
358 }
359 }
360 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
361
362 /* setup PCSRBAR/PEXCSRBAR */
363 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
364 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
365 pcicsrbar_sz = ~pcicsrbar_sz + 1;
366
367 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
368 (out_lo > 0x100000000ull))
369 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
370 else
371 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
372 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
373
374 out_lo = min(out_lo, (u64)pcicsrbar);
375
376 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
377
378 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
379 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
380 hose->region_count++;
381
382 /* see if we are a PCIe or PCI controller */
383 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
384 pci_dcr = pcie_cap_pos + 0x08;
385 pci_dsr = pcie_cap_pos + 0x0a;
386 pci_lsr = pcie_cap_pos + 0x12;
387
388 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
389
390 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
391 /* boot from PCIE --master */
392 char *s = env_get("bootmaster");
393 char pcie[6];
394 sprintf(pcie, "PCIE%d", pci_info->pci_num);
395
396 if (s && (strcmp(s, pcie) == 0)) {
397 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
398 pci_info->pci_num);
399 fsl_pcie_boot_master((pit_t *)pi);
400 } else {
401 /* inbound */
402 inbound = fsl_pci_setup_inbound_windows(hose,
403 out_lo, pcie_cap, pi);
404 }
405 #else
406 /* inbound */
407 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
408 #endif
409
410 for (r = 0; r < hose->region_count; r++)
411 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
412 (u64)hose->regions[r].phys_start,
413 (u64)hose->regions[r].bus_start,
414 (u64)hose->regions[r].size,
415 hose->regions[r].flags);
416
417 pci_register_hose(hose);
418 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
419 hose->current_busno = hose->first_busno;
420
421 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
422 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
423 * - Master abort (pci)
424 * - Master PERR (pci)
425 * - ICCA (PCIe)
426 */
427 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
428 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
429 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
430
431 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
432 pci_lcr = pcie_cap_pos + 0x10;
433 temp32 = 0;
434 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
435 temp32 &= ~0x03; /* Disable ASPM */
436 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
437 udelay(1);
438 #endif
439 if (pcie_cap == PCI_CAP_ID_EXP) {
440 if (block_rev >= PEX_IP_BLK_REV_3_0) {
441 #define PEX_CSR0_LTSSM_MASK 0xFC
442 #define PEX_CSR0_LTSSM_SHIFT 2
443 ltssm = (in_be32(&pci->pex_csr0)
444 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
445 enabled = (ltssm == 0x11) ? 1 : 0;
446 #ifdef CONFIG_FSL_PCIE_RESET
447 int i;
448 /* assert PCIe reset */
449 setbits_be32(&pci->pdb_stat, 0x08000000);
450 (void) in_be32(&pci->pdb_stat);
451 udelay(1000);
452 /* clear PCIe reset */
453 clrbits_be32(&pci->pdb_stat, 0x08000000);
454 asm("sync;isync");
455 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
456 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
457 <ssm);
458 udelay(1000);
459 }
460 #endif
461 } else {
462 /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
463 /* enabled = ltssm >= PCI_LTSSM_L0; */
464 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
465 enabled = ltssm >= PCI_LTSSM_L0;
466
467 #ifdef CONFIG_FSL_PCIE_RESET
468 if (ltssm == 1) {
469 int i;
470 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
471 /* assert PCIe reset */
472 setbits_be32(&pci->pdb_stat, 0x08000000);
473 (void) in_be32(&pci->pdb_stat);
474 udelay(100);
475 debug(" Asserting PCIe reset @%p = %x\n",
476 &pci->pdb_stat, in_be32(&pci->pdb_stat));
477 /* clear PCIe reset */
478 clrbits_be32(&pci->pdb_stat, 0x08000000);
479 asm("sync;isync");
480 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
481 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
482 <ssm);
483 udelay(1000);
484 debug("....PCIe link error. "
485 "LTSSM=0x%02x.\n", ltssm);
486 }
487 enabled = ltssm >= PCI_LTSSM_L0;
488
489 /* we need to re-write the bar0 since a reset will
490 * clear it
491 */
492 pci_hose_write_config_dword(hose, dev,
493 PCI_BASE_ADDRESS_0, pcicsrbar);
494 }
495 #endif
496 }
497
498 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
499 if (enabled == 0) {
500 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
501 temp32 = in_be32(&srds_regs->srdspccr0);
502
503 if ((temp32 >> 28) == 3) {
504 int i;
505
506 out_be32(&srds_regs->srdspccr0, 2 << 28);
507 setbits_be32(&pci->pdb_stat, 0x08000000);
508 in_be32(&pci->pdb_stat);
509 udelay(100);
510 clrbits_be32(&pci->pdb_stat, 0x08000000);
511 asm("sync;isync");
512 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
513 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
514 udelay(1000);
515 }
516 enabled = ltssm >= PCI_LTSSM_L0;
517 }
518 }
519 #endif
520 if (!enabled) {
521 /* Let the user know there's no PCIe link for root
522 * complex. for endpoint, the link may not setup, so
523 * print undetermined.
524 */
525 if (fsl_is_pci_agent(hose))
526 printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
527 else
528 printf("no link, regs @ 0x%lx\n", pci_info->regs);
529 hose->last_busno = hose->first_busno;
530 return;
531 }
532
533 out_be32(&pci->pme_msg_det, 0xffffffff);
534 out_be32(&pci->pme_msg_int_en, 0xffffffff);
535
536 /* Print the negotiated PCIe link width */
537 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
538 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
539 (temp16 & 0xf), pci_info->regs);
540
541 hose->current_busno++; /* Start scan with secondary */
542 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
543 }
544
545 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
546 /* The Read-Only Write Enable bit defaults to 1 instead of 0.
547 * Set to 0 to protect the read-only registers.
548 */
549 clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
550 #endif
551
552 /* Use generic setup_device to initialize standard pci regs,
553 * but do not allocate any windows since any BAR found (such
554 * as PCSRBAR) is not in this cpu's memory space.
555 */
556 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
557 hose->pci_prefetch, hose->pci_io);
558
559 if (inbound) {
560 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
561 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
562 temp16 | PCI_COMMAND_MEMORY);
563 }
564
565 #ifndef CONFIG_PCI_NOSCAN
566 if (!fsl_is_pci_agent(hose)) {
567 debug(" Scanning PCI bus %02x\n",
568 hose->current_busno);
569 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
570 } else {
571 debug(" Not scanning PCI bus %02x. PI=%x\n",
572 hose->current_busno, temp8);
573 hose->last_busno = hose->current_busno;
574 }
575
576 /* if we are PCIe - update limit regs and subordinate busno
577 * for the virtual P2P bridge
578 */
579 if (pcie_cap == PCI_CAP_ID_EXP) {
580 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
581 }
582 #else
583 hose->last_busno = hose->current_busno;
584 #endif
585
586 /* Clear all error indications */
587 if (pcie_cap == PCI_CAP_ID_EXP)
588 out_be32(&pci->pme_msg_det, 0xffffffff);
589 out_be32(&pci->pedr, 0xffffffff);
590
591 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
592 if (temp16) {
593 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
594 }
595
596 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
597 if (temp16) {
598 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
599 }
600 }
601
fsl_is_pci_agent(struct pci_controller * hose)602 int fsl_is_pci_agent(struct pci_controller *hose)
603 {
604 int pcie_cap_pos;
605 u8 pcie_cap;
606 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
607
608 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
609 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
610 if (pcie_cap == PCI_CAP_ID_EXP) {
611 u8 header_type;
612
613 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
614 &header_type);
615 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
616 } else {
617 u8 prog_if;
618
619 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
620 /* Programming Interface (PCI_CLASS_PROG)
621 * 0 == pci host or pcie root-complex,
622 * 1 == pci agent or pcie end-point
623 */
624 return (prog_if == FSL_PROG_IF_AGENT);
625 }
626 }
627
fsl_pci_init_port(struct fsl_pci_info * pci_info,struct pci_controller * hose,int busno)628 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
629 struct pci_controller *hose, int busno)
630 {
631 volatile ccsr_fsl_pci_t *pci;
632 struct pci_region *r;
633 pci_dev_t dev = PCI_BDF(busno,0,0);
634 int pcie_cap_pos;
635 u8 pcie_cap;
636
637 pci = (ccsr_fsl_pci_t *) pci_info->regs;
638
639 /* on non-PCIe controllers we don't have pme_msg_det so this code
640 * should do nothing since the read will return 0
641 */
642 if (in_be32(&pci->pme_msg_det)) {
643 out_be32(&pci->pme_msg_det, 0xffffffff);
644 debug (" with errors. Clearing. Now 0x%08x",
645 pci->pme_msg_det);
646 }
647
648 r = hose->regions + hose->region_count;
649
650 /* outbound memory */
651 pci_set_region(r++,
652 pci_info->mem_bus,
653 pci_info->mem_phys,
654 pci_info->mem_size,
655 PCI_REGION_MEM);
656
657 /* outbound io */
658 pci_set_region(r++,
659 pci_info->io_bus,
660 pci_info->io_phys,
661 pci_info->io_size,
662 PCI_REGION_IO);
663
664 hose->region_count = r - hose->regions;
665 hose->first_busno = busno;
666
667 fsl_pci_init(hose, pci_info);
668
669 if (fsl_is_pci_agent(hose)) {
670 fsl_pci_config_unlock(hose);
671 hose->last_busno = hose->first_busno;
672 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
673 } else {
674 /* boot from PCIE --master releases slave's core 0 */
675 char *s = env_get("bootmaster");
676 char pcie[6];
677 sprintf(pcie, "PCIE%d", pci_info->pci_num);
678
679 if (s && (strcmp(s, pcie) == 0))
680 fsl_pcie_boot_master_release_slave(pci_info->pci_num);
681 #endif
682 }
683
684 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
685 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
686 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
687 "e" : "", pci_info->pci_num,
688 hose->first_busno, hose->last_busno);
689 return(hose->last_busno + 1);
690 }
691
692 /* Enable inbound PCI config cycles for agent/endpoint interface */
fsl_pci_config_unlock(struct pci_controller * hose)693 void fsl_pci_config_unlock(struct pci_controller *hose)
694 {
695 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
696 int pcie_cap_pos;
697 u8 pcie_cap;
698 u16 pbfr;
699
700 if (!fsl_is_pci_agent(hose))
701 return;
702
703 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
704 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
705 if (pcie_cap != 0x0) {
706 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
707 u32 block_rev = in_be32(&pci->block_rev1);
708 /* PCIe - set CFG_READY bit of Configuration Ready Register */
709 if (block_rev >= PEX_IP_BLK_REV_3_0)
710 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
711 else
712 pci_hose_write_config_byte(hose, dev,
713 FSL_PCIE_CFG_RDY, 0x1);
714 } else {
715 /* PCI - clear ACL bit of PBFR */
716 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
717 pbfr &= ~0x20;
718 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
719 }
720 }
721
722 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
723 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
fsl_configure_pcie(struct fsl_pci_info * info,struct pci_controller * hose,const char * connected,int busno)724 int fsl_configure_pcie(struct fsl_pci_info *info,
725 struct pci_controller *hose,
726 const char *connected, int busno)
727 {
728 int is_endpoint;
729
730 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
731 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
732
733 is_endpoint = fsl_setup_hose(hose, info->regs);
734 printf("PCIe%u: %s", info->pci_num,
735 is_endpoint ? "Endpoint" : "Root Complex");
736 if (connected)
737 printf(" of %s", connected);
738 puts(", ");
739
740 return fsl_pci_init_port(info, hose, busno);
741 }
742
743 #if defined(CONFIG_FSL_CORENET)
744 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
745 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
746 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
747 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
748 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
749 #else
750 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
751 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
752 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
753 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
754 #endif
755 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
756 #elif defined(CONFIG_MPC85xx)
757 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
758 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
759 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
760 #define _DEVDISR_PCIE4 0
761 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
762 #elif defined(CONFIG_MPC86xx)
763 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
764 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
765 #define _DEVDISR_PCIE3 0
766 #define _DEVDISR_PCIE4 0
767 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
768 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
769 #else
770 #error "No defines for DEVDISR_PCIE"
771 #endif
772
773 /* Implement a dummy function for those platforms w/o SERDES */
__board_serdes_name(enum srds_prtcl device)774 static const char *__board_serdes_name(enum srds_prtcl device)
775 {
776 switch (device) {
777 #ifdef CONFIG_SYS_PCIE1_NAME
778 case PCIE1:
779 return CONFIG_SYS_PCIE1_NAME;
780 #endif
781 #ifdef CONFIG_SYS_PCIE2_NAME
782 case PCIE2:
783 return CONFIG_SYS_PCIE2_NAME;
784 #endif
785 #ifdef CONFIG_SYS_PCIE3_NAME
786 case PCIE3:
787 return CONFIG_SYS_PCIE3_NAME;
788 #endif
789 #ifdef CONFIG_SYS_PCIE4_NAME
790 case PCIE4:
791 return CONFIG_SYS_PCIE4_NAME;
792 #endif
793 default:
794 return NULL;
795 }
796
797 return NULL;
798 }
799
800 __attribute__((weak, alias("__board_serdes_name"))) const char *
801 board_serdes_name(enum srds_prtcl device);
802
803 static u32 devdisr_mask[] = {
804 _DEVDISR_PCIE1,
805 _DEVDISR_PCIE2,
806 _DEVDISR_PCIE3,
807 _DEVDISR_PCIE4,
808 };
809
fsl_pcie_init_ctrl(int busno,u32 devdisr,enum srds_prtcl dev,struct fsl_pci_info * pci_info)810 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
811 struct fsl_pci_info *pci_info)
812 {
813 struct pci_controller *hose;
814 int num = dev - PCIE1;
815
816 hose = calloc(1, sizeof(struct pci_controller));
817 if (!hose)
818 return busno;
819
820 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
821 busno = fsl_configure_pcie(pci_info, hose,
822 board_serdes_name(dev), busno);
823 } else {
824 printf("PCIe%d: disabled\n", num + 1);
825 }
826
827 return busno;
828 }
829
fsl_pcie_init_board(int busno)830 int fsl_pcie_init_board(int busno)
831 {
832 struct fsl_pci_info pci_info;
833 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
834 u32 devdisr;
835 u32 *addr;
836
837 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
838 addr = &gur->devdisr3;
839 #else
840 addr = &gur->devdisr;
841 #endif
842 devdisr = in_be32(addr);
843
844 #ifdef CONFIG_PCIE1
845 SET_STD_PCIE_INFO(pci_info, 1);
846 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
847 #else
848 setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
849 #endif
850
851 #ifdef CONFIG_PCIE2
852 SET_STD_PCIE_INFO(pci_info, 2);
853 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
854 #else
855 setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
856 #endif
857
858 #ifdef CONFIG_PCIE3
859 SET_STD_PCIE_INFO(pci_info, 3);
860 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
861 #else
862 setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
863 #endif
864
865 #ifdef CONFIG_PCIE4
866 SET_STD_PCIE_INFO(pci_info, 4);
867 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
868 #else
869 setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
870 #endif
871
872 return busno;
873 }
874 #else
fsl_pcie_init_ctrl(int busno,u32 devdisr,enum srds_prtcl dev,struct fsl_pci_info * pci_info)875 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
876 struct fsl_pci_info *pci_info)
877 {
878 return busno;
879 }
880
fsl_pcie_init_board(int busno)881 int fsl_pcie_init_board(int busno)
882 {
883 return busno;
884 }
885 #endif
886
887 #ifdef CONFIG_OF_BOARD_SETUP
888 #include <linux/libfdt.h>
889 #include <fdt_support.h>
890
ft_fsl_pci_setup(void * blob,const char * pci_compat,unsigned long ctrl_addr)891 void ft_fsl_pci_setup(void *blob, const char *pci_compat,
892 unsigned long ctrl_addr)
893 {
894 int off;
895 u32 bus_range[2];
896 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
897 struct pci_controller *hose;
898
899 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
900
901 /* convert ctrl_addr to true physical address */
902 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
903 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
904
905 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
906
907 if (off < 0)
908 return;
909
910 /* We assume a cfg_addr not being set means we didn't setup the controller */
911 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
912 fdt_del_node(blob, off);
913 } else {
914 bus_range[0] = 0;
915 bus_range[1] = hose->last_busno - hose->first_busno;
916 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
917 fdt_pci_dma_ranges(blob, off, hose);
918 }
919 }
920 #endif
921