1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <serial.h>
11 #include <watchdog.h>
12 #include <asm/io.h>
13 #include <asm/arch/stm32.h>
14 #include "serial_stm32.h"
15
_stm32_serial_setbrg(fdt_addr_t base,struct stm32_uart_info * uart_info,u32 clock_rate,int baudrate)16 static void _stm32_serial_setbrg(fdt_addr_t base,
17 struct stm32_uart_info *uart_info,
18 u32 clock_rate,
19 int baudrate)
20 {
21 bool stm32f4 = uart_info->stm32f4;
22 u32 int_div, mantissa, fraction, oversampling;
23
24 int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
25
26 if (int_div < 16) {
27 oversampling = 8;
28 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
29 } else {
30 oversampling = 16;
31 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
32 }
33
34 mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
35 fraction = int_div % oversampling;
36
37 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
38 }
39
stm32_serial_setbrg(struct udevice * dev,int baudrate)40 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
41 {
42 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
43
44 _stm32_serial_setbrg(plat->base, plat->uart_info,
45 plat->clock_rate, baudrate);
46
47 return 0;
48 }
49
stm32_serial_setparity(struct udevice * dev,enum serial_par parity)50 static int stm32_serial_setparity(struct udevice *dev, enum serial_par parity)
51 {
52 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
53 bool stm32f4 = plat->uart_info->stm32f4;
54 u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
55 u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
56 u32 config = 0;
57
58 if (stm32f4)
59 return -EINVAL; /* not supported in driver*/
60
61 clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
62 /* update usart configuration (uart need to be disable)
63 * PCE: parity check control
64 * PS : '0' : Even / '1' : Odd
65 * M[1:0] = '00' : 8 Data bits
66 * M[1:0] = '01' : 9 Data bits with parity
67 */
68 switch (parity) {
69 default:
70 case SERIAL_PAR_NONE:
71 config = 0;
72 break;
73 case SERIAL_PAR_ODD:
74 config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
75 break;
76 case SERIAL_PAR_EVEN:
77 config = USART_CR1_PCE | USART_CR1_M0;
78 break;
79 }
80 clrsetbits_le32(cr1,
81 USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
82 USART_CR1_M0,
83 config);
84 setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
85
86 return 0;
87 }
88
stm32_serial_getc(struct udevice * dev)89 static int stm32_serial_getc(struct udevice *dev)
90 {
91 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
92 bool stm32f4 = plat->uart_info->stm32f4;
93 fdt_addr_t base = plat->base;
94 u32 isr = readl(base + ISR_OFFSET(stm32f4));
95
96 if ((isr & USART_ISR_RXNE) == 0)
97 return -EAGAIN;
98
99 if (isr & (USART_ISR_PE | USART_ISR_ORE)) {
100 if (!stm32f4)
101 setbits_le32(base + ICR_OFFSET,
102 USART_ICR_PCECF | USART_ICR_ORECF);
103 else
104 readl(base + RDR_OFFSET(stm32f4));
105 return -EIO;
106 }
107
108 return readl(base + RDR_OFFSET(stm32f4));
109 }
110
_stm32_serial_putc(fdt_addr_t base,struct stm32_uart_info * uart_info,const char c)111 static int _stm32_serial_putc(fdt_addr_t base,
112 struct stm32_uart_info *uart_info,
113 const char c)
114 {
115 bool stm32f4 = uart_info->stm32f4;
116
117 if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
118 return -EAGAIN;
119
120 writel(c, base + TDR_OFFSET(stm32f4));
121
122 return 0;
123 }
124
stm32_serial_putc(struct udevice * dev,const char c)125 static int stm32_serial_putc(struct udevice *dev, const char c)
126 {
127 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
128
129 return _stm32_serial_putc(plat->base, plat->uart_info, c);
130 }
131
stm32_serial_pending(struct udevice * dev,bool input)132 static int stm32_serial_pending(struct udevice *dev, bool input)
133 {
134 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
135 bool stm32f4 = plat->uart_info->stm32f4;
136 fdt_addr_t base = plat->base;
137
138 if (input)
139 return readl(base + ISR_OFFSET(stm32f4)) &
140 USART_ISR_RXNE ? 1 : 0;
141 else
142 return readl(base + ISR_OFFSET(stm32f4)) &
143 USART_ISR_TXE ? 0 : 1;
144 }
145
_stm32_serial_init(fdt_addr_t base,struct stm32_uart_info * uart_info)146 static void _stm32_serial_init(fdt_addr_t base,
147 struct stm32_uart_info *uart_info)
148 {
149 bool stm32f4 = uart_info->stm32f4;
150 u8 uart_enable_bit = uart_info->uart_enable_bit;
151
152 /* Disable uart-> enable fifo -> enable uart */
153 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
154 BIT(uart_enable_bit));
155 if (uart_info->has_fifo)
156 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
157 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
158 BIT(uart_enable_bit));
159 }
160
stm32_serial_probe(struct udevice * dev)161 static int stm32_serial_probe(struct udevice *dev)
162 {
163 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
164 struct clk clk;
165 int ret;
166
167 plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
168
169 ret = clk_get_by_index(dev, 0, &clk);
170 if (ret < 0)
171 return ret;
172
173 ret = clk_enable(&clk);
174 if (ret) {
175 dev_err(dev, "failed to enable clock\n");
176 return ret;
177 }
178
179 plat->clock_rate = clk_get_rate(&clk);
180 if (plat->clock_rate < 0) {
181 clk_disable(&clk);
182 return plat->clock_rate;
183 };
184
185 _stm32_serial_init(plat->base, plat->uart_info);
186
187 return 0;
188 }
189
190 static const struct udevice_id stm32_serial_id[] = {
191 { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
192 { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
193 { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
194 {}
195 };
196
stm32_serial_ofdata_to_platdata(struct udevice * dev)197 static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
198 {
199 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
200
201 plat->base = devfdt_get_addr(dev);
202 if (plat->base == FDT_ADDR_T_NONE)
203 return -EINVAL;
204
205 return 0;
206 }
207
208 static const struct dm_serial_ops stm32_serial_ops = {
209 .putc = stm32_serial_putc,
210 .pending = stm32_serial_pending,
211 .getc = stm32_serial_getc,
212 .setbrg = stm32_serial_setbrg,
213 .setparity = stm32_serial_setparity
214 };
215
216 U_BOOT_DRIVER(serial_stm32) = {
217 .name = "serial_stm32",
218 .id = UCLASS_SERIAL,
219 .of_match = of_match_ptr(stm32_serial_id),
220 .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
221 .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
222 .ops = &stm32_serial_ops,
223 .probe = stm32_serial_probe,
224 .flags = DM_FLAG_PRE_RELOC,
225 };
226
227 #ifdef CONFIG_DEBUG_UART_STM32
228 #include <debug_uart.h>
_debug_uart_info(void)229 static inline struct stm32_uart_info *_debug_uart_info(void)
230 {
231 struct stm32_uart_info *uart_info;
232
233 #if defined(CONFIG_STM32F4)
234 uart_info = &stm32f4_info;
235 #elif defined(CONFIG_STM32F7)
236 uart_info = &stm32f7_info;
237 #else
238 uart_info = &stm32h7_info;
239 #endif
240 return uart_info;
241 }
242
_debug_uart_init(void)243 static inline void _debug_uart_init(void)
244 {
245 fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
246 struct stm32_uart_info *uart_info = _debug_uart_info();
247
248 _stm32_serial_init(base, uart_info);
249 _stm32_serial_setbrg(base, uart_info,
250 CONFIG_DEBUG_UART_CLOCK,
251 CONFIG_BAUDRATE);
252 printf("DEBUG done\n");
253 }
254
_debug_uart_putc(int c)255 static inline void _debug_uart_putc(int c)
256 {
257 fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
258 struct stm32_uart_info *uart_info = _debug_uart_info();
259
260 while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
261 WATCHDOG_RESET();
262 }
263
264 DEBUG_UART_FUNCS
265 #endif
266