1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
4 * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
5 */
6
7 #include <common.h>
8
9 #include <malloc.h>
10 #include <spi.h>
11 #include <asm/mpc8xxx_spi.h>
12
13 #define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
14 #define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
15
16 #define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
17 #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
18 #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
19 #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
20
21 #define SPI_TIMEOUT 1000
22
spi_setup_slave(unsigned int bus,unsigned int cs,unsigned int max_hz,unsigned int mode)23 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
24 unsigned int max_hz, unsigned int mode)
25 {
26 struct spi_slave *slave;
27
28 if (!spi_cs_is_valid(bus, cs))
29 return NULL;
30
31 slave = spi_alloc_slave_base(bus, cs);
32 if (!slave)
33 return NULL;
34
35 /*
36 * TODO: Some of the code in spi_init() should probably move
37 * here, or into spi_claim_bus() below.
38 */
39
40 return slave;
41 }
42
spi_free_slave(struct spi_slave * slave)43 void spi_free_slave(struct spi_slave *slave)
44 {
45 free(slave);
46 }
47
spi_init(void)48 void spi_init(void)
49 {
50 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
51
52 /*
53 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
54 * some registers
55 */
56 spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
57 spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
58 (16.67MHz typ.) */
59 spi->event = 0xffffffff; /* Clear all SPI events */
60 spi->mask = 0x00000000; /* Mask all SPI interrupts */
61 spi->com = 0; /* LST bit doesn't do anything, so disregard */
62 }
63
spi_claim_bus(struct spi_slave * slave)64 int spi_claim_bus(struct spi_slave *slave)
65 {
66 return 0;
67 }
68
spi_release_bus(struct spi_slave * slave)69 void spi_release_bus(struct spi_slave *slave)
70 {
71
72 }
73
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)74 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
75 void *din, unsigned long flags)
76 {
77 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
78 unsigned int tmpdout, tmpdin, event;
79 int numBlks = DIV_ROUND_UP(bitlen, 32);
80 int tm, isRead = 0;
81 unsigned char charSize = 32;
82
83 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
84 slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
85
86 if (flags & SPI_XFER_BEGIN)
87 spi_cs_activate(slave);
88
89 spi->event = 0xffffffff; /* Clear all SPI events */
90
91 /* handle data in 32-bit chunks */
92 while (numBlks--) {
93 tmpdout = 0;
94 charSize = (bitlen >= 32 ? 32 : bitlen);
95
96 /* Shift data so it's msb-justified */
97 tmpdout = *(u32 *) dout >> (32 - charSize);
98
99 /* The LEN field of the SPMODE register is set as follows:
100 *
101 * Bit length setting
102 * len <= 4 3
103 * 4 < len <= 16 len - 1
104 * len > 16 0
105 */
106
107 spi->mode &= ~SPI_MODE_EN;
108
109 if (bitlen <= 16) {
110 if (bitlen <= 4)
111 spi->mode = (spi->mode & 0xff0fffff) |
112 (3 << 20);
113 else
114 spi->mode = (spi->mode & 0xff0fffff) |
115 ((bitlen - 1) << 20);
116 } else {
117 spi->mode = (spi->mode & 0xff0fffff);
118 /* Set up the next iteration if sending > 32 bits */
119 bitlen -= 32;
120 dout += 4;
121 }
122
123 spi->mode |= SPI_MODE_EN;
124
125 spi->tx = tmpdout; /* Write the data out */
126 debug("*** spi_xfer: ... %08x written\n", tmpdout);
127
128 /*
129 * Wait for SPI transmit to get out
130 * or time out (1 second = 1000 ms)
131 * The NE event must be read and cleared first
132 */
133 for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
134 event = spi->event;
135 if (event & SPI_EV_NE) {
136 tmpdin = spi->rx;
137 spi->event |= SPI_EV_NE;
138 isRead = 1;
139
140 *(u32 *) din = (tmpdin << (32 - charSize));
141 if (charSize == 32) {
142 /* Advance output buffer by 32 bits */
143 din += 4;
144 }
145 }
146 /*
147 * Only bail when we've had both NE and NF events.
148 * This will cause timeouts on RO devices, so maybe
149 * in the future put an arbitrary delay after writing
150 * the device. Arbitrary delays suck, though...
151 */
152 if (isRead && (event & SPI_EV_NF))
153 break;
154 }
155 if (tm >= SPI_TIMEOUT)
156 puts("*** spi_xfer: Time out during SPI transfer");
157
158 debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
159 }
160
161 if (flags & SPI_XFER_END)
162 spi_cs_deactivate(slave);
163
164 return 0;
165 }
166