1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <usb.h>
11 #include <malloc.h>
12 #include <memalign.h>
13 #include <phys2bus.h>
14 #include <usbroothubdes.h>
15 #include <wait_bit.h>
16 #include <asm/io.h>
17 #include <power/regulator.h>
18
19 #include "dwc2.h"
20
21 /* Use only HC channel 0. */
22 #define DWC2_HC_CHANNEL 0
23
24 #define DWC2_STATUS_BUF_SIZE 64
25 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
26
27 #define MAX_DEVICE 16
28 #define MAX_ENDPOINT 16
29
30 struct dwc2_priv {
31 #ifdef CONFIG_DM_USB
32 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
33 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
34 #ifdef CONFIG_DM_REGULATOR
35 struct udevice *vbus_supply;
36 #endif
37 #else
38 uint8_t *aligned_buffer;
39 uint8_t *status_buffer;
40 #endif
41 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
42 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
43 struct dwc2_core_regs *regs;
44 int root_hub_devnum;
45 bool ext_vbus;
46 /*
47 * The hnp/srp capability must be disabled if the platform
48 * does't support hnp/srp. Otherwise the force mode can't work.
49 */
50 bool hnp_srp_disable;
51 bool oc_disable;
52 };
53
54 #ifndef CONFIG_DM_USB
55 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
56 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
57 ARCH_DMA_MINALIGN);
58 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
59 ARCH_DMA_MINALIGN);
60
61 static struct dwc2_priv local;
62 #endif
63
64 /*
65 * DWC2 IP interface
66 */
67
68 /*
69 * Initializes the FSLSPClkSel field of the HCFG register
70 * depending on the PHY type.
71 */
init_fslspclksel(struct dwc2_core_regs * regs)72 static void init_fslspclksel(struct dwc2_core_regs *regs)
73 {
74 uint32_t phyclk;
75
76 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
77 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
78 #else
79 /* High speed PHY running at full speed or high speed */
80 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
81 #endif
82
83 #ifdef CONFIG_DWC2_ULPI_FS_LS
84 uint32_t hwcfg2 = readl(®s->ghwcfg2);
85 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
86 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
87 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
88 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
89
90 if (hval == 2 && fval == 1)
91 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
92 #endif
93
94 clrsetbits_le32(®s->host_regs.hcfg,
95 DWC2_HCFG_FSLSPCLKSEL_MASK,
96 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
97 }
98
99 /*
100 * Flush a Tx FIFO.
101 *
102 * @param regs Programming view of DWC_otg controller.
103 * @param num Tx FIFO to flush.
104 */
dwc_otg_flush_tx_fifo(struct dwc2_core_regs * regs,const int num)105 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
106 {
107 int ret;
108
109 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
110 ®s->grstctl);
111 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
112 false, 1000, false);
113 if (ret)
114 dev_info(dev, "%s: Timeout!\n", __func__);
115
116 /* Wait for 3 PHY Clocks */
117 udelay(1);
118 }
119
120 /*
121 * Flush Rx FIFO.
122 *
123 * @param regs Programming view of DWC_otg controller.
124 */
dwc_otg_flush_rx_fifo(struct dwc2_core_regs * regs)125 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
126 {
127 int ret;
128
129 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
130 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
131 false, 1000, false);
132 if (ret)
133 dev_info(dev, "%s: Timeout!\n", __func__);
134
135 /* Wait for 3 PHY Clocks */
136 udelay(1);
137 }
138
139 /*
140 * Do core a soft reset of the core. Be careful with this because it
141 * resets all the internal state machines of the core.
142 */
dwc_otg_core_reset(struct dwc2_core_regs * regs)143 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
144 {
145 int ret;
146
147 /* Wait for AHB master IDLE state. */
148 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
149 true, 1000, false);
150 if (ret)
151 dev_info(dev, "%s: Timeout!\n", __func__);
152
153 /* Core Soft Reset */
154 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
155 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
156 false, 1000, false);
157 if (ret)
158 dev_info(dev, "%s: Timeout!\n", __func__);
159
160 /*
161 * Wait for core to come out of reset.
162 * NOTE: This long sleep is _very_ important, otherwise the core will
163 * not stay in host mode after a connector ID change!
164 */
165 mdelay(100);
166 }
167
168 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
dwc_vbus_supply_init(struct udevice * dev)169 static int dwc_vbus_supply_init(struct udevice *dev)
170 {
171 struct dwc2_priv *priv = dev_get_priv(dev);
172 int ret;
173
174 ret = device_get_supply_regulator(dev, "vbus-supply",
175 &priv->vbus_supply);
176 if (ret) {
177 debug("%s: No vbus supply\n", dev->name);
178 return 0;
179 }
180
181 ret = regulator_set_enable(priv->vbus_supply, true);
182 if (ret) {
183 dev_err(dev, "Error enabling vbus supply\n");
184 return ret;
185 }
186
187 return 0;
188 }
189
dwc_vbus_supply_exit(struct udevice * dev)190 static int dwc_vbus_supply_exit(struct udevice *dev)
191 {
192 struct dwc2_priv *priv = dev_get_priv(dev);
193 int ret;
194
195 if (priv->vbus_supply) {
196 ret = regulator_set_enable(priv->vbus_supply, false);
197 if (ret) {
198 dev_err(dev, "Error disabling vbus supply\n");
199 return ret;
200 }
201 }
202
203 return 0;
204 }
205 #else
dwc_vbus_supply_init(struct udevice * dev)206 static int dwc_vbus_supply_init(struct udevice *dev)
207 {
208 return 0;
209 }
210
211 #if defined(CONFIG_DM_USB)
dwc_vbus_supply_exit(struct udevice * dev)212 static int dwc_vbus_supply_exit(struct udevice *dev)
213 {
214 return 0;
215 }
216 #endif
217 #endif
218
219 /*
220 * This function initializes the DWC_otg controller registers for
221 * host mode.
222 *
223 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
224 * request queues. Host channels are reset to ensure that they are ready for
225 * performing transfers.
226 *
227 * @param dev USB Device (NULL if driver model is not being used)
228 * @param regs Programming view of DWC_otg controller
229 *
230 */
dwc_otg_core_host_init(struct udevice * dev,struct dwc2_core_regs * regs)231 static void dwc_otg_core_host_init(struct udevice *dev,
232 struct dwc2_core_regs *regs)
233 {
234 uint32_t nptxfifosize = 0;
235 uint32_t ptxfifosize = 0;
236 uint32_t hprt0 = 0;
237 int i, ret, num_channels;
238
239 /* Restart the Phy Clock */
240 writel(0, ®s->pcgcctl);
241
242 /* Initialize Host Configuration Register */
243 init_fslspclksel(regs);
244 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
245 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
246 #endif
247
248 /* Configure data FIFO sizes */
249 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
250 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
251 /* Rx FIFO */
252 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
253
254 /* Non-periodic Tx FIFO */
255 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
256 DWC2_FIFOSIZE_DEPTH_OFFSET;
257 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
258 DWC2_FIFOSIZE_STARTADDR_OFFSET;
259 writel(nptxfifosize, ®s->gnptxfsiz);
260
261 /* Periodic Tx FIFO */
262 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
263 DWC2_FIFOSIZE_DEPTH_OFFSET;
264 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
265 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
266 DWC2_FIFOSIZE_STARTADDR_OFFSET;
267 writel(ptxfifosize, ®s->hptxfsiz);
268 }
269 #endif
270
271 /* Clear Host Set HNP Enable in the OTG Control Register */
272 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
273
274 /* Make sure the FIFOs are flushed. */
275 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
276 dwc_otg_flush_rx_fifo(regs);
277
278 /* Flush out any leftover queued requests. */
279 num_channels = readl(®s->ghwcfg2);
280 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
281 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
282 num_channels += 1;
283
284 for (i = 0; i < num_channels; i++)
285 clrsetbits_le32(®s->hc_regs[i].hcchar,
286 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
287 DWC2_HCCHAR_CHDIS);
288
289 /* Halt all channels to put them into a known state. */
290 for (i = 0; i < num_channels; i++) {
291 clrsetbits_le32(®s->hc_regs[i].hcchar,
292 DWC2_HCCHAR_EPDIR,
293 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
294 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
295 DWC2_HCCHAR_CHEN, false, 1000, false);
296 if (ret)
297 dev_info("%s: Timeout!\n", __func__);
298 }
299
300 /* Turn on the vbus power. */
301 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
302 hprt0 = readl(®s->hprt0);
303 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
304 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
305 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
306 hprt0 |= DWC2_HPRT0_PRTPWR;
307 writel(hprt0, ®s->hprt0);
308 }
309 }
310
311 if (dev)
312 dwc_vbus_supply_init(dev);
313 }
314
315 /*
316 * This function initializes the DWC_otg controller registers and
317 * prepares the core for device mode or host mode operation.
318 *
319 * @param regs Programming view of the DWC_otg controller
320 */
dwc_otg_core_init(struct dwc2_priv * priv)321 static void dwc_otg_core_init(struct dwc2_priv *priv)
322 {
323 struct dwc2_core_regs *regs = priv->regs;
324 uint32_t ahbcfg = 0;
325 uint32_t usbcfg = 0;
326 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
327
328 /* Common Initialization */
329 usbcfg = readl(®s->gusbcfg);
330
331 /* Program the ULPI External VBUS bit if needed */
332 if (priv->ext_vbus) {
333 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
334 if (!priv->oc_disable) {
335 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
336 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
337 }
338 } else {
339 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
340 }
341
342 /* Set external TS Dline pulsing */
343 #ifdef CONFIG_DWC2_TS_DLINE
344 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
345 #else
346 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
347 #endif
348 writel(usbcfg, ®s->gusbcfg);
349
350 /* Reset the Controller */
351 dwc_otg_core_reset(regs);
352
353 /*
354 * This programming sequence needs to happen in FS mode before
355 * any other programming occurs
356 */
357 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
358 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
359 /* If FS mode with FS PHY */
360 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
361
362 /* Reset after a PHY select */
363 dwc_otg_core_reset(regs);
364
365 /*
366 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
367 * Also do this on HNP Dev/Host mode switches (done in dev_init
368 * and host_init).
369 */
370 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
371 init_fslspclksel(regs);
372
373 #ifdef CONFIG_DWC2_I2C_ENABLE
374 /* Program GUSBCFG.OtgUtmifsSel to I2C */
375 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
376
377 /* Program GI2CCTL.I2CEn */
378 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
379 DWC2_GI2CCTL_I2CDEVADDR_MASK,
380 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
381 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
382 #endif
383
384 #else
385 /* High speed PHY. */
386
387 /*
388 * HS PHY parameters. These parameters are preserved during
389 * soft reset so only program the first time. Do a soft reset
390 * immediately after setting phyif.
391 */
392 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
393 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
394
395 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
396 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
397 usbcfg |= DWC2_GUSBCFG_DDRSEL;
398 #else
399 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
400 #endif
401 } else { /* UTMI+ interface */
402 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
403 usbcfg |= DWC2_GUSBCFG_PHYIF;
404 #endif
405 }
406
407 writel(usbcfg, ®s->gusbcfg);
408
409 /* Reset after setting the PHY parameters */
410 dwc_otg_core_reset(regs);
411 #endif
412
413 usbcfg = readl(®s->gusbcfg);
414 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
415 #ifdef CONFIG_DWC2_ULPI_FS_LS
416 uint32_t hwcfg2 = readl(®s->ghwcfg2);
417 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
418 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
419 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
420 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
421 if (hval == 2 && fval == 1) {
422 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
423 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
424 }
425 #endif
426 if (priv->hnp_srp_disable)
427 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
428
429 writel(usbcfg, ®s->gusbcfg);
430
431 /* Program the GAHBCFG Register. */
432 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
433 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
434 break;
435 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
436 while (brst_sz > 1) {
437 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
438 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
439 brst_sz >>= 1;
440 }
441
442 #ifdef CONFIG_DWC2_DMA_ENABLE
443 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
444 #endif
445 break;
446
447 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
448 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
449 #ifdef CONFIG_DWC2_DMA_ENABLE
450 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
451 #endif
452 break;
453 }
454
455 writel(ahbcfg, ®s->gahbcfg);
456
457 /* Program the capabilities in GUSBCFG Register */
458 usbcfg = 0;
459
460 if (!priv->hnp_srp_disable)
461 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
462 #ifdef CONFIG_DWC2_IC_USB_CAP
463 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
464 #endif
465
466 setbits_le32(®s->gusbcfg, usbcfg);
467 }
468
469 /*
470 * Prepares a host channel for transferring packets to/from a specific
471 * endpoint. The HCCHARn register is set up with the characteristics specified
472 * in _hc. Host channel interrupts that may need to be serviced while this
473 * transfer is in progress are enabled.
474 *
475 * @param regs Programming view of DWC_otg controller
476 * @param hc Information needed to initialize the host channel
477 */
dwc_otg_hc_init(struct dwc2_core_regs * regs,uint8_t hc_num,struct usb_device * dev,uint8_t dev_addr,uint8_t ep_num,uint8_t ep_is_in,uint8_t ep_type,uint16_t max_packet)478 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
479 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
480 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
481 {
482 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
483 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
484 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
485 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
486 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
487 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
488
489 if (dev->speed == USB_SPEED_LOW)
490 hcchar |= DWC2_HCCHAR_LSPDDEV;
491
492 /*
493 * Program the HCCHARn register with the endpoint characteristics
494 * for the current transfer.
495 */
496 writel(hcchar, &hc_regs->hcchar);
497
498 /* Program the HCSPLIT register, default to no SPLIT */
499 writel(0, &hc_regs->hcsplt);
500 }
501
dwc_otg_hc_init_split(struct dwc2_hc_regs * hc_regs,uint8_t hub_devnum,uint8_t hub_port)502 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
503 uint8_t hub_devnum, uint8_t hub_port)
504 {
505 uint32_t hcsplt = 0;
506
507 hcsplt = DWC2_HCSPLT_SPLTENA;
508 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
509 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
510
511 /* Program the HCSPLIT register for SPLITs */
512 writel(hcsplt, &hc_regs->hcsplt);
513 }
514
515 /*
516 * DWC2 to USB API interface
517 */
518 /* Direction: In ; Request: Status */
dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs * regs,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)519 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
520 struct usb_device *dev, void *buffer,
521 int txlen, struct devrequest *cmd)
522 {
523 uint32_t hprt0 = 0;
524 uint32_t port_status = 0;
525 uint32_t port_change = 0;
526 int len = 0;
527 int stat = 0;
528
529 switch (cmd->requesttype & ~USB_DIR_IN) {
530 case 0:
531 *(uint16_t *)buffer = cpu_to_le16(1);
532 len = 2;
533 break;
534 case USB_RECIP_INTERFACE:
535 case USB_RECIP_ENDPOINT:
536 *(uint16_t *)buffer = cpu_to_le16(0);
537 len = 2;
538 break;
539 case USB_TYPE_CLASS:
540 *(uint32_t *)buffer = cpu_to_le32(0);
541 len = 4;
542 break;
543 case USB_RECIP_OTHER | USB_TYPE_CLASS:
544 hprt0 = readl(®s->hprt0);
545 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
546 port_status |= USB_PORT_STAT_CONNECTION;
547 if (hprt0 & DWC2_HPRT0_PRTENA)
548 port_status |= USB_PORT_STAT_ENABLE;
549 if (hprt0 & DWC2_HPRT0_PRTSUSP)
550 port_status |= USB_PORT_STAT_SUSPEND;
551 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
552 port_status |= USB_PORT_STAT_OVERCURRENT;
553 if (hprt0 & DWC2_HPRT0_PRTRST)
554 port_status |= USB_PORT_STAT_RESET;
555 if (hprt0 & DWC2_HPRT0_PRTPWR)
556 port_status |= USB_PORT_STAT_POWER;
557
558 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
559 port_status |= USB_PORT_STAT_LOW_SPEED;
560 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
561 DWC2_HPRT0_PRTSPD_HIGH)
562 port_status |= USB_PORT_STAT_HIGH_SPEED;
563
564 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
565 port_change |= USB_PORT_STAT_C_ENABLE;
566 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
567 port_change |= USB_PORT_STAT_C_CONNECTION;
568 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
569 port_change |= USB_PORT_STAT_C_OVERCURRENT;
570
571 *(uint32_t *)buffer = cpu_to_le32(port_status |
572 (port_change << 16));
573 len = 4;
574 break;
575 default:
576 puts("unsupported root hub command\n");
577 stat = USB_ST_STALLED;
578 }
579
580 dev->act_len = min(len, txlen);
581 dev->status = stat;
582
583 return stat;
584 }
585
586 /* Direction: In ; Request: Descriptor */
dwc_otg_submit_rh_msg_in_descriptor(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)587 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
588 void *buffer, int txlen,
589 struct devrequest *cmd)
590 {
591 unsigned char data[32];
592 uint32_t dsc;
593 int len = 0;
594 int stat = 0;
595 uint16_t wValue = cpu_to_le16(cmd->value);
596 uint16_t wLength = cpu_to_le16(cmd->length);
597
598 switch (cmd->requesttype & ~USB_DIR_IN) {
599 case 0:
600 switch (wValue & 0xff00) {
601 case 0x0100: /* device descriptor */
602 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
603 memcpy(buffer, root_hub_dev_des, len);
604 break;
605 case 0x0200: /* configuration descriptor */
606 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
607 memcpy(buffer, root_hub_config_des, len);
608 break;
609 case 0x0300: /* string descriptors */
610 switch (wValue & 0xff) {
611 case 0x00:
612 len = min3(txlen, (int)sizeof(root_hub_str_index0),
613 (int)wLength);
614 memcpy(buffer, root_hub_str_index0, len);
615 break;
616 case 0x01:
617 len = min3(txlen, (int)sizeof(root_hub_str_index1),
618 (int)wLength);
619 memcpy(buffer, root_hub_str_index1, len);
620 break;
621 }
622 break;
623 default:
624 stat = USB_ST_STALLED;
625 }
626 break;
627
628 case USB_TYPE_CLASS:
629 /* Root port config, set 1 port and nothing else. */
630 dsc = 0x00000001;
631
632 data[0] = 9; /* min length; */
633 data[1] = 0x29;
634 data[2] = dsc & RH_A_NDP;
635 data[3] = 0;
636 if (dsc & RH_A_PSM)
637 data[3] |= 0x1;
638 if (dsc & RH_A_NOCP)
639 data[3] |= 0x10;
640 else if (dsc & RH_A_OCPM)
641 data[3] |= 0x8;
642
643 /* corresponds to data[4-7] */
644 data[5] = (dsc & RH_A_POTPGT) >> 24;
645 data[7] = dsc & RH_B_DR;
646 if (data[2] < 7) {
647 data[8] = 0xff;
648 } else {
649 data[0] += 2;
650 data[8] = (dsc & RH_B_DR) >> 8;
651 data[9] = 0xff;
652 data[10] = data[9];
653 }
654
655 len = min3(txlen, (int)data[0], (int)wLength);
656 memcpy(buffer, data, len);
657 break;
658 default:
659 puts("unsupported root hub command\n");
660 stat = USB_ST_STALLED;
661 }
662
663 dev->act_len = min(len, txlen);
664 dev->status = stat;
665
666 return stat;
667 }
668
669 /* Direction: In ; Request: Configuration */
dwc_otg_submit_rh_msg_in_configuration(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)670 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
671 void *buffer, int txlen,
672 struct devrequest *cmd)
673 {
674 int len = 0;
675 int stat = 0;
676
677 switch (cmd->requesttype & ~USB_DIR_IN) {
678 case 0:
679 *(uint8_t *)buffer = 0x01;
680 len = 1;
681 break;
682 default:
683 puts("unsupported root hub command\n");
684 stat = USB_ST_STALLED;
685 }
686
687 dev->act_len = min(len, txlen);
688 dev->status = stat;
689
690 return stat;
691 }
692
693 /* Direction: In */
dwc_otg_submit_rh_msg_in(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)694 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
695 struct usb_device *dev, void *buffer,
696 int txlen, struct devrequest *cmd)
697 {
698 switch (cmd->request) {
699 case USB_REQ_GET_STATUS:
700 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
701 txlen, cmd);
702 case USB_REQ_GET_DESCRIPTOR:
703 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
704 txlen, cmd);
705 case USB_REQ_GET_CONFIGURATION:
706 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
707 txlen, cmd);
708 default:
709 puts("unsupported root hub command\n");
710 return USB_ST_STALLED;
711 }
712 }
713
714 /* Direction: Out */
dwc_otg_submit_rh_msg_out(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)715 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
716 struct usb_device *dev,
717 void *buffer, int txlen,
718 struct devrequest *cmd)
719 {
720 struct dwc2_core_regs *regs = priv->regs;
721 int len = 0;
722 int stat = 0;
723 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
724 uint16_t wValue = cpu_to_le16(cmd->value);
725
726 switch (bmrtype_breq & ~USB_DIR_IN) {
727 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
728 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
729 break;
730
731 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
732 switch (wValue) {
733 case USB_PORT_FEAT_C_CONNECTION:
734 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
735 break;
736 }
737 break;
738
739 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
740 switch (wValue) {
741 case USB_PORT_FEAT_SUSPEND:
742 break;
743
744 case USB_PORT_FEAT_RESET:
745 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
746 DWC2_HPRT0_PRTCONNDET |
747 DWC2_HPRT0_PRTENCHNG |
748 DWC2_HPRT0_PRTOVRCURRCHNG,
749 DWC2_HPRT0_PRTRST);
750 mdelay(50);
751 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
752 break;
753
754 case USB_PORT_FEAT_POWER:
755 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
756 DWC2_HPRT0_PRTCONNDET |
757 DWC2_HPRT0_PRTENCHNG |
758 DWC2_HPRT0_PRTOVRCURRCHNG,
759 DWC2_HPRT0_PRTRST);
760 break;
761
762 case USB_PORT_FEAT_ENABLE:
763 break;
764 }
765 break;
766 case (USB_REQ_SET_ADDRESS << 8):
767 priv->root_hub_devnum = wValue;
768 break;
769 case (USB_REQ_SET_CONFIGURATION << 8):
770 break;
771 default:
772 puts("unsupported root hub command\n");
773 stat = USB_ST_STALLED;
774 }
775
776 len = min(len, txlen);
777
778 dev->act_len = len;
779 dev->status = stat;
780
781 return stat;
782 }
783
dwc_otg_submit_rh_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int txlen,struct devrequest * cmd)784 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
785 unsigned long pipe, void *buffer, int txlen,
786 struct devrequest *cmd)
787 {
788 int stat = 0;
789
790 if (usb_pipeint(pipe)) {
791 puts("Root-Hub submit IRQ: NOT implemented\n");
792 return 0;
793 }
794
795 if (cmd->requesttype & USB_DIR_IN)
796 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
797 else
798 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
799
800 mdelay(1);
801
802 return stat;
803 }
804
wait_for_chhltd(struct dwc2_hc_regs * hc_regs,uint32_t * sub,u8 * toggle)805 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
806 {
807 int ret;
808 uint32_t hcint, hctsiz;
809
810 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
811 2000, false);
812 if (ret)
813 return ret;
814
815 hcint = readl(&hc_regs->hcint);
816 hctsiz = readl(&hc_regs->hctsiz);
817 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
818 DWC2_HCTSIZ_XFERSIZE_OFFSET;
819 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
820
821 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
822 *toggle);
823
824 if (hcint & DWC2_HCINT_XFERCOMP)
825 return 0;
826
827 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
828 return -EAGAIN;
829
830 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
831 return -EINVAL;
832 }
833
834 static int dwc2_eptype[] = {
835 DWC2_HCCHAR_EPTYPE_ISOC,
836 DWC2_HCCHAR_EPTYPE_INTR,
837 DWC2_HCCHAR_EPTYPE_CONTROL,
838 DWC2_HCCHAR_EPTYPE_BULK,
839 };
840
transfer_chunk(struct dwc2_hc_regs * hc_regs,void * aligned_buffer,u8 * pid,int in,void * buffer,int num_packets,int xfer_len,int * actual_len,int odd_frame)841 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
842 u8 *pid, int in, void *buffer, int num_packets,
843 int xfer_len, int *actual_len, int odd_frame)
844 {
845 int ret = 0;
846 uint32_t sub;
847
848 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
849 *pid, xfer_len, num_packets);
850
851 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
852 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
853 (*pid << DWC2_HCTSIZ_PID_OFFSET),
854 &hc_regs->hctsiz);
855
856 if (xfer_len) {
857 if (in) {
858 invalidate_dcache_range(
859 (uintptr_t)aligned_buffer,
860 (uintptr_t)aligned_buffer +
861 roundup(xfer_len, ARCH_DMA_MINALIGN));
862 } else {
863 memcpy(aligned_buffer, buffer, xfer_len);
864 flush_dcache_range(
865 (uintptr_t)aligned_buffer,
866 (uintptr_t)aligned_buffer +
867 roundup(xfer_len, ARCH_DMA_MINALIGN));
868 }
869 }
870
871 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
872
873 /* Clear old interrupt conditions for this host channel. */
874 writel(0x3fff, &hc_regs->hcint);
875
876 /* Set host channel enable after all other setup is complete. */
877 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
878 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
879 DWC2_HCCHAR_ODDFRM,
880 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
881 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
882 DWC2_HCCHAR_CHEN);
883
884 ret = wait_for_chhltd(hc_regs, &sub, pid);
885 if (ret < 0)
886 return ret;
887
888 if (in) {
889 xfer_len -= sub;
890
891 invalidate_dcache_range((unsigned long)aligned_buffer,
892 (unsigned long)aligned_buffer +
893 roundup(xfer_len, ARCH_DMA_MINALIGN));
894
895 memcpy(buffer, aligned_buffer, xfer_len);
896 }
897 *actual_len = xfer_len;
898
899 return ret;
900 }
901
chunk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,u8 * pid,int in,void * buffer,int len)902 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
903 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
904 {
905 struct dwc2_core_regs *regs = priv->regs;
906 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
907 struct dwc2_host_regs *host_regs = ®s->host_regs;
908 int devnum = usb_pipedevice(pipe);
909 int ep = usb_pipeendpoint(pipe);
910 int max = usb_maxpacket(dev, pipe);
911 int eptype = dwc2_eptype[usb_pipetype(pipe)];
912 int done = 0;
913 int ret = 0;
914 int do_split = 0;
915 int complete_split = 0;
916 uint32_t xfer_len;
917 uint32_t num_packets;
918 int stop_transfer = 0;
919 uint32_t max_xfer_len;
920 int ssplit_frame_num = 0;
921
922 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
923 in, len);
924
925 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
926 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
927 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
928 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
929 max_xfer_len = DWC2_DATA_BUF_SIZE;
930
931 /* Make sure that max_xfer_len is a multiple of max packet size. */
932 num_packets = max_xfer_len / max;
933 max_xfer_len = num_packets * max;
934
935 /* Initialize channel */
936 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
937 eptype, max);
938
939 /* Check if the target is a FS/LS device behind a HS hub */
940 if (dev->speed != USB_SPEED_HIGH) {
941 uint8_t hub_addr;
942 uint8_t hub_port;
943 uint32_t hprt0 = readl(®s->hprt0);
944 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
945 DWC2_HPRT0_PRTSPD_HIGH) {
946 usb_find_usb2_hub_address_port(dev, &hub_addr,
947 &hub_port);
948 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
949
950 do_split = 1;
951 num_packets = 1;
952 max_xfer_len = max;
953 }
954 }
955
956 do {
957 int actual_len = 0;
958 uint32_t hcint;
959 int odd_frame = 0;
960 xfer_len = len - done;
961
962 if (xfer_len > max_xfer_len)
963 xfer_len = max_xfer_len;
964 else if (xfer_len > max)
965 num_packets = (xfer_len + max - 1) / max;
966 else
967 num_packets = 1;
968
969 if (complete_split)
970 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
971 else if (do_split)
972 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
973
974 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
975 int uframe_num = readl(&host_regs->hfnum);
976 if (!(uframe_num & 0x1))
977 odd_frame = 1;
978 }
979
980 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
981 in, (char *)buffer + done, num_packets,
982 xfer_len, &actual_len, odd_frame);
983
984 hcint = readl(&hc_regs->hcint);
985 if (complete_split) {
986 stop_transfer = 0;
987 if (hcint & DWC2_HCINT_NYET) {
988 ret = 0;
989 int frame_num = DWC2_HFNUM_MAX_FRNUM &
990 readl(&host_regs->hfnum);
991 if (((frame_num - ssplit_frame_num) &
992 DWC2_HFNUM_MAX_FRNUM) > 4)
993 ret = -EAGAIN;
994 } else
995 complete_split = 0;
996 } else if (do_split) {
997 if (hcint & DWC2_HCINT_ACK) {
998 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
999 readl(&host_regs->hfnum);
1000 ret = 0;
1001 complete_split = 1;
1002 }
1003 }
1004
1005 if (ret)
1006 break;
1007
1008 if (actual_len < xfer_len)
1009 stop_transfer = 1;
1010
1011 done += actual_len;
1012
1013 /* Transactions are done when when either all data is transferred or
1014 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1015 * is executed.
1016 */
1017 } while (((done < len) && !stop_transfer) || complete_split);
1018
1019 writel(0, &hc_regs->hcintmsk);
1020 writel(0xFFFFFFFF, &hc_regs->hcint);
1021
1022 dev->status = 0;
1023 dev->act_len = done;
1024
1025 return ret;
1026 }
1027
1028 /* U-Boot USB transmission interface */
_submit_bulk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len)1029 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1030 unsigned long pipe, void *buffer, int len)
1031 {
1032 int devnum = usb_pipedevice(pipe);
1033 int ep = usb_pipeendpoint(pipe);
1034 u8* pid;
1035
1036 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1037 dev->status = 0;
1038 return -EINVAL;
1039 }
1040
1041 if (usb_pipein(pipe))
1042 pid = &priv->in_data_toggle[devnum][ep];
1043 else
1044 pid = &priv->out_data_toggle[devnum][ep];
1045
1046 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1047 }
1048
_submit_control_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1049 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1050 unsigned long pipe, void *buffer, int len,
1051 struct devrequest *setup)
1052 {
1053 int devnum = usb_pipedevice(pipe);
1054 int ret, act_len;
1055 u8 pid;
1056 /* For CONTROL endpoint pid should start with DATA1 */
1057 int status_direction;
1058
1059 if (devnum == priv->root_hub_devnum) {
1060 dev->status = 0;
1061 dev->speed = USB_SPEED_HIGH;
1062 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1063 setup);
1064 }
1065
1066 /* SETUP stage */
1067 pid = DWC2_HC_PID_SETUP;
1068 do {
1069 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1070 } while (ret == -EAGAIN);
1071 if (ret)
1072 return ret;
1073
1074 /* DATA stage */
1075 act_len = 0;
1076 if (buffer) {
1077 pid = DWC2_HC_PID_DATA1;
1078 do {
1079 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1080 buffer, len);
1081 act_len += dev->act_len;
1082 buffer += dev->act_len;
1083 len -= dev->act_len;
1084 } while (ret == -EAGAIN);
1085 if (ret)
1086 return ret;
1087 status_direction = usb_pipeout(pipe);
1088 } else {
1089 /* No-data CONTROL always ends with an IN transaction */
1090 status_direction = 1;
1091 }
1092
1093 /* STATUS stage */
1094 pid = DWC2_HC_PID_DATA1;
1095 do {
1096 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1097 priv->status_buffer, 0);
1098 } while (ret == -EAGAIN);
1099 if (ret)
1100 return ret;
1101
1102 dev->act_len = act_len;
1103
1104 return 0;
1105 }
1106
_submit_int_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval)1107 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1108 unsigned long pipe, void *buffer, int len, int interval)
1109 {
1110 unsigned long timeout;
1111 int ret;
1112
1113 /* FIXME: what is interval? */
1114
1115 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1116 for (;;) {
1117 if (get_timer(0) > timeout) {
1118 dev_err(dev, "Timeout poll on interrupt endpoint\n");
1119 return -ETIMEDOUT;
1120 }
1121 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1122 if (ret != -EAGAIN)
1123 return ret;
1124 }
1125 }
1126
dwc2_init_common(struct udevice * dev,struct dwc2_priv * priv)1127 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1128 {
1129 struct dwc2_core_regs *regs = priv->regs;
1130 uint32_t snpsid;
1131 int i, j;
1132
1133 snpsid = readl(®s->gsnpsid);
1134 dev_info(dev, "Core Release: %x.%03x\n",
1135 snpsid >> 12 & 0xf, snpsid & 0xfff);
1136
1137 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1138 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1139 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1140 snpsid);
1141 return -ENODEV;
1142 }
1143
1144 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1145 priv->ext_vbus = 1;
1146 #else
1147 priv->ext_vbus = 0;
1148 #endif
1149
1150 dwc_otg_core_init(priv);
1151 dwc_otg_core_host_init(dev, regs);
1152
1153 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1154 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1155 DWC2_HPRT0_PRTOVRCURRCHNG,
1156 DWC2_HPRT0_PRTRST);
1157 mdelay(50);
1158 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1159 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1160 DWC2_HPRT0_PRTRST);
1161
1162 for (i = 0; i < MAX_DEVICE; i++) {
1163 for (j = 0; j < MAX_ENDPOINT; j++) {
1164 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1165 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1166 }
1167 }
1168
1169 /*
1170 * Add a 1 second delay here. This gives the host controller
1171 * a bit time before the comminucation with the USB devices
1172 * is started (the bus is scanned) and fixes the USB detection
1173 * problems with some problematic USB keys.
1174 */
1175 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1176 mdelay(1000);
1177
1178 return 0;
1179 }
1180
dwc2_uninit_common(struct dwc2_core_regs * regs)1181 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1182 {
1183 /* Put everything in reset. */
1184 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1185 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1186 DWC2_HPRT0_PRTOVRCURRCHNG,
1187 DWC2_HPRT0_PRTRST);
1188 }
1189
1190 #ifndef CONFIG_DM_USB
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1191 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1192 int len, struct devrequest *setup)
1193 {
1194 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1195 }
1196
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len)1197 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1198 int len)
1199 {
1200 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1201 }
1202
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval)1203 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1204 int len, int interval)
1205 {
1206 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1207 }
1208
1209 /* U-Boot USB control interface */
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)1210 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1211 {
1212 struct dwc2_priv *priv = &local;
1213
1214 memset(priv, '\0', sizeof(*priv));
1215 priv->root_hub_devnum = 0;
1216 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1217 priv->aligned_buffer = aligned_buffer_addr;
1218 priv->status_buffer = status_buffer_addr;
1219
1220 /* board-dependant init */
1221 if (board_usb_init(index, USB_INIT_HOST))
1222 return -1;
1223
1224 return dwc2_init_common(NULL, priv);
1225 }
1226
usb_lowlevel_stop(int index)1227 int usb_lowlevel_stop(int index)
1228 {
1229 dwc2_uninit_common(local.regs);
1230
1231 return 0;
1232 }
1233 #endif
1234
1235 #ifdef CONFIG_DM_USB
dwc2_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1236 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1237 unsigned long pipe, void *buffer, int length,
1238 struct devrequest *setup)
1239 {
1240 struct dwc2_priv *priv = dev_get_priv(dev);
1241
1242 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1243 dev->name, udev, udev->dev->name, udev->portnr);
1244
1245 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1246 }
1247
dwc2_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)1248 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1249 unsigned long pipe, void *buffer, int length)
1250 {
1251 struct dwc2_priv *priv = dev_get_priv(dev);
1252
1253 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1254
1255 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1256 }
1257
dwc2_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval)1258 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1259 unsigned long pipe, void *buffer, int length,
1260 int interval)
1261 {
1262 struct dwc2_priv *priv = dev_get_priv(dev);
1263
1264 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1265
1266 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1267 }
1268
dwc2_usb_ofdata_to_platdata(struct udevice * dev)1269 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1270 {
1271 struct dwc2_priv *priv = dev_get_priv(dev);
1272 fdt_addr_t addr;
1273
1274 addr = dev_read_addr(dev);
1275 if (addr == FDT_ADDR_T_NONE)
1276 return -EINVAL;
1277 priv->regs = (struct dwc2_core_regs *)addr;
1278
1279 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1280 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1281
1282 return 0;
1283 }
1284
dwc2_usb_probe(struct udevice * dev)1285 static int dwc2_usb_probe(struct udevice *dev)
1286 {
1287 struct dwc2_priv *priv = dev_get_priv(dev);
1288 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1289
1290 bus_priv->desc_before_addr = true;
1291
1292 return dwc2_init_common(dev, priv);
1293 }
1294
dwc2_usb_remove(struct udevice * dev)1295 static int dwc2_usb_remove(struct udevice *dev)
1296 {
1297 struct dwc2_priv *priv = dev_get_priv(dev);
1298 int ret;
1299
1300 ret = dwc_vbus_supply_exit(dev);
1301 if (ret)
1302 return ret;
1303
1304 dwc2_uninit_common(priv->regs);
1305
1306 return 0;
1307 }
1308
1309 struct dm_usb_ops dwc2_usb_ops = {
1310 .control = dwc2_submit_control_msg,
1311 .bulk = dwc2_submit_bulk_msg,
1312 .interrupt = dwc2_submit_int_msg,
1313 };
1314
1315 static const struct udevice_id dwc2_usb_ids[] = {
1316 { .compatible = "brcm,bcm2835-usb" },
1317 { .compatible = "brcm,bcm2708-usb" },
1318 { .compatible = "snps,dwc2" },
1319 { }
1320 };
1321
1322 U_BOOT_DRIVER(usb_dwc2) = {
1323 .name = "dwc2_usb",
1324 .id = UCLASS_USB,
1325 .of_match = dwc2_usb_ids,
1326 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1327 .probe = dwc2_usb_probe,
1328 .remove = dwc2_usb_remove,
1329 .ops = &dwc2_usb_ops,
1330 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1331 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1332 };
1333 #endif
1334