1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 4 * Hayden Fraser (Hayden.Fraser@freescale.com) 5 */ 6 7 #ifndef _M5253EVBE_H 8 #define _M5253EVBE_H 9 10 #define CONFIG_MCFTMR 11 12 #define CONFIG_MCFUART 13 #define CONFIG_SYS_UART_PORT (0) 14 15 #undef CONFIG_WATCHDOG /* disable watchdog */ 16 17 18 /* Configuration for environment 19 * Environment is embedded in u-boot in the second sector of the flash 20 */ 21 #ifndef CONFIG_MONITOR_IS_IN_RAM 22 #define CONFIG_ENV_OFFSET 0x4000 23 #define CONFIG_ENV_SECT_SIZE 0x2000 24 #else 25 #define CONFIG_ENV_ADDR 0xffe04000 26 #define CONFIG_ENV_SECT_SIZE 0x2000 27 #endif 28 29 #define LDS_BOARD_TEXT \ 30 . = DEFINED(env_offset) ? env_offset : .; \ 31 env/embedded.o(.text) 32 33 /* 34 * BOOTP options 35 */ 36 #undef CONFIG_BOOTP_BOOTFILESIZE 37 38 /* 39 * Command line configuration. 40 */ 41 42 /* ATA */ 43 #define CONFIG_IDE_RESET 1 44 #define CONFIG_IDE_PREINIT 1 45 #define CONFIG_ATAPI 46 #undef CONFIG_LBA48 47 48 #define CONFIG_SYS_IDE_MAXBUS 1 49 #define CONFIG_SYS_IDE_MAXDEVICE 2 50 51 #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 52 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 53 54 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 55 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 56 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 57 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 58 59 #define CONFIG_SYS_LOAD_ADDR 0x00100000 60 61 #define CONFIG_SYS_MEMTEST_START 0x400 62 #define CONFIG_SYS_MEMTEST_END 0x380000 63 64 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 65 #define CONFIG_SYS_FAST_CLK 66 #ifdef CONFIG_SYS_FAST_CLK 67 # define CONFIG_SYS_PLLCR 0x1243E054 68 # define CONFIG_SYS_CLK 140000000 69 #else 70 # define CONFIG_SYS_PLLCR 0x135a4140 71 # define CONFIG_SYS_CLK 70000000 72 #endif 73 74 /* 75 * Low Level Configuration Settings 76 * (address mappings, register initial values, etc.) 77 * You should know what you are doing if you make changes here. 78 */ 79 80 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 81 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 82 83 /* 84 * Definitions for initial stack pointer and data area (in DPRAM) 85 */ 86 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 87 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 88 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 89 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 90 91 /* 92 * Start addresses for the final memory configuration 93 * (Set up by the startup code) 94 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 95 */ 96 #define CONFIG_SYS_SDRAM_BASE 0x00000000 97 #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ 98 99 #ifdef CONFIG_MONITOR_IS_IN_RAM 100 #define CONFIG_SYS_MONITOR_BASE 0x20000 101 #else 102 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 103 #endif 104 105 #define CONFIG_SYS_MONITOR_LEN 0x40000 106 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 107 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 108 109 /* 110 * For booting Linux, the board info and command line data 111 * have to be in the first 8 MB of memory, since this is 112 * the maximum mapped by the Linux kernel during initialization ?? 113 */ 114 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 115 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 116 117 /* FLASH organization */ 118 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 120 #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ 121 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 122 123 #define CONFIG_SYS_FLASH_CFI 1 124 #define CONFIG_FLASH_CFI_DRIVER 1 125 #define CONFIG_SYS_FLASH_SIZE 0x200000 126 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 127 128 /* Cache Configuration */ 129 #define CONFIG_SYS_CACHELINE_SIZE 16 130 131 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 132 CONFIG_SYS_INIT_RAM_SIZE - 8) 133 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 134 CONFIG_SYS_INIT_RAM_SIZE - 4) 135 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 136 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 137 CF_ADDRMASK(2) | \ 138 CF_ACR_EN | CF_ACR_SM_ALL) 139 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 140 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 141 CF_ACR_EN | CF_ACR_SM_ALL) 142 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 143 CF_CACR_DBWE) 144 145 /* Port configuration */ 146 #define CONFIG_SYS_FECI2C 0xF0 147 148 #define CONFIG_SYS_CS0_BASE 0xFFE00000 149 #define CONFIG_SYS_CS0_MASK 0x001F0021 150 #define CONFIG_SYS_CS0_CTRL 0x00001D80 151 152 /*----------------------------------------------------------------------- 153 * Port configuration 154 */ 155 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 156 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 157 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 158 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 159 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 160 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 161 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 162 163 #endif /* _M5253EVB_H */ 164