1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuration for Xilinx ZynqMP zcu111
4  *
5  * (C) Copyright 2017 Xilinx, Inc.
6  * Michal Simek <michal.simek@xilinx.com>
7  */
8 
9 #ifndef __CONFIG_ZYNQMP_ZCU111_H
10 #define __CONFIG_ZYNQMP_ZCU111_H
11 
12 #define CONFIG_ZYNQ_SDHCI1
13 #define CONFIG_SYS_I2C_MAX_HOPS		1
14 #define CONFIG_SYS_NUM_I2C_BUSES	21
15 #define CONFIG_SYS_I2C_BUSES	{ \
16 				{0, {I2C_NULL_HOP} }, \
17 				{0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
18 				{0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
19 				{0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
20 				{0, {{I2C_MUX_PCA9544, 0x75, 3} } }, \
21 				{1, {I2C_NULL_HOP} }, \
22 				{1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
23 				{1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
24 				{1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
25 				{1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
26 				{1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
27 				{1, {{I2C_MUX_PCA9548, 0x74, 5} } }, \
28 				{1, {{I2C_MUX_PCA9548, 0x74, 6} } }, \
29 				{1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
30 				{1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
31 				{1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
32 				{1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
33 				{1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
34 				{1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
35 				{1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
36 				{1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
37 				}
38 
39 #define CONFIG_PCA953X
40 
41 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
42 #define CONFIG_ZYNQ_EEPROM_BUS		5
43 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR	0x54
44 
45 #include <configs/xilinx_zynqmp.h>
46 
47 #endif /* __CONFIG_ZYNQMP_ZCU111_H */
48