1// Copyright 2016, VIXL authors
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7//   * Redistributions of source code must retain the above copyright notice,
8//     this list of conditions and the following disclaimer.
9//   * Redistributions in binary form must reproduce the above copyright notice,
10//     this list of conditions and the following disclaimer in the documentation
11//     and/or other materials provided with the distribution.
12//   * Neither the name of ARM Limited nor the names of its contributors may be
13//     used to endorse or promote products derived from this software without
14//     specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27// Test description for instructions of the following form:
28//   MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, ROR #<amount>
29
30{
31  "mnemonics": [
32    "Sxtab",   // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
33    "Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
34    "Sxtah",   // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
35    "Uxtab",   // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
36    "Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
37    "Uxtah"    // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
38  ],
39  "description": {
40    "operands": [
41      {
42        "name": "cond",
43        "type": "Condition"
44      },
45      {
46        "name": "rd",
47        "type": "AllRegistersButPC"
48      },
49      {
50        "name": "rn",
51        "type": "AllRegistersButPC"
52      },
53      {
54        "name": "op",
55        "wrapper": "Operand",
56        "operands": [
57          {
58            "name": "rm",
59            "type": "AllRegistersButPC"
60          },
61          {
62            "name": "ror",
63            "type": "ShiftROR"
64          },
65          {
66            "name": "amount",
67            "type": "ShiftRotationAmountX8"
68          }
69        ]
70      }
71    ],
72    "inputs": [
73      {
74        "name": "apsr",
75        "type": "NZCV"
76      },
77      {
78        "name": "rd",
79        "type": "Register"
80      },
81      {
82        "name": "rn",
83        "type": "Register"
84      },
85      {
86        "name": "rm",
87        "type": "Register"
88      }
89    ]
90  },
91  "test-files": [
92    {
93      "type": "assembler",
94      "test-cases": [
95        {
96          "name": "Operands",
97          "operands": [
98            "cond", "rd", "rn", "rm", "ror", "amount"
99          ],
100          "operand-filter": "cond == 'al'",
101          "operand-limit": 1000
102        }
103      ]
104    },
105    {
106      "type": "simulator",
107      "test-cases": [
108        {
109          "name": "Condition",
110          "operands": [
111            "cond"
112          ],
113          "inputs": [
114            "apsr"
115          ]
116        },
117        // Test combinations of registers values with rd == rn.
118        {
119          "name": "RdIsRn",
120          "operands": [
121            "rd", "rn", "rm"
122          ],
123          "inputs": [
124            "rd", "rn", "rm"
125          ],
126          "operand-filter": "rd == rn and rn != rm",
127          "operand-limit": 10,
128          "input-filter": "rd == rn",
129          "input-limit": 200
130        },
131        // Test combinations of registers values with rd == rm.
132        {
133          "name": "RdIsRm",
134          "operands": [
135            "rd", "rn", "rm"
136          ],
137          "inputs": [
138            "rd", "rn", "rm"
139          ],
140          "operand-filter": "rd == rm and rn != rm",
141          "operand-limit": 10,
142          "input-filter": "rd == rm",
143          "input-limit": 200
144        },
145        // Test combinations of registers values.
146        {
147          "name": "RdIsNotRnIsNotRm",
148          "operands": [
149            "rd", "rn", "rm"
150          ],
151          "inputs": [
152            "rd", "rn", "rm"
153          ],
154          "operand-filter": "rd != rn != rm",
155          "operand-limit": 10,
156          "input-limit": 200
157        },
158        // Test combinations of rotation amounts.
159        {
160          "name": "Rotations",
161          "operands": [
162            "rd", "rn", "rm", "ror", "amount"
163          ],
164          "inputs": [
165            "rm"
166          ],
167          // Specify exactly what registers to use in this test to make sure
168          // that they are different. It makes the execution trace more
169          // understandable.
170          "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r2'"
171        }
172      ]
173    }
174  ]
175}
176