1// Copyright 2016, VIXL authors
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7//   * Redistributions of source code must retain the above copyright notice,
8//     this list of conditions and the following disclaimer.
9//   * Redistributions in binary form must reproduce the above copyright notice,
10//     this list of conditions and the following disclaimer in the documentation
11//     and/or other materials provided with the distribution.
12//   * Neither the name of ARM Limited nor the names of its contributors may be
13//     used to endorse or promote products derived from this software without
14//     specific prior written permission.
15//
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24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27// Test description for instructions of the following form:
28//   MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, LSL|ROR #<amount>
29//   MNEMONIC{<c>}.W <Rd>, SP,   <Rm>, LSL|ROR #<amount>
30
31{
32  "mnemonics": [
33    "Adc",  // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
34    "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
35    "Add",  // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
36            // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
37    "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38            // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
39    "And",  // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
40    "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
41    "Bic",  // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
42    "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
43    "Eor",  // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
44    "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
45    "Orn",  // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
46    "Orns", // ORNS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
47    "Orr",  // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
48    "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
49    "Rsb",  // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
50    "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
51    "Sbc",  // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
52    "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
53    "Sub",  // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
54            // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
55    "Subs"  // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
56            // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
57  ],
58  "description": {
59    "operands": [
60      {
61        "name": "cond",
62        "type": "Condition"
63      },
64      {
65        "name": "rd",
66        "type": "AllRegistersButPC"
67      },
68      {
69        "name": "rn",
70        "type": "AllRegistersButPC"
71      },
72      {
73        "name": "op",
74        "wrapper": "Operand",
75        "operands": [
76          {
77            "name": "rm",
78            "type": "AllRegistersButPC"
79          },
80          {
81            "name": "shift",
82            "type": "Shift1To31"
83          },
84          {
85            "name": "amount",
86            "type": "ShiftAmount1To31"
87          }
88        ]
89      }
90    ],
91    "inputs": [
92      {
93        "name": "apsr",
94        "type": "NZCV"
95      },
96      {
97        "name": "rd",
98        "type": "Register"
99      },
100      {
101        "name": "rn",
102        "type": "Register"
103      },
104      {
105        "name": "rm",
106        "type": "Register"
107      }
108    ]
109  },
110  "test-files": [
111    {
112      "type": "assembler",
113      "test-cases": [
114        {
115          "name": "Operands",
116          "operands": [
117            "cond", "rd", "rn", "rm", "shift", "amount"
118          ],
119          "operand-filter": "cond == 'al'",
120          "operand-limit": 500
121        }
122      ]
123    },
124    {
125      "type": "simulator",
126      "test-cases": [
127        {
128          "name": "Condition",
129          "operands": [
130            "cond"
131          ],
132          "inputs": [
133            "apsr"
134          ]
135        },
136        // Test combinations of registers values with rd == rn.
137        {
138          "name": "RdIsRn",
139          "operands": [
140            "rd", "rn", "rm"
141          ],
142          "inputs": [
143            "rd", "rn", "rm"
144          ],
145          "operand-filter": "rd == rn and rn != rm",
146          "operand-limit": 10,
147          "input-filter": "rd == rn",
148          "input-limit": 200
149        },
150        // Test combinations of registers values with rd == rm.
151        {
152          "name": "RdIsRm",
153          "operands": [
154            "rd", "rn", "rm"
155          ],
156          "inputs": [
157            "rd", "rn", "rm"
158          ],
159          "operand-filter": "rd == rm and rn != rm",
160          "operand-limit": 10,
161          "input-filter": "rd == rm",
162          "input-limit": 200
163        },
164        // Test combinations of registers values.
165        {
166          "name": "RdIsNotRnIsNotRm",
167          "operands": [
168            "rd", "rn", "rm"
169          ],
170          "inputs": [
171            "rd", "rn", "rm"
172          ],
173          "operand-filter": "rd != rn != rm",
174          "operand-limit": 10,
175          "input-limit": 200
176        },
177        // Test combinations of shift types and shift amounts.
178        {
179          "name": "ShiftTypes",
180          "operands": [
181            "rd", "rn", "rm", "shift", "amount"
182          ],
183          "inputs": [
184            "rm"
185          ],
186          // Specify exactly what registers to use in this test to make sure
187          // that they are different. It makes the execution trace more
188          // understandable.
189          "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r2'"
190        }
191      ]
192    }
193  ]
194}
195