1 // Copyright 2016, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27
28 // -----------------------------------------------------------------------------
29 // This file is auto generated from the
30 // test/aarch32/config/template-simulator-aarch32.cc.in template file using
31 // tools/generate_tests.py.
32 //
33 // PLEASE DO NOT EDIT.
34 // -----------------------------------------------------------------------------
35
36
37 #include "test-runner.h"
38
39 #include "test-utils.h"
40 #include "test-utils-aarch32.h"
41
42 #include "aarch32/assembler-aarch32.h"
43 #include "aarch32/disasm-aarch32.h"
44 #include "aarch32/macro-assembler-aarch32.h"
45
46 #define __ masm.
47 #define BUF_SIZE (4096)
48
49 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
50 // Run tests with the simulator.
51
52 #define SETUP() MacroAssembler masm(BUF_SIZE)
53
54 #define START() masm.GetBuffer()->Reset()
55
56 #define END() \
57 __ Hlt(0); \
58 __ FinalizeCode();
59
60 // TODO: Run the tests in the simulator.
61 #define RUN()
62
63 #else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
64
65 #define SETUP() \
66 MacroAssembler masm(BUF_SIZE); \
67 UseScratchRegisterScope harness_scratch;
68
69 #define START() \
70 harness_scratch.Open(&masm); \
71 harness_scratch.ExcludeAll(); \
72 masm.GetBuffer()->Reset(); \
73 __ Push(r4); \
74 __ Push(r5); \
75 __ Push(r6); \
76 __ Push(r7); \
77 __ Push(r8); \
78 __ Push(r9); \
79 __ Push(r10); \
80 __ Push(r11); \
81 __ Push(lr); \
82 harness_scratch.Include(ip);
83
84 #define END() \
85 harness_scratch.Exclude(ip); \
86 __ Pop(lr); \
87 __ Pop(r11); \
88 __ Pop(r10); \
89 __ Pop(r9); \
90 __ Pop(r8); \
91 __ Pop(r7); \
92 __ Pop(r6); \
93 __ Pop(r5); \
94 __ Pop(r4); \
95 __ Bx(lr); \
96 __ FinalizeCode(); \
97 harness_scratch.Close();
98
99 #define RUN() \
100 { \
101 int pcs_offset = masm.IsUsingT32() ? 1 : 0; \
102 masm.GetBuffer()->SetExecutable(); \
103 ExecuteMemory(masm.GetBuffer()->GetStartAddress<byte*>(), \
104 masm.GetSizeOfCodeGenerated(), \
105 pcs_offset); \
106 masm.GetBuffer()->SetWritable(); \
107 }
108
109 #endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
110
111 namespace vixl {
112 namespace aarch32 {
113
114 // List of instruction encodings:
115 #define FOREACH_INSTRUCTION(M) \
116 M(Mov) \
117 M(Movt)
118
119
120 // The following definitions are defined again in each generated test, therefore
121 // we need to place them in an anomymous namespace. It expresses that they are
122 // local to this file only, and the compiler is not allowed to share these types
123 // across test files during template instantiation. Specifically, `Operands` and
124 // `Inputs` have various layouts across generated tests so they absolutely
125 // cannot be shared.
126
127 #ifdef VIXL_INCLUDE_TARGET_T32
128 namespace {
129
130 // Values to be passed to the assembler to produce the instruction under test.
131 struct Operands {
132 Condition cond;
133 Register rd;
134 uint32_t immediate;
135 };
136
137 // Input data to feed to the instruction.
138 struct Inputs {
139 uint32_t apsr;
140 uint32_t rd;
141 };
142
143 // This structure contains all input data needed to test one specific encoding.
144 // It used to generate a loop over an instruction.
145 struct TestLoopData {
146 // The `operands` fields represents the values to pass to the assembler to
147 // produce the instruction.
148 Operands operands;
149 // Description of the operands, used for error reporting.
150 const char* operands_description;
151 // Unique identifier, used for generating traces.
152 const char* identifier;
153 // Array of values to be fed to the instruction.
154 size_t input_size;
155 const Inputs* inputs;
156 };
157
158 static const Inputs kCondition[] = {{NFlag, 0xabababab},
159 {ZFlag, 0xabababab},
160 {CFlag, 0xabababab},
161 {VFlag, 0xabababab},
162 {NZFlag, 0xabababab},
163 {NCFlag, 0xabababab},
164 {NVFlag, 0xabababab},
165 {ZCFlag, 0xabababab},
166 {ZVFlag, 0xabababab},
167 {CVFlag, 0xabababab},
168 {NZCFlag, 0xabababab},
169 {NZVFlag, 0xabababab},
170 {NCVFlag, 0xabababab},
171 {ZCVFlag, 0xabababab},
172 {NZCVFlag, 0xabababab}};
173
174 static const Inputs kModifiedImmediate[] =
175 {{NoFlag, 0x00000000}, {NoFlag, 0x00000001}, {NoFlag, 0x00000002},
176 {NoFlag, 0x00000020}, {NoFlag, 0x0000007d}, {NoFlag, 0x0000007e},
177 {NoFlag, 0x0000007f}, {NoFlag, 0x00007ffd}, {NoFlag, 0x00007ffe},
178 {NoFlag, 0x00007fff}, {NoFlag, 0x33333333}, {NoFlag, 0x55555555},
179 {NoFlag, 0x7ffffffd}, {NoFlag, 0x7ffffffe}, {NoFlag, 0x7fffffff},
180 {NoFlag, 0x80000000}, {NoFlag, 0x80000001}, {NoFlag, 0xaaaaaaaa},
181 {NoFlag, 0xcccccccc}, {NoFlag, 0xffff8000}, {NoFlag, 0xffff8001},
182 {NoFlag, 0xffff8002}, {NoFlag, 0xffff8003}, {NoFlag, 0xffffff80},
183 {NoFlag, 0xffffff81}, {NoFlag, 0xffffff82}, {NoFlag, 0xffffff83},
184 {NoFlag, 0xffffffe0}, {NoFlag, 0xfffffffd}, {NoFlag, 0xfffffffe},
185 {NoFlag, 0xffffffff}};
186
187
188 // A loop will be generated for each element of this array.
189 const TestLoopData kTests[] = {{{eq, r0, 0x0},
190 "eq r0 0x0",
191 "Condition_eq_r0_0x0",
192 ARRAY_SIZE(kCondition),
193 kCondition},
194 {{ne, r0, 0x0},
195 "ne r0 0x0",
196 "Condition_ne_r0_0x0",
197 ARRAY_SIZE(kCondition),
198 kCondition},
199 {{cs, r0, 0x0},
200 "cs r0 0x0",
201 "Condition_cs_r0_0x0",
202 ARRAY_SIZE(kCondition),
203 kCondition},
204 {{cc, r0, 0x0},
205 "cc r0 0x0",
206 "Condition_cc_r0_0x0",
207 ARRAY_SIZE(kCondition),
208 kCondition},
209 {{mi, r0, 0x0},
210 "mi r0 0x0",
211 "Condition_mi_r0_0x0",
212 ARRAY_SIZE(kCondition),
213 kCondition},
214 {{pl, r0, 0x0},
215 "pl r0 0x0",
216 "Condition_pl_r0_0x0",
217 ARRAY_SIZE(kCondition),
218 kCondition},
219 {{vs, r0, 0x0},
220 "vs r0 0x0",
221 "Condition_vs_r0_0x0",
222 ARRAY_SIZE(kCondition),
223 kCondition},
224 {{vc, r0, 0x0},
225 "vc r0 0x0",
226 "Condition_vc_r0_0x0",
227 ARRAY_SIZE(kCondition),
228 kCondition},
229 {{hi, r0, 0x0},
230 "hi r0 0x0",
231 "Condition_hi_r0_0x0",
232 ARRAY_SIZE(kCondition),
233 kCondition},
234 {{ls, r0, 0x0},
235 "ls r0 0x0",
236 "Condition_ls_r0_0x0",
237 ARRAY_SIZE(kCondition),
238 kCondition},
239 {{ge, r0, 0x0},
240 "ge r0 0x0",
241 "Condition_ge_r0_0x0",
242 ARRAY_SIZE(kCondition),
243 kCondition},
244 {{lt, r0, 0x0},
245 "lt r0 0x0",
246 "Condition_lt_r0_0x0",
247 ARRAY_SIZE(kCondition),
248 kCondition},
249 {{gt, r0, 0x0},
250 "gt r0 0x0",
251 "Condition_gt_r0_0x0",
252 ARRAY_SIZE(kCondition),
253 kCondition},
254 {{le, r0, 0x0},
255 "le r0 0x0",
256 "Condition_le_r0_0x0",
257 ARRAY_SIZE(kCondition),
258 kCondition},
259 {{al, r0, 0x0},
260 "al r0 0x0",
261 "Condition_al_r0_0x0",
262 ARRAY_SIZE(kCondition),
263 kCondition},
264 {{al, r0, 0x0000},
265 "al r0 0x0000",
266 "ModifiedImmediate_al_r0_0x0000",
267 ARRAY_SIZE(kModifiedImmediate),
268 kModifiedImmediate},
269 {{al, r0, 0x0001},
270 "al r0 0x0001",
271 "ModifiedImmediate_al_r0_0x0001",
272 ARRAY_SIZE(kModifiedImmediate),
273 kModifiedImmediate},
274 {{al, r0, 0x0002},
275 "al r0 0x0002",
276 "ModifiedImmediate_al_r0_0x0002",
277 ARRAY_SIZE(kModifiedImmediate),
278 kModifiedImmediate},
279 {{al, r0, 0x0020},
280 "al r0 0x0020",
281 "ModifiedImmediate_al_r0_0x0020",
282 ARRAY_SIZE(kModifiedImmediate),
283 kModifiedImmediate},
284 {{al, r0, 0x007d},
285 "al r0 0x007d",
286 "ModifiedImmediate_al_r0_0x007d",
287 ARRAY_SIZE(kModifiedImmediate),
288 kModifiedImmediate},
289 {{al, r0, 0x007e},
290 "al r0 0x007e",
291 "ModifiedImmediate_al_r0_0x007e",
292 ARRAY_SIZE(kModifiedImmediate),
293 kModifiedImmediate},
294 {{al, r0, 0x007f},
295 "al r0 0x007f",
296 "ModifiedImmediate_al_r0_0x007f",
297 ARRAY_SIZE(kModifiedImmediate),
298 kModifiedImmediate},
299 {{al, r0, 0x7ffd},
300 "al r0 0x7ffd",
301 "ModifiedImmediate_al_r0_0x7ffd",
302 ARRAY_SIZE(kModifiedImmediate),
303 kModifiedImmediate},
304 {{al, r0, 0x7ffe},
305 "al r0 0x7ffe",
306 "ModifiedImmediate_al_r0_0x7ffe",
307 ARRAY_SIZE(kModifiedImmediate),
308 kModifiedImmediate},
309 {{al, r0, 0x7fff},
310 "al r0 0x7fff",
311 "ModifiedImmediate_al_r0_0x7fff",
312 ARRAY_SIZE(kModifiedImmediate),
313 kModifiedImmediate},
314 {{al, r0, 0x3333},
315 "al r0 0x3333",
316 "ModifiedImmediate_al_r0_0x3333",
317 ARRAY_SIZE(kModifiedImmediate),
318 kModifiedImmediate},
319 {{al, r0, 0x5555},
320 "al r0 0x5555",
321 "ModifiedImmediate_al_r0_0x5555",
322 ARRAY_SIZE(kModifiedImmediate),
323 kModifiedImmediate},
324 {{al, r0, 0xaaaa},
325 "al r0 0xaaaa",
326 "ModifiedImmediate_al_r0_0xaaaa",
327 ARRAY_SIZE(kModifiedImmediate),
328 kModifiedImmediate},
329 {{al, r0, 0xcccc},
330 "al r0 0xcccc",
331 "ModifiedImmediate_al_r0_0xcccc",
332 ARRAY_SIZE(kModifiedImmediate),
333 kModifiedImmediate},
334 {{al, r0, 0x8000},
335 "al r0 0x8000",
336 "ModifiedImmediate_al_r0_0x8000",
337 ARRAY_SIZE(kModifiedImmediate),
338 kModifiedImmediate},
339 {{al, r0, 0x8001},
340 "al r0 0x8001",
341 "ModifiedImmediate_al_r0_0x8001",
342 ARRAY_SIZE(kModifiedImmediate),
343 kModifiedImmediate},
344 {{al, r0, 0x8002},
345 "al r0 0x8002",
346 "ModifiedImmediate_al_r0_0x8002",
347 ARRAY_SIZE(kModifiedImmediate),
348 kModifiedImmediate},
349 {{al, r0, 0x8003},
350 "al r0 0x8003",
351 "ModifiedImmediate_al_r0_0x8003",
352 ARRAY_SIZE(kModifiedImmediate),
353 kModifiedImmediate},
354 {{al, r0, 0xff80},
355 "al r0 0xff80",
356 "ModifiedImmediate_al_r0_0xff80",
357 ARRAY_SIZE(kModifiedImmediate),
358 kModifiedImmediate},
359 {{al, r0, 0xff81},
360 "al r0 0xff81",
361 "ModifiedImmediate_al_r0_0xff81",
362 ARRAY_SIZE(kModifiedImmediate),
363 kModifiedImmediate},
364 {{al, r0, 0xff82},
365 "al r0 0xff82",
366 "ModifiedImmediate_al_r0_0xff82",
367 ARRAY_SIZE(kModifiedImmediate),
368 kModifiedImmediate},
369 {{al, r0, 0xff83},
370 "al r0 0xff83",
371 "ModifiedImmediate_al_r0_0xff83",
372 ARRAY_SIZE(kModifiedImmediate),
373 kModifiedImmediate},
374 {{al, r0, 0xffe0},
375 "al r0 0xffe0",
376 "ModifiedImmediate_al_r0_0xffe0",
377 ARRAY_SIZE(kModifiedImmediate),
378 kModifiedImmediate},
379 {{al, r0, 0xfffd},
380 "al r0 0xfffd",
381 "ModifiedImmediate_al_r0_0xfffd",
382 ARRAY_SIZE(kModifiedImmediate),
383 kModifiedImmediate},
384 {{al, r0, 0xfffe},
385 "al r0 0xfffe",
386 "ModifiedImmediate_al_r0_0xfffe",
387 ARRAY_SIZE(kModifiedImmediate),
388 kModifiedImmediate},
389 {{al, r0, 0xffff},
390 "al r0 0xffff",
391 "ModifiedImmediate_al_r0_0xffff",
392 ARRAY_SIZE(kModifiedImmediate),
393 kModifiedImmediate}};
394
395 // We record all inputs to the instructions as outputs. This way, we also check
396 // that what shouldn't change didn't change.
397 struct TestResult {
398 size_t output_size;
399 const Inputs* outputs;
400 };
401
402 // These headers each contain an array of `TestResult` with the reference output
403 // values. The reference arrays are names `kReference{mnemonic}`.
404 #include "aarch32/traces/simulator-cond-rd-operand-imm16-mov-t32.h"
405 #include "aarch32/traces/simulator-cond-rd-operand-imm16-movt-t32.h"
406
407
408 // The maximum number of errors to report in detail for each test.
409 const unsigned kErrorReportLimit = 8;
410
411 typedef void (MacroAssembler::*Fn)(Condition cond,
412 Register rd,
413 const Operand& op);
414
TestHelper(Fn instruction,const char * mnemonic,const TestResult reference[])415 void TestHelper(Fn instruction,
416 const char* mnemonic,
417 const TestResult reference[]) {
418 SETUP();
419 masm.UseT32();
420 START();
421
422 // Data to compare to `reference`.
423 TestResult* results[ARRAY_SIZE(kTests)];
424
425 // Test cases for memory bound instructions may allocate a buffer and save its
426 // address in this array.
427 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)];
428
429 // Generate a loop for each element in `kTests`. Each loop tests one specific
430 // instruction.
431 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
432 // Allocate results on the heap for this test.
433 results[i] = new TestResult;
434 results[i]->outputs = new Inputs[kTests[i].input_size];
435 results[i]->output_size = kTests[i].input_size;
436
437 size_t input_stride = sizeof(kTests[i].inputs[0]) * kTests[i].input_size;
438 VIXL_ASSERT(IsUint32(input_stride));
439
440 scratch_memory_buffers[i] = NULL;
441
442 Label loop;
443 UseScratchRegisterScope scratch_registers(&masm);
444 // Include all registers from r0 ro r12.
445 scratch_registers.Include(RegisterList(0x1fff));
446
447 // Values to pass to the macro-assembler.
448 Condition cond = kTests[i].operands.cond;
449 Register rd = kTests[i].operands.rd;
450 uint32_t immediate = kTests[i].operands.immediate;
451 Operand op(immediate);
452 scratch_registers.Exclude(rd);
453
454 // Allocate reserved registers for our own use.
455 Register input_ptr = scratch_registers.Acquire();
456 Register input_end = scratch_registers.Acquire();
457 Register result_ptr = scratch_registers.Acquire();
458
459 // Initialize `input_ptr` to the first element and `input_end` the address
460 // after the array.
461 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
462 __ Add(input_end, input_ptr, static_cast<uint32_t>(input_stride));
463 __ Mov(result_ptr, Operand::From(results[i]->outputs));
464 __ Bind(&loop);
465
466 {
467 UseScratchRegisterScope temp_registers(&masm);
468 Register nzcv_bits = temp_registers.Acquire();
469 Register saved_q_bit = temp_registers.Acquire();
470 // Save the `Q` bit flag.
471 __ Mrs(saved_q_bit, APSR);
472 __ And(saved_q_bit, saved_q_bit, QFlag);
473 // Set the `NZCV` and `Q` flags together.
474 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
475 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
476 __ Msr(APSR_nzcvq, nzcv_bits);
477 }
478 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
479
480 (masm.*instruction)(cond, rd, op);
481
482 {
483 UseScratchRegisterScope temp_registers(&masm);
484 Register nzcv_bits = temp_registers.Acquire();
485 __ Mrs(nzcv_bits, APSR);
486 // Only record the NZCV bits.
487 __ And(nzcv_bits, nzcv_bits, NZCVFlag);
488 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr)));
489 }
490 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd)));
491
492 // Advance the result pointer.
493 __ Add(result_ptr, result_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
494 // Loop back until `input_ptr` is lower than `input_base`.
495 __ Add(input_ptr, input_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
496 __ Cmp(input_ptr, input_end);
497 __ B(ne, &loop);
498 }
499
500 END();
501
502 RUN();
503
504 if (Test::generate_test_trace()) {
505 // Print the results.
506 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
507 printf("const Inputs kOutputs_%s_%s[] = {\n",
508 mnemonic,
509 kTests[i].identifier);
510 for (size_t j = 0; j < results[i]->output_size; j++) {
511 printf(" { ");
512 printf("0x%08" PRIx32, results[i]->outputs[j].apsr);
513 printf(", ");
514 printf("0x%08" PRIx32, results[i]->outputs[j].rd);
515 printf(" },\n");
516 }
517 printf("};\n");
518 }
519 printf("const TestResult kReference%s[] = {\n", mnemonic);
520 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
521 printf(" {\n");
522 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n",
523 mnemonic,
524 kTests[i].identifier);
525 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier);
526 printf(" },\n");
527 }
528 printf("};\n");
529 } else if (kCheckSimulatorTestResults) {
530 // Check the results.
531 unsigned total_error_count = 0;
532 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
533 bool instruction_has_errors = false;
534 for (size_t j = 0; j < kTests[i].input_size; j++) {
535 uint32_t apsr = results[i]->outputs[j].apsr;
536 uint32_t rd = results[i]->outputs[j].rd;
537 uint32_t apsr_input = kTests[i].inputs[j].apsr;
538 uint32_t rd_input = kTests[i].inputs[j].rd;
539 uint32_t apsr_ref = reference[i].outputs[j].apsr;
540 uint32_t rd_ref = reference[i].outputs[j].rd;
541
542 if (((apsr != apsr_ref) || (rd != rd_ref)) &&
543 (++total_error_count <= kErrorReportLimit)) {
544 // Print the instruction once even if it triggered multiple failures.
545 if (!instruction_has_errors) {
546 printf("Error(s) when testing \"%s %s\":\n",
547 mnemonic,
548 kTests[i].operands_description);
549 instruction_has_errors = true;
550 }
551 // Print subsequent errors.
552 printf(" Input: ");
553 printf("0x%08" PRIx32, apsr_input);
554 printf(", ");
555 printf("0x%08" PRIx32, rd_input);
556 printf("\n");
557 printf(" Expected: ");
558 printf("0x%08" PRIx32, apsr_ref);
559 printf(", ");
560 printf("0x%08" PRIx32, rd_ref);
561 printf("\n");
562 printf(" Found: ");
563 printf("0x%08" PRIx32, apsr);
564 printf(", ");
565 printf("0x%08" PRIx32, rd);
566 printf("\n\n");
567 }
568 }
569 }
570
571 if (total_error_count > kErrorReportLimit) {
572 printf("%u other errors follow.\n",
573 total_error_count - kErrorReportLimit);
574 }
575 VIXL_CHECK(total_error_count == 0);
576 } else {
577 VIXL_WARNING("Assembled the code, but did not run anything.\n");
578 }
579
580 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
581 delete[] results[i]->outputs;
582 delete results[i];
583 delete[] scratch_memory_buffers[i];
584 }
585 }
586
587 // Instantiate tests for each instruction in the list.
588 // TODO: Remove this limitation by having a sandboxing mechanism.
589 #if defined(VIXL_HOST_POINTER_32)
590 #define TEST(mnemonic) \
591 void Test_##mnemonic() { \
592 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \
593 } \
594 Test test_##mnemonic("AARCH32_SIMULATOR_COND_RD_OPERAND_IMM16_" #mnemonic \
595 "_T32", \
596 &Test_##mnemonic);
597 #else
598 #define TEST(mnemonic) \
599 void Test_##mnemonic() { \
600 VIXL_WARNING("This test can only run on a 32-bit host.\n"); \
601 USE(TestHelper); \
602 } \
603 Test test_##mnemonic("AARCH32_SIMULATOR_COND_RD_OPERAND_IMM16_" #mnemonic \
604 "_T32", \
605 &Test_##mnemonic);
606 #endif
607
608 FOREACH_INSTRUCTION(TEST)
609 #undef TEST
610
611 } // namespace
612 #endif
613
614 } // namespace aarch32
615 } // namespace vixl
616