| /art/compiler/optimizing/ |
| D | locations.h | 145 bool IsRegister() const { in IsRegister() function
162 return IsRegister() || IsFpuRegister() || IsRegisterPair() || IsFpuRegisterPair(); in IsRegisterKind()
166 DCHECK(IsRegister() || IsFpuRegister()); in reg()
182 DCHECK(IsRegister()); in AsRegister()
439 if (loc.IsRegister()) { in Add()
448 if (loc.IsRegister()) { in Remove()
652 return input.IsRegister() in IsFixedInput()
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| D | intrinsics_utils.h | 67 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory. in EmitNativeCode()
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| D | code_generator_x86_64.cc | 288 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg())); in EmitNativeCode()
831 DCHECK(index_.IsRegister()); in EmitNativeCode()
1494 if (destination.IsRegister()) { in Move()
1496 if (source.IsRegister()) { in Move()
1515 if (source.IsRegister()) { in Move()
1534 if (source.IsRegister()) { in Move()
1551 if (source.IsRegister()) { in Move()
1571 DCHECK(location.IsRegister()); in MoveConstant()
1581 if (location.IsRegister()) { in AddLocationAsTemp()
1797 if (lhs.IsRegister()) { in GenerateTestAndBranch()
[all …]
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| D | register_allocator_linear_scan.cc | 133 DCHECK(location.IsRegister() || location.IsFpuRegister()); in BlockRegister()
134 LiveInterval* interval = location.IsRegister() in BlockRegister()
137 DataType::Type type = location.IsRegister() in BlockRegister()
142 if (location.IsRegister()) { in BlockRegister()
233 if (temp.IsRegister() || temp.IsFpuRegister()) { in ProcessInstruction()
292 if (input.IsRegister() || input.IsFpuRegister()) { in ProcessInstruction()
347 if (first.IsRegister() || first.IsFpuRegister()) { in ProcessInstruction()
357 } else if (output.IsRegister() || output.IsFpuRegister()) { in ProcessInstruction()
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| D | locations.cc | 100 if (location.IsRegister() || location.IsFpuRegister()) { in operator <<()
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| D | common_arm64.h | 67 DCHECK(location.IsRegister()) << location; in XRegisterFrom()
72 DCHECK(location.IsRegister()) << location; in WRegisterFrom()
164 if (location.IsRegister()) { in OperandFrom()
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| D | common_arm.h | 66 DCHECK(location.IsRegister()) << location; in RegisterFrom()
191 if (location.IsRegister()) { in OperandFrom()
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| D | code_generator_x86.cc | 306 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg())); in EmitNativeCode()
1307 if (destination.IsRegister()) { in Move32()
1308 if (source.IsRegister()) { in Move32()
1317 if (source.IsRegister()) { in Move32()
1327 if (source.IsRegister()) { in Move32()
1415 DCHECK(location.IsRegister()); in MoveConstant()
1431 if (location.IsRegister()) { in AddLocationAsTemp()
1729 if (lhs.IsRegister()) { in GenerateTestAndBranch()
1919 if (true_loc.IsRegister()) { in VisitSelect()
2491 DCHECK(in.IsRegister()); in VisitNeg()
[all …]
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| D | register_allocator_graph_color.cc | 882 if (input.IsRegister() || input.IsFpuRegister()) { in CheckForFixedInputs()
907 if (out.IsRegister() || out.IsFpuRegister()) { in CheckForFixedOutput()
955 if (temp.IsRegister() || temp.IsFpuRegister()) { in CheckForTempLiveIntervals()
1062 DCHECK(location.IsRegister() || location.IsFpuRegister()); in BlockRegister()
1064 LiveInterval* interval = location.IsRegister() in BlockRegister()
1068 bool blocked_by_codegen = location.IsRegister() in BlockRegister()
1438 if (input.IsRegister() || input.IsFpuRegister()) { in FindCoalesceOpportunities()
1441 InterferenceNode* fixed_node = input.IsRegister() in FindCoalesceOpportunities()
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| D | code_generator_arm_vixl.cc | 546 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg())); in EmitNativeCode()
1794 if (!out.IsRegister() && !out.IsRegisterPair()) { in CanGenerateConditionalMove()
1806 if (out.IsRegister()) { in CanGenerateConditionalMove()
2442 if (destination.IsRegister()) { in Move32()
2443 if (source.IsRegister()) { in Move32()
2454 if (source.IsRegister()) { in Move32()
2463 if (source.IsRegister()) { in Move32()
2481 DCHECK(location.IsRegister()); in MoveConstant()
2494 if (location.IsRegister()) { in AddLocationAsTemp()
2670 DCHECK(cond_val.IsRegister()); in GenerateTestAndBranch()
[all …]
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| D | intrinsics_x86_64.cc | 268 DCHECK(out.IsRegister()); in InvokeOutOfLineIntrinsic()
1647 DCHECK(srcBegin.IsRegister()); in VisitStringGetCharsNoCheck()
2352 if (src.IsRegister()) { in GenBitCount()
2425 src.IsRegister()) { in GenOneBit()
2431 if (src.IsRegister()) { in GenOneBit()
2459 if (src.IsRegister()) { in GenOneBit()
2546 if (src.IsRegister()) { in GenLeadingZeros()
2619 if (src.IsRegister()) { in GenTrailingZeros()
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| D | code_generator_arm64.cc | 345 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg())); in EmitNativeCode()
719 DCHECK(index_.IsRegister()); in EmitNativeCode()
1050 if (loc.IsRegister()) { in FreeScratchLocation()
1244 DCHECK(location.IsRegister()); in MoveConstant()
1249 if (location.IsRegister()) { in AddLocationAsTemp()
1413 if (destination.IsRegister() || destination.IsFpuRegister()) { in MoveLocation()
1421 dst_type = destination.IsRegister() ? DataType::Type::kInt32 : DataType::Type::kFloat32; in MoveLocation()
1427 dst_type = destination.IsRegister() ? DataType::Type::kInt64 : DataType::Type::kFloat64; in MoveLocation()
1431 (destination.IsRegister() && !DataType::IsFloatingPointType(dst_type))); in MoveLocation()
1441 } else if (source.IsRegister()) { in MoveLocation()
[all …]
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| D | intrinsics_x86.cc | 360 DCHECK(out.IsRegister()); in InvokeOutOfLineIntrinsic()
615 if (codegen->GetInstructionSetFeatures().HasAVX2() && src.IsRegister()) { in GenLowestOneBit()
621 if (src.IsRegister()) { in GenLowestOneBit()
629 if (src.IsRegister()) { in GenLowestOneBit()
1462 DCHECK(srcBegin.IsRegister()); in VisitStringGetCharsNoCheck()
2256 if (src.IsRegister()) { in GenBitCount()
2325 if (src.IsRegister()) { in GenLeadingZeros()
2429 if (src.IsRegister()) { in GenTrailingZeros()
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| D | ssa_liveness_analysis.cc | 486 return other.IsRegister(); in SameRegisterKind()
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| D | ssa_liveness_analysis.h | 964 && (locations->InAt(0).IsRegister() in DefinitionRequiresRegister()
975 } else if (location.IsRegister() || location.IsRegisterPair()) { in DefinitionRequiresRegister()
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| D | parallel_move_test.cc | 44 } else if (location.IsRegister()) { in DumpLocationForTest()
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| D | register_allocation_resolver.cc | 500 return destination.IsRegister() in IsValidDestination()
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| D | graph_visualizer.cc | 288 if (location.IsRegister()) { in DumpLocation()
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| D | code_generator.cc | 70 } else if (location.IsRegister() || in CheckType()
883 if (location.IsRegister()) { in BlockIfInRegister()
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| /art/disassembler/ |
| D | disassembler_arm64.cc | 47 if (reg.IsRegister() && reg.Is64Bits()) { in AppendRegisterNameToOutput()
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| /art/compiler/utils/ |
| D | managed_register.h | 61 constexpr bool IsRegister() const { in IsRegister() function
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 74 (method_reg.IsRegister() ? kFramePointerSize /*method*/ : 0u); in BuildFrame()
79 if (method_reg.IsRegister()) { in BuildFrame()
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 118 CHECK_GE(frame_size, (pushed_values + (method_reg.IsRegister() ? 1u : 0u)) * kFramePointerSize); in BuildFrame()
121 if (method_reg.IsRegister()) { in BuildFrame()
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 726 core_reg_size + fp_reg_size + (method_reg.IsRegister() ? kXRegSizeInBytes : 0u)); in BuildFrame()
733 if (method_reg.IsRegister()) { in BuildFrame()
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 86 if (method_reg.IsRegister()) { in BuildFrame()
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