1 /*
2  * Copyright (C) 2011 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #include "assembler_x86.h"
18 
19 #include "base/casts.h"
20 #include "base/memory_region.h"
21 #include "entrypoints/quick/quick_entrypoints.h"
22 #include "thread.h"
23 
24 namespace art {
25 namespace x86 {
26 
operator <<(std::ostream & os,const XmmRegister & reg)27 std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28   return os << "XMM" << static_cast<int>(reg);
29 }
30 
operator <<(std::ostream & os,const X87Register & reg)31 std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32   return os << "ST" << static_cast<int>(reg);
33 }
34 
operator <<(std::ostream & os,const Address & addr)35 std::ostream& operator<<(std::ostream& os, const Address& addr) {
36   switch (addr.mod()) {
37     case 0:
38       if (addr.rm() != ESP || addr.index() == ESP) {
39         return os << "(%" << addr.rm() << ")";
40       } else if (addr.base() == EBP) {
41         return os << static_cast<int>(addr.disp32()) << "(,%" << addr.index()
42                   << "," << (1 << addr.scale()) << ")";
43       }
44       return os << "(%" << addr.base() << ",%" << addr.index() << "," << (1 << addr.scale()) << ")";
45     case 1:
46       if (addr.rm() != ESP || addr.index() == ESP) {
47         return os << static_cast<int>(addr.disp8()) << "(%" << addr.rm() << ")";
48       }
49       return os << static_cast<int>(addr.disp8()) << "(%" << addr.base() << ",%"
50                 << addr.index() << "," << (1 << addr.scale()) << ")";
51     case 2:
52       if (addr.rm() != ESP || addr.index() == ESP) {
53         return os << static_cast<int>(addr.disp32()) << "(%" << addr.rm() << ")";
54       }
55       return os << static_cast<int>(addr.disp32()) << "(%" << addr.base() << ",%"
56                 << addr.index() << "," << (1 << addr.scale()) << ")";
57     default:
58       return os << "<address?>";
59   }
60 }
61 
CpuHasAVXorAVX2FeatureFlag()62 bool X86Assembler::CpuHasAVXorAVX2FeatureFlag() {
63   if (has_AVX_ || has_AVX2_) {
64     return true;
65   }
66   return false;
67 }
68 
call(Register reg)69 void X86Assembler::call(Register reg) {
70   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
71   EmitUint8(0xFF);
72   EmitRegisterOperand(2, reg);
73 }
74 
75 
call(const Address & address)76 void X86Assembler::call(const Address& address) {
77   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
78   EmitUint8(0xFF);
79   EmitOperand(2, address);
80 }
81 
82 
call(Label * label)83 void X86Assembler::call(Label* label) {
84   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
85   EmitUint8(0xE8);
86   static const int kSize = 5;
87   // Offset by one because we already have emitted the opcode.
88   EmitLabel(label, kSize - 1);
89 }
90 
91 
call(const ExternalLabel & label)92 void X86Assembler::call(const ExternalLabel& label) {
93   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
94   intptr_t call_start = buffer_.GetPosition();
95   EmitUint8(0xE8);
96   EmitInt32(label.address());
97   static const intptr_t kCallExternalLabelSize = 5;
98   DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
99 }
100 
101 
pushl(Register reg)102 void X86Assembler::pushl(Register reg) {
103   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
104   EmitUint8(0x50 + reg);
105 }
106 
107 
pushl(const Address & address)108 void X86Assembler::pushl(const Address& address) {
109   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
110   EmitUint8(0xFF);
111   EmitOperand(6, address);
112 }
113 
114 
pushl(const Immediate & imm)115 void X86Assembler::pushl(const Immediate& imm) {
116   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
117   if (imm.is_int8()) {
118     EmitUint8(0x6A);
119     EmitUint8(imm.value() & 0xFF);
120   } else {
121     EmitUint8(0x68);
122     EmitImmediate(imm);
123   }
124 }
125 
126 
popl(Register reg)127 void X86Assembler::popl(Register reg) {
128   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129   EmitUint8(0x58 + reg);
130 }
131 
132 
popl(const Address & address)133 void X86Assembler::popl(const Address& address) {
134   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
135   EmitUint8(0x8F);
136   EmitOperand(0, address);
137 }
138 
139 
movl(Register dst,const Immediate & imm)140 void X86Assembler::movl(Register dst, const Immediate& imm) {
141   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
142   EmitUint8(0xB8 + dst);
143   EmitImmediate(imm);
144 }
145 
146 
movl(Register dst,Register src)147 void X86Assembler::movl(Register dst, Register src) {
148   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
149   EmitUint8(0x89);
150   EmitRegisterOperand(src, dst);
151 }
152 
153 
movl(Register dst,const Address & src)154 void X86Assembler::movl(Register dst, const Address& src) {
155   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
156   EmitUint8(0x8B);
157   EmitOperand(dst, src);
158 }
159 
160 
movl(const Address & dst,Register src)161 void X86Assembler::movl(const Address& dst, Register src) {
162   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163   EmitUint8(0x89);
164   EmitOperand(src, dst);
165 }
166 
167 
movl(const Address & dst,const Immediate & imm)168 void X86Assembler::movl(const Address& dst, const Immediate& imm) {
169   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170   EmitUint8(0xC7);
171   EmitOperand(0, dst);
172   EmitImmediate(imm);
173 }
174 
movl(const Address & dst,Label * lbl)175 void X86Assembler::movl(const Address& dst, Label* lbl) {
176   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177   EmitUint8(0xC7);
178   EmitOperand(0, dst);
179   EmitLabel(lbl, dst.length_ + 5);
180 }
181 
movntl(const Address & dst,Register src)182 void X86Assembler::movntl(const Address& dst, Register src) {
183   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184   EmitUint8(0x0F);
185   EmitUint8(0xC3);
186   EmitOperand(src, dst);
187 }
188 
blsi(Register dst,Register src)189 void X86Assembler::blsi(Register dst, Register src) {
190   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191   uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
192   uint8_t byte_one  = EmitVexPrefixByteOne(false, false, false, SET_VEX_M_0F_38);
193   uint8_t byte_two  = EmitVexPrefixByteTwo(false,
194                                            X86ManagedRegister::FromCpuRegister(dst),
195                                             SET_VEX_L_128, SET_VEX_PP_NONE);
196   EmitUint8(byte_zero);
197   EmitUint8(byte_one);
198   EmitUint8(byte_two);
199   EmitUint8(0xF3);
200   EmitRegisterOperand(3, src);
201 }
202 
blsmsk(Register dst,Register src)203 void X86Assembler::blsmsk(Register dst, Register src) {
204   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
205   uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
206   uint8_t byte_one = EmitVexPrefixByteOne(false, false, false, SET_VEX_M_0F_38);
207   uint8_t byte_two = EmitVexPrefixByteTwo(false,
208                                          X86ManagedRegister::FromCpuRegister(dst),
209                                          SET_VEX_L_128, SET_VEX_PP_NONE);
210   EmitUint8(byte_zero);
211   EmitUint8(byte_one);
212   EmitUint8(byte_two);
213   EmitUint8(0xF3);
214   EmitRegisterOperand(2, src);
215 }
216 
blsr(Register dst,Register src)217 void X86Assembler::blsr(Register dst, Register src) {
218   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
219   uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
220   uint8_t byte_one = EmitVexPrefixByteOne(false, false, false,  SET_VEX_M_0F_38);
221   uint8_t byte_two = EmitVexPrefixByteTwo(false,
222                                           X86ManagedRegister::FromCpuRegister(dst),
223                                           SET_VEX_L_128, SET_VEX_PP_NONE);
224   EmitUint8(byte_zero);
225   EmitUint8(byte_one);
226   EmitUint8(byte_two);
227   EmitUint8(0xF3);
228   EmitRegisterOperand(1, src);
229 }
230 
bswapl(Register dst)231 void X86Assembler::bswapl(Register dst) {
232   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
233   EmitUint8(0x0F);
234   EmitUint8(0xC8 + dst);
235 }
236 
bsfl(Register dst,Register src)237 void X86Assembler::bsfl(Register dst, Register src) {
238   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
239   EmitUint8(0x0F);
240   EmitUint8(0xBC);
241   EmitRegisterOperand(dst, src);
242 }
243 
bsfl(Register dst,const Address & src)244 void X86Assembler::bsfl(Register dst, const Address& src) {
245   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
246   EmitUint8(0x0F);
247   EmitUint8(0xBC);
248   EmitOperand(dst, src);
249 }
250 
bsrl(Register dst,Register src)251 void X86Assembler::bsrl(Register dst, Register src) {
252   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
253   EmitUint8(0x0F);
254   EmitUint8(0xBD);
255   EmitRegisterOperand(dst, src);
256 }
257 
bsrl(Register dst,const Address & src)258 void X86Assembler::bsrl(Register dst, const Address& src) {
259   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260   EmitUint8(0x0F);
261   EmitUint8(0xBD);
262   EmitOperand(dst, src);
263 }
264 
popcntl(Register dst,Register src)265 void X86Assembler::popcntl(Register dst, Register src) {
266   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
267   EmitUint8(0xF3);
268   EmitUint8(0x0F);
269   EmitUint8(0xB8);
270   EmitRegisterOperand(dst, src);
271 }
272 
popcntl(Register dst,const Address & src)273 void X86Assembler::popcntl(Register dst, const Address& src) {
274   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
275   EmitUint8(0xF3);
276   EmitUint8(0x0F);
277   EmitUint8(0xB8);
278   EmitOperand(dst, src);
279 }
280 
movzxb(Register dst,ByteRegister src)281 void X86Assembler::movzxb(Register dst, ByteRegister src) {
282   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
283   EmitUint8(0x0F);
284   EmitUint8(0xB6);
285   EmitRegisterOperand(dst, src);
286 }
287 
288 
movzxb(Register dst,const Address & src)289 void X86Assembler::movzxb(Register dst, const Address& src) {
290   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
291   EmitUint8(0x0F);
292   EmitUint8(0xB6);
293   EmitOperand(dst, src);
294 }
295 
296 
movsxb(Register dst,ByteRegister src)297 void X86Assembler::movsxb(Register dst, ByteRegister src) {
298   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
299   EmitUint8(0x0F);
300   EmitUint8(0xBE);
301   EmitRegisterOperand(dst, src);
302 }
303 
304 
movsxb(Register dst,const Address & src)305 void X86Assembler::movsxb(Register dst, const Address& src) {
306   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
307   EmitUint8(0x0F);
308   EmitUint8(0xBE);
309   EmitOperand(dst, src);
310 }
311 
312 
movb(Register,const Address &)313 void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
314   LOG(FATAL) << "Use movzxb or movsxb instead.";
315 }
316 
317 
movb(const Address & dst,ByteRegister src)318 void X86Assembler::movb(const Address& dst, ByteRegister src) {
319   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
320   EmitUint8(0x88);
321   EmitOperand(src, dst);
322 }
323 
324 
movb(const Address & dst,const Immediate & imm)325 void X86Assembler::movb(const Address& dst, const Immediate& imm) {
326   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
327   EmitUint8(0xC6);
328   EmitOperand(EAX, dst);
329   CHECK(imm.is_int8());
330   EmitUint8(imm.value() & 0xFF);
331 }
332 
333 
movzxw(Register dst,Register src)334 void X86Assembler::movzxw(Register dst, Register src) {
335   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
336   EmitUint8(0x0F);
337   EmitUint8(0xB7);
338   EmitRegisterOperand(dst, src);
339 }
340 
341 
movzxw(Register dst,const Address & src)342 void X86Assembler::movzxw(Register dst, const Address& src) {
343   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
344   EmitUint8(0x0F);
345   EmitUint8(0xB7);
346   EmitOperand(dst, src);
347 }
348 
349 
movsxw(Register dst,Register src)350 void X86Assembler::movsxw(Register dst, Register src) {
351   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
352   EmitUint8(0x0F);
353   EmitUint8(0xBF);
354   EmitRegisterOperand(dst, src);
355 }
356 
357 
movsxw(Register dst,const Address & src)358 void X86Assembler::movsxw(Register dst, const Address& src) {
359   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
360   EmitUint8(0x0F);
361   EmitUint8(0xBF);
362   EmitOperand(dst, src);
363 }
364 
365 
movw(Register,const Address &)366 void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
367   LOG(FATAL) << "Use movzxw or movsxw instead.";
368 }
369 
370 
movw(const Address & dst,Register src)371 void X86Assembler::movw(const Address& dst, Register src) {
372   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
373   EmitOperandSizeOverride();
374   EmitUint8(0x89);
375   EmitOperand(src, dst);
376 }
377 
378 
movw(const Address & dst,const Immediate & imm)379 void X86Assembler::movw(const Address& dst, const Immediate& imm) {
380   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
381   EmitOperandSizeOverride();
382   EmitUint8(0xC7);
383   EmitOperand(0, dst);
384   CHECK(imm.is_uint16() || imm.is_int16());
385   EmitUint8(imm.value() & 0xFF);
386   EmitUint8(imm.value() >> 8);
387 }
388 
389 
leal(Register dst,const Address & src)390 void X86Assembler::leal(Register dst, const Address& src) {
391   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
392   EmitUint8(0x8D);
393   EmitOperand(dst, src);
394 }
395 
396 
cmovl(Condition condition,Register dst,Register src)397 void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
398   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
399   EmitUint8(0x0F);
400   EmitUint8(0x40 + condition);
401   EmitRegisterOperand(dst, src);
402 }
403 
404 
cmovl(Condition condition,Register dst,const Address & src)405 void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
406   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
407   EmitUint8(0x0F);
408   EmitUint8(0x40 + condition);
409   EmitOperand(dst, src);
410 }
411 
412 
setb(Condition condition,Register dst)413 void X86Assembler::setb(Condition condition, Register dst) {
414   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
415   EmitUint8(0x0F);
416   EmitUint8(0x90 + condition);
417   EmitOperand(0, Operand(dst));
418 }
419 
420 
movaps(XmmRegister dst,XmmRegister src)421 void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
422   if (CpuHasAVXorAVX2FeatureFlag()) {
423     vmovaps(dst, src);
424     return;
425   }
426   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
427   EmitUint8(0x0F);
428   EmitUint8(0x28);
429   EmitXmmRegisterOperand(dst, src);
430 }
431 
432 /**VEX.128.0F.WIG 28 /r VMOVAPS xmm1, xmm2*/
vmovaps(XmmRegister dst,XmmRegister src)433 void X86Assembler::vmovaps(XmmRegister dst, XmmRegister src) {
434   DCHECK(CpuHasAVXorAVX2FeatureFlag());
435   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
436   /**Instruction VEX Prefix*/
437   uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
438   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
439   /**a REX prefix is necessary only if an instruction references one of the
440   extended registers or uses a 64-bit operand.*/
441   uint8_t byte_one = EmitVexPrefixByteOne(/*R=*/ false,
442                                           vvvv_reg,
443                                           SET_VEX_L_128,
444                                           SET_VEX_PP_NONE);
445   EmitUint8(byte_zero);
446   EmitUint8(byte_one);
447   /**Instruction Opcode*/
448   EmitUint8(0x28);
449   /**Instruction Operands*/
450   EmitXmmRegisterOperand(dst, src);
451 }
452 
movaps(XmmRegister dst,const Address & src)453 void X86Assembler::movaps(XmmRegister dst, const Address& src) {
454   if (CpuHasAVXorAVX2FeatureFlag()) {
455     vmovaps(dst, src);
456     return;
457   }
458   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459   EmitUint8(0x0F);
460   EmitUint8(0x28);
461   EmitOperand(dst, src);
462 }
463 
464 /**VEX.128.0F.WIG 28 /r VMOVAPS xmm1, m128*/
vmovaps(XmmRegister dst,const Address & src)465 void X86Assembler::vmovaps(XmmRegister dst, const Address& src) {
466   DCHECK(CpuHasAVXorAVX2FeatureFlag());
467   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468   /**Instruction VEX Prefix*/
469   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
470   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
471   /**a REX prefix is necessary only if an instruction references one of the
472   extended registers or uses a 64-bit operand.*/
473   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
474                                          vvvv_reg,
475                                          SET_VEX_L_128,
476                                          SET_VEX_PP_NONE);
477   EmitUint8(ByteZero);
478   EmitUint8(ByteOne);
479   /**Instruction Opcode*/
480   EmitUint8(0x28);
481   /**Instruction Operands*/
482   EmitOperand(dst, src);
483 }
484 
movups(XmmRegister dst,const Address & src)485 void X86Assembler::movups(XmmRegister dst, const Address& src) {
486   if (CpuHasAVXorAVX2FeatureFlag()) {
487     vmovups(dst, src);
488     return;
489   }
490   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
491   EmitUint8(0x0F);
492   EmitUint8(0x10);
493   EmitOperand(dst, src);
494 }
495 
496 /**VEX.128.0F.WIG 10 /r VMOVUPS xmm1, m128*/
vmovups(XmmRegister dst,const Address & src)497 void X86Assembler::vmovups(XmmRegister dst, const Address& src) {
498   DCHECK(CpuHasAVXorAVX2FeatureFlag());
499   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
500   /**Instruction VEX Prefix*/
501   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
502   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
503   /**a REX prefix is necessary only if an instruction references one of the
504   extended registers or uses a 64-bit operand.*/
505   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
506                                          vvvv_reg,
507                                          SET_VEX_L_128,
508                                          SET_VEX_PP_NONE);
509   EmitUint8(ByteZero);
510   EmitUint8(ByteOne);
511   /*Instruction Opcode*/
512   EmitUint8(0x10);
513   /*Instruction Operands*/
514   EmitOperand(dst, src);
515 }
516 
movaps(const Address & dst,XmmRegister src)517 void X86Assembler::movaps(const Address& dst, XmmRegister src) {
518   if (CpuHasAVXorAVX2FeatureFlag()) {
519     vmovaps(dst, src);
520     return;
521   }
522   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
523   EmitUint8(0x0F);
524   EmitUint8(0x29);
525   EmitOperand(src, dst);
526 }
527 
528 /**VEX.128.0F.WIG 29 /r VMOVAPS m128, xmm1*/
vmovaps(const Address & dst,XmmRegister src)529 void X86Assembler::vmovaps(const Address& dst, XmmRegister src) {
530   DCHECK(CpuHasAVXorAVX2FeatureFlag());
531   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
532   /**Instruction VEX Prefix*/
533   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
534   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
535   /**a REX prefix is necessary only if an instruction references one of the
536   extended registers or uses a 64-bit operand.*/
537   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
538                                          vvvv_reg,
539                                          SET_VEX_L_128,
540                                          SET_VEX_PP_NONE);
541   EmitUint8(ByteZero);
542   EmitUint8(ByteOne);
543   /**Instruction Opcode*/
544   EmitUint8(0x29);
545   /**Instruction Operands*/
546   EmitOperand(src, dst);
547 }
548 
movups(const Address & dst,XmmRegister src)549 void X86Assembler::movups(const Address& dst, XmmRegister src) {
550   if (CpuHasAVXorAVX2FeatureFlag()) {
551     vmovups(dst, src);
552     return;
553   }
554   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
555   EmitUint8(0x0F);
556   EmitUint8(0x11);
557   EmitOperand(src, dst);
558 }
559 
560 /**VEX.128.0F.WIG 11 /r VMOVUPS m128, xmm1*/
vmovups(const Address & dst,XmmRegister src)561 void X86Assembler::vmovups(const Address& dst, XmmRegister src) {
562   DCHECK(CpuHasAVXorAVX2FeatureFlag());
563   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
564   /**Instruction VEX Prefix*/
565   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
566   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
567   /**a REX prefix is necessary only if an instruction references one of the
568   extended registers or uses a 64-bit operand.*/
569   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
570                                          vvvv_reg,
571                                          SET_VEX_L_128,
572                                          SET_VEX_PP_NONE);
573   EmitUint8(ByteZero);
574   EmitUint8(ByteOne);
575   // Instruction Opcode
576   EmitUint8(0x11);
577   // Instruction Operands
578   EmitOperand(src, dst);
579 }
580 
581 
movss(XmmRegister dst,const Address & src)582 void X86Assembler::movss(XmmRegister dst, const Address& src) {
583   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
584   EmitUint8(0xF3);
585   EmitUint8(0x0F);
586   EmitUint8(0x10);
587   EmitOperand(dst, src);
588 }
589 
590 
movss(const Address & dst,XmmRegister src)591 void X86Assembler::movss(const Address& dst, XmmRegister src) {
592   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
593   EmitUint8(0xF3);
594   EmitUint8(0x0F);
595   EmitUint8(0x11);
596   EmitOperand(src, dst);
597 }
598 
599 
movss(XmmRegister dst,XmmRegister src)600 void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
601   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
602   EmitUint8(0xF3);
603   EmitUint8(0x0F);
604   EmitUint8(0x11);
605   EmitXmmRegisterOperand(src, dst);
606 }
607 
608 
movd(XmmRegister dst,Register src)609 void X86Assembler::movd(XmmRegister dst, Register src) {
610   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
611   EmitUint8(0x66);
612   EmitUint8(0x0F);
613   EmitUint8(0x6E);
614   EmitOperand(dst, Operand(src));
615 }
616 
617 
movd(Register dst,XmmRegister src)618 void X86Assembler::movd(Register dst, XmmRegister src) {
619   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
620   EmitUint8(0x66);
621   EmitUint8(0x0F);
622   EmitUint8(0x7E);
623   EmitOperand(src, Operand(dst));
624 }
625 
626 
addss(XmmRegister dst,XmmRegister src)627 void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
628   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629   EmitUint8(0xF3);
630   EmitUint8(0x0F);
631   EmitUint8(0x58);
632   EmitXmmRegisterOperand(dst, src);
633 }
634 
635 
addss(XmmRegister dst,const Address & src)636 void X86Assembler::addss(XmmRegister dst, const Address& src) {
637   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638   EmitUint8(0xF3);
639   EmitUint8(0x0F);
640   EmitUint8(0x58);
641   EmitOperand(dst, src);
642 }
643 
644 
subss(XmmRegister dst,XmmRegister src)645 void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
646   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647   EmitUint8(0xF3);
648   EmitUint8(0x0F);
649   EmitUint8(0x5C);
650   EmitXmmRegisterOperand(dst, src);
651 }
652 
653 
subss(XmmRegister dst,const Address & src)654 void X86Assembler::subss(XmmRegister dst, const Address& src) {
655   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656   EmitUint8(0xF3);
657   EmitUint8(0x0F);
658   EmitUint8(0x5C);
659   EmitOperand(dst, src);
660 }
661 
662 
mulss(XmmRegister dst,XmmRegister src)663 void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
664   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
665   EmitUint8(0xF3);
666   EmitUint8(0x0F);
667   EmitUint8(0x59);
668   EmitXmmRegisterOperand(dst, src);
669 }
670 
671 
mulss(XmmRegister dst,const Address & src)672 void X86Assembler::mulss(XmmRegister dst, const Address& src) {
673   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674   EmitUint8(0xF3);
675   EmitUint8(0x0F);
676   EmitUint8(0x59);
677   EmitOperand(dst, src);
678 }
679 
680 
divss(XmmRegister dst,XmmRegister src)681 void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
682   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
683   EmitUint8(0xF3);
684   EmitUint8(0x0F);
685   EmitUint8(0x5E);
686   EmitXmmRegisterOperand(dst, src);
687 }
688 
689 
divss(XmmRegister dst,const Address & src)690 void X86Assembler::divss(XmmRegister dst, const Address& src) {
691   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
692   EmitUint8(0xF3);
693   EmitUint8(0x0F);
694   EmitUint8(0x5E);
695   EmitOperand(dst, src);
696 }
697 
698 
addps(XmmRegister dst,XmmRegister src)699 void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
700   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
701   EmitUint8(0x0F);
702   EmitUint8(0x58);
703   EmitXmmRegisterOperand(dst, src);
704 }
705 
vaddps(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)706 void X86Assembler::vaddps(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
707   DCHECK(CpuHasAVXorAVX2FeatureFlag());
708   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
709   uint8_t ByteZero = 0x00, ByteOne = 0x00;
710   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
711   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
712                                  X86ManagedRegister::FromXmmRegister(add_left),
713                                  SET_VEX_L_128,
714                                  SET_VEX_PP_NONE);
715   EmitUint8(ByteZero);
716   EmitUint8(ByteOne);
717   EmitUint8(0x58);
718   EmitXmmRegisterOperand(dst, add_right);
719 }
720 
subps(XmmRegister dst,XmmRegister src)721 void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
722   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
723   EmitUint8(0x0F);
724   EmitUint8(0x5C);
725   EmitXmmRegisterOperand(dst, src);
726 }
727 
vsubps(XmmRegister dst,XmmRegister src1,XmmRegister src2)728 void X86Assembler::vsubps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
729   DCHECK(CpuHasAVXorAVX2FeatureFlag());
730   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
731   uint8_t byte_zero = 0x00, byte_one = 0x00;
732   byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
733   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(src1);
734   byte_one = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_NONE);
735   EmitUint8(byte_zero);
736   EmitUint8(byte_one);
737   EmitUint8(0x5C);
738   EmitXmmRegisterOperand(dst, src2);
739 }
740 
mulps(XmmRegister dst,XmmRegister src)741 void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
742   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
743   EmitUint8(0x0F);
744   EmitUint8(0x59);
745   EmitXmmRegisterOperand(dst, src);
746 }
747 
vmulps(XmmRegister dst,XmmRegister src1,XmmRegister src2)748 void X86Assembler::vmulps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
749   DCHECK(CpuHasAVXorAVX2FeatureFlag());
750   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
751   uint8_t ByteZero = 0x00, ByteOne = 0x00;
752   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
753   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
754                                  X86ManagedRegister::FromXmmRegister(src1),
755                                  SET_VEX_L_128,
756                                  SET_VEX_PP_NONE);
757   EmitUint8(ByteZero);
758   EmitUint8(ByteOne);
759   EmitUint8(0x59);
760   EmitXmmRegisterOperand(dst, src2);
761 }
762 
divps(XmmRegister dst,XmmRegister src)763 void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
764   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
765   EmitUint8(0x0F);
766   EmitUint8(0x5E);
767   EmitXmmRegisterOperand(dst, src);
768 }
769 
770 
vdivps(XmmRegister dst,XmmRegister src1,XmmRegister src2)771 void X86Assembler::vdivps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
772   DCHECK(CpuHasAVXorAVX2FeatureFlag());
773   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
774   uint8_t ByteZero = 0x00, ByteOne = 0x00;
775   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
776   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
777                                  X86ManagedRegister::FromXmmRegister(src1),
778                                  SET_VEX_L_128,
779                                  SET_VEX_PP_NONE);
780   EmitUint8(ByteZero);
781   EmitUint8(ByteOne);
782   EmitUint8(0x5E);
783   EmitXmmRegisterOperand(dst, src2);
784 }
785 
786 
movapd(XmmRegister dst,XmmRegister src)787 void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
788   if (CpuHasAVXorAVX2FeatureFlag()) {
789     vmovapd(dst, src);
790     return;
791   }
792   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
793   EmitUint8(0x66);
794   EmitUint8(0x0F);
795   EmitUint8(0x28);
796   EmitXmmRegisterOperand(dst, src);
797 }
798 
799 /**VEX.128.66.0F.WIG 28 /r VMOVAPD xmm1, xmm2*/
vmovapd(XmmRegister dst,XmmRegister src)800 void X86Assembler::vmovapd(XmmRegister dst, XmmRegister src) {
801   DCHECK(CpuHasAVXorAVX2FeatureFlag());
802   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
803   /**Instruction VEX Prefix*/
804   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
805   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
806   /**a REX prefix is necessary only if an instruction references one of the
807   extended registers or uses a 64-bit operand.*/
808   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
809                                          vvvv_reg ,
810                                          SET_VEX_L_128,
811                                          SET_VEX_PP_66);
812   EmitUint8(ByteZero);
813   EmitUint8(ByteOne);
814   // Instruction Opcode
815   EmitUint8(0x28);
816   // Instruction Operands
817   EmitXmmRegisterOperand(dst, src);
818 }
819 
movapd(XmmRegister dst,const Address & src)820 void X86Assembler::movapd(XmmRegister dst, const Address& src) {
821   if (CpuHasAVXorAVX2FeatureFlag()) {
822     vmovapd(dst, src);
823     return;
824   }
825   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
826   EmitUint8(0x66);
827   EmitUint8(0x0F);
828   EmitUint8(0x28);
829   EmitOperand(dst, src);
830 }
831 
832 /**VEX.128.66.0F.WIG 28 /r VMOVAPD xmm1, m128*/
vmovapd(XmmRegister dst,const Address & src)833 void X86Assembler::vmovapd(XmmRegister dst, const Address& src) {
834   DCHECK(CpuHasAVXorAVX2FeatureFlag());
835   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
836   /**Instruction VEX Prefix*/
837   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
838   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
839   /**a REX prefix is necessary only if an instruction references one of the
840   extended registers or uses a 64-bit operand.*/
841   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
842                                          vvvv_reg,
843                                          SET_VEX_L_128,
844                                          SET_VEX_PP_66);
845   EmitUint8(ByteZero);
846   EmitUint8(ByteOne);
847   // Instruction Opcode
848   EmitUint8(0x28);
849   // Instruction Operands
850   EmitOperand(dst, src);
851 }
852 
movupd(XmmRegister dst,const Address & src)853 void X86Assembler::movupd(XmmRegister dst, const Address& src) {
854   if (CpuHasAVXorAVX2FeatureFlag()) {
855     vmovupd(dst, src);
856     return;
857   }
858   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
859   EmitUint8(0x66);
860   EmitUint8(0x0F);
861   EmitUint8(0x10);
862   EmitOperand(dst, src);
863 }
864 
865 /**VEX.128.66.0F.WIG 10 /r VMOVUPD xmm1, m128*/
vmovupd(XmmRegister dst,const Address & src)866 void X86Assembler::vmovupd(XmmRegister dst, const Address& src) {
867   DCHECK(CpuHasAVXorAVX2FeatureFlag());
868   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
869   /**Instruction VEX Prefix*/
870   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
871   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
872   /**a REX prefix is necessary only if an instruction references one of the
873   extended registers or uses a 64-bit operand.*/
874   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
875                                          vvvv_reg,
876                                          SET_VEX_L_128,
877                                          SET_VEX_PP_66);
878   EmitUint8(ByteZero);
879   EmitUint8(ByteOne);
880   // Instruction Opcode
881   EmitUint8(0x10);
882   // Instruction Operands
883   EmitOperand(dst, src);
884 }
885 
886 
movapd(const Address & dst,XmmRegister src)887 void X86Assembler::movapd(const Address& dst, XmmRegister src) {
888   if (CpuHasAVXorAVX2FeatureFlag()) {
889     vmovapd(dst, src);
890     return;
891   }
892   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
893   EmitUint8(0x66);
894   EmitUint8(0x0F);
895   EmitUint8(0x29);
896   EmitOperand(src, dst);
897 }
898 
899 /**VEX.128.66.0F.WIG 29 /r VMOVAPD m128, xmm1 */
vmovapd(const Address & dst,XmmRegister src)900 void X86Assembler::vmovapd(const Address& dst, XmmRegister src) {
901   DCHECK(CpuHasAVXorAVX2FeatureFlag());
902   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
903   /**Instruction VEX Prefix */
904   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
905   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
906   /**a REX prefix is necessary only if an instruction references one of the
907   extended registers or uses a 64-bit operand.*/
908   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
909                                          vvvv_reg,
910                                          SET_VEX_L_128,
911                                          SET_VEX_PP_66);
912   EmitUint8(ByteZero);
913   EmitUint8(ByteOne);
914   // Instruction Opcode
915   EmitUint8(0x29);
916   // Instruction Operands
917   EmitOperand(src, dst);
918 }
919 
movupd(const Address & dst,XmmRegister src)920 void X86Assembler::movupd(const Address& dst, XmmRegister src) {
921   if (CpuHasAVXorAVX2FeatureFlag()) {
922     vmovupd(dst, src);
923     return;
924   }
925   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
926   EmitUint8(0x66);
927   EmitUint8(0x0F);
928   EmitUint8(0x11);
929   EmitOperand(src, dst);
930 }
931 
932 /**VEX.128.66.0F.WIG 11 /r VMOVUPD m128, xmm1 */
vmovupd(const Address & dst,XmmRegister src)933 void X86Assembler::vmovupd(const Address& dst, XmmRegister src) {
934   DCHECK(CpuHasAVXorAVX2FeatureFlag());
935   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
936   /**Instruction VEX Prefix */
937   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
938   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
939   /**a REX prefix is necessary only if an instruction references one of the
940   extended registers or uses a 64-bit operand.**/
941   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
942                                          vvvv_reg,
943                                          SET_VEX_L_128,
944                                          SET_VEX_PP_66);
945   EmitUint8(ByteZero);
946   EmitUint8(ByteOne);
947   // Instruction Opcode
948   EmitUint8(0x11);
949   // Instruction Operands
950   EmitOperand(src, dst);
951 }
952 
flds(const Address & src)953 void X86Assembler::flds(const Address& src) {
954   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
955   EmitUint8(0xD9);
956   EmitOperand(0, src);
957 }
958 
959 
fsts(const Address & dst)960 void X86Assembler::fsts(const Address& dst) {
961   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
962   EmitUint8(0xD9);
963   EmitOperand(2, dst);
964 }
965 
966 
fstps(const Address & dst)967 void X86Assembler::fstps(const Address& dst) {
968   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
969   EmitUint8(0xD9);
970   EmitOperand(3, dst);
971 }
972 
973 
movsd(XmmRegister dst,const Address & src)974 void X86Assembler::movsd(XmmRegister dst, const Address& src) {
975   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
976   EmitUint8(0xF2);
977   EmitUint8(0x0F);
978   EmitUint8(0x10);
979   EmitOperand(dst, src);
980 }
981 
982 
movsd(const Address & dst,XmmRegister src)983 void X86Assembler::movsd(const Address& dst, XmmRegister src) {
984   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
985   EmitUint8(0xF2);
986   EmitUint8(0x0F);
987   EmitUint8(0x11);
988   EmitOperand(src, dst);
989 }
990 
991 
movsd(XmmRegister dst,XmmRegister src)992 void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
993   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
994   EmitUint8(0xF2);
995   EmitUint8(0x0F);
996   EmitUint8(0x11);
997   EmitXmmRegisterOperand(src, dst);
998 }
999 
1000 
movhpd(XmmRegister dst,const Address & src)1001 void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
1002   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1003   EmitUint8(0x66);
1004   EmitUint8(0x0F);
1005   EmitUint8(0x16);
1006   EmitOperand(dst, src);
1007 }
1008 
1009 
movhpd(const Address & dst,XmmRegister src)1010 void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
1011   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1012   EmitUint8(0x66);
1013   EmitUint8(0x0F);
1014   EmitUint8(0x17);
1015   EmitOperand(src, dst);
1016 }
1017 
1018 
addsd(XmmRegister dst,XmmRegister src)1019 void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
1020   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1021   EmitUint8(0xF2);
1022   EmitUint8(0x0F);
1023   EmitUint8(0x58);
1024   EmitXmmRegisterOperand(dst, src);
1025 }
1026 
1027 
addsd(XmmRegister dst,const Address & src)1028 void X86Assembler::addsd(XmmRegister dst, const Address& src) {
1029   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1030   EmitUint8(0xF2);
1031   EmitUint8(0x0F);
1032   EmitUint8(0x58);
1033   EmitOperand(dst, src);
1034 }
1035 
1036 
subsd(XmmRegister dst,XmmRegister src)1037 void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
1038   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1039   EmitUint8(0xF2);
1040   EmitUint8(0x0F);
1041   EmitUint8(0x5C);
1042   EmitXmmRegisterOperand(dst, src);
1043 }
1044 
1045 
subsd(XmmRegister dst,const Address & src)1046 void X86Assembler::subsd(XmmRegister dst, const Address& src) {
1047   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1048   EmitUint8(0xF2);
1049   EmitUint8(0x0F);
1050   EmitUint8(0x5C);
1051   EmitOperand(dst, src);
1052 }
1053 
1054 
mulsd(XmmRegister dst,XmmRegister src)1055 void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
1056   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1057   EmitUint8(0xF2);
1058   EmitUint8(0x0F);
1059   EmitUint8(0x59);
1060   EmitXmmRegisterOperand(dst, src);
1061 }
1062 
1063 
mulsd(XmmRegister dst,const Address & src)1064 void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
1065   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1066   EmitUint8(0xF2);
1067   EmitUint8(0x0F);
1068   EmitUint8(0x59);
1069   EmitOperand(dst, src);
1070 }
1071 
1072 
divsd(XmmRegister dst,XmmRegister src)1073 void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
1074   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1075   EmitUint8(0xF2);
1076   EmitUint8(0x0F);
1077   EmitUint8(0x5E);
1078   EmitXmmRegisterOperand(dst, src);
1079 }
1080 
1081 
divsd(XmmRegister dst,const Address & src)1082 void X86Assembler::divsd(XmmRegister dst, const Address& src) {
1083   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1084   EmitUint8(0xF2);
1085   EmitUint8(0x0F);
1086   EmitUint8(0x5E);
1087   EmitOperand(dst, src);
1088 }
1089 
1090 
addpd(XmmRegister dst,XmmRegister src)1091 void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
1092   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1093   EmitUint8(0x66);
1094   EmitUint8(0x0F);
1095   EmitUint8(0x58);
1096   EmitXmmRegisterOperand(dst, src);
1097 }
1098 
1099 
vaddpd(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1100 void X86Assembler::vaddpd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1101   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1102   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1103   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1104   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1105                                  X86ManagedRegister::FromXmmRegister(add_left),
1106                                  SET_VEX_L_128,
1107                                  SET_VEX_PP_66);
1108   EmitUint8(ByteZero);
1109   EmitUint8(ByteOne);
1110   EmitUint8(0x58);
1111   EmitXmmRegisterOperand(dst, add_right);
1112 }
1113 
1114 
subpd(XmmRegister dst,XmmRegister src)1115 void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
1116   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1117   EmitUint8(0x66);
1118   EmitUint8(0x0F);
1119   EmitUint8(0x5C);
1120   EmitXmmRegisterOperand(dst, src);
1121 }
1122 
1123 
vsubpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)1124 void X86Assembler::vsubpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1125   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1126   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1127   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form*/ true);
1128   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1129                                  X86ManagedRegister::FromXmmRegister(src1),
1130                                  SET_VEX_L_128,
1131                                  SET_VEX_PP_66);
1132   EmitUint8(ByteZero);
1133   EmitUint8(ByteOne);
1134   EmitUint8(0x5C);
1135   EmitXmmRegisterOperand(dst, src2);
1136 }
1137 
mulpd(XmmRegister dst,XmmRegister src)1138 void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
1139   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1140   EmitUint8(0x66);
1141   EmitUint8(0x0F);
1142   EmitUint8(0x59);
1143   EmitXmmRegisterOperand(dst, src);
1144 }
1145 
vmulpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)1146 void X86Assembler::vmulpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1147   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1148   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1149   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1150   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1151   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1152                                  X86ManagedRegister::FromXmmRegister(src1),
1153                                  SET_VEX_L_128,
1154                                  SET_VEX_PP_66);
1155   EmitUint8(ByteZero);
1156   EmitUint8(ByteOne);
1157   EmitUint8(0x59);
1158   EmitXmmRegisterOperand(dst, src2);
1159 }
1160 
divpd(XmmRegister dst,XmmRegister src)1161 void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
1162   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1163   EmitUint8(0x66);
1164   EmitUint8(0x0F);
1165   EmitUint8(0x5E);
1166   EmitXmmRegisterOperand(dst, src);
1167 }
1168 
vdivpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)1169 void X86Assembler::vdivpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1170   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1171   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1172   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1173   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1174   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1175                                  X86ManagedRegister::FromXmmRegister(src1),
1176                                  SET_VEX_L_128,
1177                                  SET_VEX_PP_66);
1178   EmitUint8(ByteZero);
1179   EmitUint8(ByteOne);
1180   EmitUint8(0x5E);
1181   EmitXmmRegisterOperand(dst, src2);
1182 }
1183 
movdqa(XmmRegister dst,XmmRegister src)1184 void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
1185   if (CpuHasAVXorAVX2FeatureFlag()) {
1186     vmovdqa(dst, src);
1187     return;
1188   }
1189   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1190   EmitUint8(0x66);
1191   EmitUint8(0x0F);
1192   EmitUint8(0x6F);
1193   EmitXmmRegisterOperand(dst, src);
1194 }
1195 
1196 /**VEX.128.66.0F.WIG 6F /r VMOVDQA xmm1, xmm2 */
vmovdqa(XmmRegister dst,XmmRegister src)1197 void X86Assembler::vmovdqa(XmmRegister dst, XmmRegister src) {
1198   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1199   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1200   /**Instruction VEX Prefix */
1201   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1202   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1203   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1204                                          vvvv_reg,
1205                                          SET_VEX_L_128,
1206                                          SET_VEX_PP_66);
1207   EmitUint8(ByteZero);
1208   EmitUint8(ByteOne);
1209   // Instruction Opcode
1210   EmitUint8(0x6F);
1211   // Instruction Operands
1212   EmitXmmRegisterOperand(dst, src);
1213 }
1214 
movdqa(XmmRegister dst,const Address & src)1215 void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
1216   if (CpuHasAVXorAVX2FeatureFlag()) {
1217     vmovdqa(dst, src);
1218     return;
1219   }
1220   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1221   EmitUint8(0x66);
1222   EmitUint8(0x0F);
1223   EmitUint8(0x6F);
1224   EmitOperand(dst, src);
1225 }
1226 
1227 /**VEX.128.66.0F.WIG 6F /r VMOVDQA xmm1, m128 */
vmovdqa(XmmRegister dst,const Address & src)1228 void X86Assembler::vmovdqa(XmmRegister dst, const Address& src) {
1229   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1230   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1231   /**Instruction VEX Prefix */
1232   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1233   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1234   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1235                                          vvvv_reg,
1236                                          SET_VEX_L_128,
1237                                          SET_VEX_PP_66);
1238   EmitUint8(ByteZero);
1239   EmitUint8(ByteOne);
1240   // Instruction Opcode
1241   EmitUint8(0x6F);
1242   // Instruction Operands
1243   EmitOperand(dst, src);
1244 }
1245 
movdqu(XmmRegister dst,const Address & src)1246 void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
1247   if (CpuHasAVXorAVX2FeatureFlag()) {
1248     vmovdqu(dst, src);
1249     return;
1250   }
1251   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1252   EmitUint8(0xF3);
1253   EmitUint8(0x0F);
1254   EmitUint8(0x6F);
1255   EmitOperand(dst, src);
1256 }
1257 
1258 /**VEX.128.F3.0F.WIG 6F /r VMOVDQU xmm1, m128 */
vmovdqu(XmmRegister dst,const Address & src)1259 void X86Assembler::vmovdqu(XmmRegister dst, const Address& src) {
1260   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1261   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1262   /**Instruction VEX Prefix */
1263   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1264   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1265   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1266                                          vvvv_reg,
1267                                          SET_VEX_L_128,
1268                                          SET_VEX_PP_F3);
1269   EmitUint8(ByteZero);
1270   EmitUint8(ByteOne);
1271   // Instruction Opcode
1272   EmitUint8(0x6F);
1273   // Instruction Operands
1274   EmitOperand(dst, src);
1275 }
1276 
movdqa(const Address & dst,XmmRegister src)1277 void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
1278   if (CpuHasAVXorAVX2FeatureFlag()) {
1279     vmovdqa(dst, src);
1280     return;
1281   }
1282   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1283   EmitUint8(0x66);
1284   EmitUint8(0x0F);
1285   EmitUint8(0x7F);
1286   EmitOperand(src, dst);
1287 }
1288 
1289 /**VEX.128.66.0F.WIG 7F /r VMOVDQA m128, xmm1 */
vmovdqa(const Address & dst,XmmRegister src)1290 void X86Assembler::vmovdqa(const Address& dst, XmmRegister src) {
1291   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1292   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1293   /**Instruction VEX Prefix */
1294   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1295   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1296   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1297                                          vvvv_reg,
1298                                          SET_VEX_L_128,
1299                                          SET_VEX_PP_66);
1300   EmitUint8(ByteZero);
1301   EmitUint8(ByteOne);
1302   // Instruction Opcode
1303   EmitUint8(0x7F);
1304   // Instruction Operands
1305   EmitOperand(src, dst);
1306 }
1307 
1308 
movdqu(const Address & dst,XmmRegister src)1309 void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
1310   if (CpuHasAVXorAVX2FeatureFlag()) {
1311     vmovdqu(dst, src);
1312     return;
1313   }
1314   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1315   EmitUint8(0xF3);
1316   EmitUint8(0x0F);
1317   EmitUint8(0x7F);
1318   EmitOperand(src, dst);
1319 }
1320 
1321 /**VEX.128.F3.0F.WIG 7F /r VMOVDQU m128, xmm1 */
vmovdqu(const Address & dst,XmmRegister src)1322 void X86Assembler::vmovdqu(const Address& dst, XmmRegister src) {
1323   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1324   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1325   // Instruction VEX Prefix
1326   uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1327   X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1328   uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1329                                          vvvv_reg,
1330                                          SET_VEX_L_128,
1331                                          SET_VEX_PP_F3);
1332   EmitUint8(ByteZero);
1333   EmitUint8(ByteOne);
1334   // Instruction Opcode
1335   EmitUint8(0x7F);
1336   // Instruction Operands
1337   EmitOperand(src, dst);
1338 }
1339 
paddb(XmmRegister dst,XmmRegister src)1340 void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
1341   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1342   EmitUint8(0x66);
1343   EmitUint8(0x0F);
1344   EmitUint8(0xFC);
1345   EmitXmmRegisterOperand(dst, src);
1346 }
1347 
vpaddb(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1348 void X86Assembler::vpaddb(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1349   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1350   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1351   uint8_t ByteOne = 0x00, ByteZero = 0x00;
1352   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1353   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1354   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1355   EmitUint8(ByteZero);
1356   EmitUint8(ByteOne);
1357   EmitUint8(0xFC);
1358   EmitXmmRegisterOperand(dst, add_right);
1359 }
1360 
psubb(XmmRegister dst,XmmRegister src)1361 void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
1362   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1363   EmitUint8(0x66);
1364   EmitUint8(0x0F);
1365   EmitUint8(0xF8);
1366   EmitXmmRegisterOperand(dst, src);
1367 }
1368 
vpsubb(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1369 void X86Assembler::vpsubb(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1370   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1371   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1372   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1373   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1374   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1375   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1376   EmitUint8(ByteZero);
1377   EmitUint8(ByteOne);
1378   EmitUint8(0xF8);
1379   EmitXmmRegisterOperand(dst, add_right);
1380 }
1381 
paddw(XmmRegister dst,XmmRegister src)1382 void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
1383   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1384   EmitUint8(0x66);
1385   EmitUint8(0x0F);
1386   EmitUint8(0xFD);
1387   EmitXmmRegisterOperand(dst, src);
1388 }
1389 
vpaddw(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1390 void X86Assembler::vpaddw(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1391   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1392   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1393   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1394   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1395   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1396   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1397   EmitUint8(ByteZero);
1398   EmitUint8(ByteOne);
1399   EmitUint8(0xFD);
1400   EmitXmmRegisterOperand(dst, add_right);
1401 }
1402 
psubw(XmmRegister dst,XmmRegister src)1403 void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
1404   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1405   EmitUint8(0x66);
1406   EmitUint8(0x0F);
1407   EmitUint8(0xF9);
1408   EmitXmmRegisterOperand(dst, src);
1409 }
1410 
vpsubw(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1411 void X86Assembler::vpsubw(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1412   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1413   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1414   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1415   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1416   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1417   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1418   EmitUint8(ByteZero);
1419   EmitUint8(ByteOne);
1420   EmitUint8(0xF9);
1421   EmitXmmRegisterOperand(dst, add_right);
1422 }
1423 
pmullw(XmmRegister dst,XmmRegister src)1424 void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
1425   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1426   EmitUint8(0x66);
1427   EmitUint8(0x0F);
1428   EmitUint8(0xD5);
1429   EmitXmmRegisterOperand(dst, src);
1430 }
1431 
1432 
paddd(XmmRegister dst,XmmRegister src)1433 void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
1434   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1435   EmitUint8(0x66);
1436   EmitUint8(0x0F);
1437   EmitUint8(0xFE);
1438   EmitXmmRegisterOperand(dst, src);
1439 }
1440 
vpaddd(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1441 void X86Assembler::vpaddd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1442   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1443   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1444   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1445   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1446   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1447   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1448   EmitUint8(ByteZero);
1449   EmitUint8(ByteOne);
1450   EmitUint8(0xFE);
1451   EmitXmmRegisterOperand(dst, add_right);
1452 }
1453 
psubd(XmmRegister dst,XmmRegister src)1454 void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
1455   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1456   EmitUint8(0x66);
1457   EmitUint8(0x0F);
1458   EmitUint8(0xFA);
1459   EmitXmmRegisterOperand(dst, src);
1460 }
1461 
1462 
vpsubd(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1463 void X86Assembler::vpsubd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1464   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1465   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1466   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1467   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1468   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1469   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1470   EmitUint8(ByteZero);
1471   EmitUint8(ByteOne);
1472   EmitUint8(0xFA);
1473   EmitXmmRegisterOperand(dst, add_right);
1474 }
1475 
1476 
pmulld(XmmRegister dst,XmmRegister src)1477 void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
1478   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1479   EmitUint8(0x66);
1480   EmitUint8(0x0F);
1481   EmitUint8(0x38);
1482   EmitUint8(0x40);
1483   EmitXmmRegisterOperand(dst, src);
1484 }
1485 
vpmulld(XmmRegister dst,XmmRegister src1,XmmRegister src2)1486 void X86Assembler::vpmulld(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1487   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1488   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1489   uint8_t ByteZero = 0x00, ByteOne = 0x00, ByteTwo = 0x00;
1490   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
1491   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1492                                  /*X=*/ false,
1493                                  /*B=*/ false,
1494                                  SET_VEX_M_0F_38);
1495   ByteTwo = EmitVexPrefixByteTwo(/*W=*/ false,
1496                                  X86ManagedRegister::FromXmmRegister(src1),
1497                                  SET_VEX_L_128,
1498                                  SET_VEX_PP_66);
1499   EmitUint8(ByteZero);
1500   EmitUint8(ByteOne);
1501   EmitUint8(ByteTwo);
1502   EmitUint8(0x40);
1503   EmitRegisterOperand(dst, src2);
1504 }
1505 
vpmullw(XmmRegister dst,XmmRegister src1,XmmRegister src2)1506 void X86Assembler::vpmullw(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1507   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1508   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1509   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1510   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1511   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1512                                  X86ManagedRegister::FromXmmRegister(src1),
1513                                  SET_VEX_L_128,
1514                                  SET_VEX_PP_66);
1515   EmitUint8(ByteZero);
1516   EmitUint8(ByteOne);
1517   EmitUint8(0xD5);
1518   EmitRegisterOperand(dst, src2);
1519 }
1520 
paddq(XmmRegister dst,XmmRegister src)1521 void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
1522   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1523   EmitUint8(0x66);
1524   EmitUint8(0x0F);
1525   EmitUint8(0xD4);
1526   EmitXmmRegisterOperand(dst, src);
1527 }
1528 
vpaddq(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1529 void X86Assembler::vpaddq(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1530   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1531   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1532   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1533   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1534   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1535   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1536   EmitUint8(ByteZero);
1537   EmitUint8(ByteOne);
1538   EmitUint8(0xD4);
1539   EmitXmmRegisterOperand(dst, add_right);
1540 }
1541 
1542 
psubq(XmmRegister dst,XmmRegister src)1543 void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
1544   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1545   EmitUint8(0x66);
1546   EmitUint8(0x0F);
1547   EmitUint8(0xFB);
1548   EmitXmmRegisterOperand(dst, src);
1549 }
1550 
vpsubq(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1551 void X86Assembler::vpsubq(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1552   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1553   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1554   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1555   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1556   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1557   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1558   EmitUint8(ByteZero);
1559   EmitUint8(ByteOne);
1560   EmitUint8(0xFB);
1561   EmitXmmRegisterOperand(dst, add_right);
1562 }
1563 
paddusb(XmmRegister dst,XmmRegister src)1564 void X86Assembler::paddusb(XmmRegister dst, XmmRegister src) {
1565   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1566   EmitUint8(0x66);
1567   EmitUint8(0x0F);
1568   EmitUint8(0xDC);
1569   EmitXmmRegisterOperand(dst, src);
1570 }
1571 
1572 
paddsb(XmmRegister dst,XmmRegister src)1573 void X86Assembler::paddsb(XmmRegister dst, XmmRegister src) {
1574   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1575   EmitUint8(0x66);
1576   EmitUint8(0x0F);
1577   EmitUint8(0xEC);
1578   EmitXmmRegisterOperand(dst, src);
1579 }
1580 
1581 
paddusw(XmmRegister dst,XmmRegister src)1582 void X86Assembler::paddusw(XmmRegister dst, XmmRegister src) {
1583   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1584   EmitUint8(0x66);
1585   EmitUint8(0x0F);
1586   EmitUint8(0xDD);
1587   EmitXmmRegisterOperand(dst, src);
1588 }
1589 
1590 
paddsw(XmmRegister dst,XmmRegister src)1591 void X86Assembler::paddsw(XmmRegister dst, XmmRegister src) {
1592   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1593   EmitUint8(0x66);
1594   EmitUint8(0x0F);
1595   EmitUint8(0xED);
1596   EmitXmmRegisterOperand(dst, src);
1597 }
1598 
1599 
psubusb(XmmRegister dst,XmmRegister src)1600 void X86Assembler::psubusb(XmmRegister dst, XmmRegister src) {
1601   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1602   EmitUint8(0x66);
1603   EmitUint8(0x0F);
1604   EmitUint8(0xD8);
1605   EmitXmmRegisterOperand(dst, src);
1606 }
1607 
1608 
psubsb(XmmRegister dst,XmmRegister src)1609 void X86Assembler::psubsb(XmmRegister dst, XmmRegister src) {
1610   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1611   EmitUint8(0x66);
1612   EmitUint8(0x0F);
1613   EmitUint8(0xE8);
1614   EmitXmmRegisterOperand(dst, src);
1615 }
1616 
1617 
psubusw(XmmRegister dst,XmmRegister src)1618 void X86Assembler::psubusw(XmmRegister dst, XmmRegister src) {
1619   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1620   EmitUint8(0x66);
1621   EmitUint8(0x0F);
1622   EmitUint8(0xD9);
1623   EmitXmmRegisterOperand(dst, src);
1624 }
1625 
1626 
psubsw(XmmRegister dst,XmmRegister src)1627 void X86Assembler::psubsw(XmmRegister dst, XmmRegister src) {
1628   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1629   EmitUint8(0x66);
1630   EmitUint8(0x0F);
1631   EmitUint8(0xE9);
1632   EmitXmmRegisterOperand(dst, src);
1633 }
1634 
1635 
cvtsi2ss(XmmRegister dst,Register src)1636 void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
1637   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1638   EmitUint8(0xF3);
1639   EmitUint8(0x0F);
1640   EmitUint8(0x2A);
1641   EmitOperand(dst, Operand(src));
1642 }
1643 
1644 
cvtsi2sd(XmmRegister dst,Register src)1645 void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
1646   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1647   EmitUint8(0xF2);
1648   EmitUint8(0x0F);
1649   EmitUint8(0x2A);
1650   EmitOperand(dst, Operand(src));
1651 }
1652 
1653 
cvtss2si(Register dst,XmmRegister src)1654 void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
1655   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1656   EmitUint8(0xF3);
1657   EmitUint8(0x0F);
1658   EmitUint8(0x2D);
1659   EmitXmmRegisterOperand(dst, src);
1660 }
1661 
1662 
cvtss2sd(XmmRegister dst,XmmRegister src)1663 void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
1664   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1665   EmitUint8(0xF3);
1666   EmitUint8(0x0F);
1667   EmitUint8(0x5A);
1668   EmitXmmRegisterOperand(dst, src);
1669 }
1670 
1671 
cvtsd2si(Register dst,XmmRegister src)1672 void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
1673   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1674   EmitUint8(0xF2);
1675   EmitUint8(0x0F);
1676   EmitUint8(0x2D);
1677   EmitXmmRegisterOperand(dst, src);
1678 }
1679 
1680 
cvttss2si(Register dst,XmmRegister src)1681 void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
1682   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1683   EmitUint8(0xF3);
1684   EmitUint8(0x0F);
1685   EmitUint8(0x2C);
1686   EmitXmmRegisterOperand(dst, src);
1687 }
1688 
1689 
cvttsd2si(Register dst,XmmRegister src)1690 void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
1691   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1692   EmitUint8(0xF2);
1693   EmitUint8(0x0F);
1694   EmitUint8(0x2C);
1695   EmitXmmRegisterOperand(dst, src);
1696 }
1697 
1698 
cvtsd2ss(XmmRegister dst,XmmRegister src)1699 void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
1700   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1701   EmitUint8(0xF2);
1702   EmitUint8(0x0F);
1703   EmitUint8(0x5A);
1704   EmitXmmRegisterOperand(dst, src);
1705 }
1706 
1707 
cvtdq2ps(XmmRegister dst,XmmRegister src)1708 void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
1709   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1710   EmitUint8(0x0F);
1711   EmitUint8(0x5B);
1712   EmitXmmRegisterOperand(dst, src);
1713 }
1714 
1715 
cvtdq2pd(XmmRegister dst,XmmRegister src)1716 void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
1717   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1718   EmitUint8(0xF3);
1719   EmitUint8(0x0F);
1720   EmitUint8(0xE6);
1721   EmitXmmRegisterOperand(dst, src);
1722 }
1723 
1724 
comiss(XmmRegister a,XmmRegister b)1725 void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
1726   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1727   EmitUint8(0x0F);
1728   EmitUint8(0x2F);
1729   EmitXmmRegisterOperand(a, b);
1730 }
1731 
1732 
comiss(XmmRegister a,const Address & b)1733 void X86Assembler::comiss(XmmRegister a, const Address& b) {
1734   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1735   EmitUint8(0x0F);
1736   EmitUint8(0x2F);
1737   EmitOperand(a, b);
1738 }
1739 
1740 
comisd(XmmRegister a,XmmRegister b)1741 void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
1742   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1743   EmitUint8(0x66);
1744   EmitUint8(0x0F);
1745   EmitUint8(0x2F);
1746   EmitXmmRegisterOperand(a, b);
1747 }
1748 
1749 
comisd(XmmRegister a,const Address & b)1750 void X86Assembler::comisd(XmmRegister a, const Address& b) {
1751   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1752   EmitUint8(0x66);
1753   EmitUint8(0x0F);
1754   EmitUint8(0x2F);
1755   EmitOperand(a, b);
1756 }
1757 
1758 
ucomiss(XmmRegister a,XmmRegister b)1759 void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1760   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1761   EmitUint8(0x0F);
1762   EmitUint8(0x2E);
1763   EmitXmmRegisterOperand(a, b);
1764 }
1765 
1766 
ucomiss(XmmRegister a,const Address & b)1767 void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1768   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1769   EmitUint8(0x0F);
1770   EmitUint8(0x2E);
1771   EmitOperand(a, b);
1772 }
1773 
1774 
ucomisd(XmmRegister a,XmmRegister b)1775 void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1776   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1777   EmitUint8(0x66);
1778   EmitUint8(0x0F);
1779   EmitUint8(0x2E);
1780   EmitXmmRegisterOperand(a, b);
1781 }
1782 
1783 
ucomisd(XmmRegister a,const Address & b)1784 void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1785   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1786   EmitUint8(0x66);
1787   EmitUint8(0x0F);
1788   EmitUint8(0x2E);
1789   EmitOperand(a, b);
1790 }
1791 
1792 
roundsd(XmmRegister dst,XmmRegister src,const Immediate & imm)1793 void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1794   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1795   EmitUint8(0x66);
1796   EmitUint8(0x0F);
1797   EmitUint8(0x3A);
1798   EmitUint8(0x0B);
1799   EmitXmmRegisterOperand(dst, src);
1800   EmitUint8(imm.value());
1801 }
1802 
1803 
roundss(XmmRegister dst,XmmRegister src,const Immediate & imm)1804 void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1805   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1806   EmitUint8(0x66);
1807   EmitUint8(0x0F);
1808   EmitUint8(0x3A);
1809   EmitUint8(0x0A);
1810   EmitXmmRegisterOperand(dst, src);
1811   EmitUint8(imm.value());
1812 }
1813 
1814 
sqrtsd(XmmRegister dst,XmmRegister src)1815 void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
1816   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1817   EmitUint8(0xF2);
1818   EmitUint8(0x0F);
1819   EmitUint8(0x51);
1820   EmitXmmRegisterOperand(dst, src);
1821 }
1822 
1823 
sqrtss(XmmRegister dst,XmmRegister src)1824 void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
1825   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1826   EmitUint8(0xF3);
1827   EmitUint8(0x0F);
1828   EmitUint8(0x51);
1829   EmitXmmRegisterOperand(dst, src);
1830 }
1831 
1832 
xorpd(XmmRegister dst,const Address & src)1833 void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
1834   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1835   EmitUint8(0x66);
1836   EmitUint8(0x0F);
1837   EmitUint8(0x57);
1838   EmitOperand(dst, src);
1839 }
1840 
1841 
xorpd(XmmRegister dst,XmmRegister src)1842 void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
1843   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1844   EmitUint8(0x66);
1845   EmitUint8(0x0F);
1846   EmitUint8(0x57);
1847   EmitXmmRegisterOperand(dst, src);
1848 }
1849 
1850 
xorps(XmmRegister dst,const Address & src)1851 void X86Assembler::xorps(XmmRegister dst, const Address& src) {
1852   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1853   EmitUint8(0x0F);
1854   EmitUint8(0x57);
1855   EmitOperand(dst, src);
1856 }
1857 
1858 
xorps(XmmRegister dst,XmmRegister src)1859 void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1860   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1861   EmitUint8(0x0F);
1862   EmitUint8(0x57);
1863   EmitXmmRegisterOperand(dst, src);
1864 }
1865 
1866 
pxor(XmmRegister dst,XmmRegister src)1867 void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1868   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1869   EmitUint8(0x66);
1870   EmitUint8(0x0F);
1871   EmitUint8(0xEF);
1872   EmitXmmRegisterOperand(dst, src);
1873 }
1874 
1875 /* VEX.128.66.0F.WIG EF /r VPXOR xmm1, xmm2, xmm3/m128 */
vpxor(XmmRegister dst,XmmRegister src1,XmmRegister src2)1876 void X86Assembler::vpxor(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1877   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1878   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1879   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1880   /* Instruction VEX Prefix */
1881   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1882   /* REX prefix is necessary only if an instruction references one of extended
1883   registers or uses a 64-bit operand. */
1884   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1885                                  X86ManagedRegister::FromXmmRegister(src1),
1886                                  SET_VEX_L_128,
1887                                  SET_VEX_PP_66);
1888   EmitUint8(ByteZero);
1889   EmitUint8(ByteOne);
1890   // Instruction Opcode
1891   EmitUint8(0xEF);
1892   // Instruction Operands
1893   EmitXmmRegisterOperand(dst, src2);
1894 }
1895 
1896 /* VEX.128.0F.WIG 57 /r VXORPS xmm1,xmm2, xmm3/m128 */
vxorps(XmmRegister dst,XmmRegister src1,XmmRegister src2)1897 void X86Assembler::vxorps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1898   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1899   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1900   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1901   /* Instruction VEX Prefix */
1902   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1903   /* REX prefix is necessary only if an instruction references one of extended
1904   registers or uses a 64-bit operand. */
1905   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1906                                  X86ManagedRegister::FromXmmRegister(src1),
1907                                  SET_VEX_L_128,
1908                                  SET_VEX_PP_NONE);
1909   EmitUint8(ByteZero);
1910   EmitUint8(ByteOne);
1911   // Instruction Opcode
1912   EmitUint8(0x57);
1913   // Instruction Operands
1914   EmitXmmRegisterOperand(dst, src2);
1915 }
1916 
1917 /* VEX.128.66.0F.WIG 57 /r VXORPD xmm1,xmm2, xmm3/m128 */
vxorpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)1918 void X86Assembler::vxorpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1919   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1920   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1921   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1922   /* Instruction VEX Prefix */
1923   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1924   /* REX prefix is necessary only if an instruction references one of extended
1925   registers or uses a 64-bit operand. */
1926   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1927                                  X86ManagedRegister::FromXmmRegister(src1),
1928                                  SET_VEX_L_128,
1929                                  SET_VEX_PP_66);
1930   EmitUint8(ByteZero);
1931   EmitUint8(ByteOne);
1932   // Instruction Opcode
1933   EmitUint8(0x57);
1934   // Instruction Operands
1935   EmitXmmRegisterOperand(dst, src2);
1936 }
1937 
andpd(XmmRegister dst,XmmRegister src)1938 void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1939   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1940   EmitUint8(0x66);
1941   EmitUint8(0x0F);
1942   EmitUint8(0x54);
1943   EmitXmmRegisterOperand(dst, src);
1944 }
1945 
1946 
andpd(XmmRegister dst,const Address & src)1947 void X86Assembler::andpd(XmmRegister dst, const Address& src) {
1948   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1949   EmitUint8(0x66);
1950   EmitUint8(0x0F);
1951   EmitUint8(0x54);
1952   EmitOperand(dst, src);
1953 }
1954 
1955 
andps(XmmRegister dst,XmmRegister src)1956 void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
1957   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1958   EmitUint8(0x0F);
1959   EmitUint8(0x54);
1960   EmitXmmRegisterOperand(dst, src);
1961 }
1962 
1963 
andps(XmmRegister dst,const Address & src)1964 void X86Assembler::andps(XmmRegister dst, const Address& src) {
1965   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1966   EmitUint8(0x0F);
1967   EmitUint8(0x54);
1968   EmitOperand(dst, src);
1969 }
1970 
1971 
pand(XmmRegister dst,XmmRegister src)1972 void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
1973   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1974   EmitUint8(0x66);
1975   EmitUint8(0x0F);
1976   EmitUint8(0xDB);
1977   EmitXmmRegisterOperand(dst, src);
1978 }
1979 
1980 /* VEX.128.66.0F.WIG DB /r VPAND xmm1, xmm2, xmm3/m128 */
vpand(XmmRegister dst,XmmRegister src1,XmmRegister src2)1981 void X86Assembler::vpand(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1982   DCHECK(CpuHasAVXorAVX2FeatureFlag());
1983   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1984   uint8_t ByteZero = 0x00, ByteOne = 0x00;
1985   /* Instruction VEX Prefix */
1986   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1987   /* REX prefix is necessary only if an instruction references one of extended
1988   registers or uses a 64-bit operand. */
1989   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1990                                  X86ManagedRegister::FromXmmRegister(src1),
1991                                  SET_VEX_L_128,
1992                                  SET_VEX_PP_66);
1993   EmitUint8(ByteZero);
1994   EmitUint8(ByteOne);
1995   // Instruction Opcode
1996   EmitUint8(0xDB);
1997   // Instruction Operands
1998   EmitXmmRegisterOperand(dst, src2);
1999 }
2000 
2001 /* VEX.128.0F 54 /r VANDPS xmm1,xmm2, xmm3/m128 */
vandps(XmmRegister dst,XmmRegister src1,XmmRegister src2)2002 void X86Assembler::vandps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2003   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2004   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2005   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2006   /* Instruction VEX Prefix */
2007   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2008   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2009                                  X86ManagedRegister::FromXmmRegister(src1),
2010                                  SET_VEX_L_128,
2011                                  SET_VEX_PP_NONE);
2012   EmitUint8(ByteZero);
2013   EmitUint8(ByteOne);
2014   // Instruction Opcode
2015   EmitUint8(0x54);
2016   // Instruction Operands
2017   EmitXmmRegisterOperand(dst, src2);
2018 }
2019 
2020 /* VEX.128.66.0F 54 /r VANDPD xmm1, xmm2, xmm3/m128 */
vandpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)2021 void X86Assembler::vandpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2022   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2023   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2024   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2025   /* Instruction VEX Prefix */
2026   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2027   /* REX prefix is necessary only if an instruction references one of extended
2028   registers or uses a 64-bit operand. */
2029   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2030                                  X86ManagedRegister::FromXmmRegister(src1),
2031                                  SET_VEX_L_128,
2032                                  SET_VEX_PP_66);
2033   EmitUint8(ByteZero);
2034   EmitUint8(ByteOne);
2035   // Instruction Opcode
2036   EmitUint8(0x54);
2037   // Instruction Operands
2038   EmitXmmRegisterOperand(dst, src2);
2039 }
2040 
andnpd(XmmRegister dst,XmmRegister src)2041 void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
2042   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2043   EmitUint8(0x66);
2044   EmitUint8(0x0F);
2045   EmitUint8(0x55);
2046   EmitXmmRegisterOperand(dst, src);
2047 }
2048 
2049 
andnps(XmmRegister dst,XmmRegister src)2050 void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
2051   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2052   EmitUint8(0x0F);
2053   EmitUint8(0x55);
2054   EmitXmmRegisterOperand(dst, src);
2055 }
2056 
2057 
pandn(XmmRegister dst,XmmRegister src)2058 void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
2059   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2060   EmitUint8(0x66);
2061   EmitUint8(0x0F);
2062   EmitUint8(0xDF);
2063   EmitXmmRegisterOperand(dst, src);
2064 }
2065 
2066 /* VEX.128.66.0F.WIG DF /r VPANDN xmm1, xmm2, xmm3/m128 */
vpandn(XmmRegister dst,XmmRegister src1,XmmRegister src2)2067 void X86Assembler::vpandn(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2068   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2069   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2070   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2071   /* Instruction VEX Prefix */
2072   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2073   /* REX prefix is necessary only if an instruction references one of extended
2074   registers or uses a 64-bit operand. */
2075   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2076                                  X86ManagedRegister::FromXmmRegister(src1),
2077                                  SET_VEX_L_128,
2078                                  SET_VEX_PP_66);
2079   EmitUint8(ByteZero);
2080   EmitUint8(ByteOne);
2081   // Instruction Opcode
2082   EmitUint8(0xDF);
2083   // Instruction Operands
2084   EmitXmmRegisterOperand(dst, src2);
2085 }
2086 
2087 /* VEX.128.0F 55 /r VANDNPS xmm1, xmm2, xmm3/m128 */
vandnps(XmmRegister dst,XmmRegister src1,XmmRegister src2)2088 void X86Assembler::vandnps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2089   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2090   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2091   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2092   /* Instruction VEX Prefix */
2093   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2094   /* REX prefix is necessary only if an instruction references one of extended
2095   registers or uses a 64-bit operand. */
2096   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2097                                  X86ManagedRegister::FromXmmRegister(src1),
2098                                  SET_VEX_L_128,
2099                                  SET_VEX_PP_NONE);
2100   EmitUint8(ByteZero);
2101   EmitUint8(ByteOne);
2102   // Instruction Opcode
2103   EmitUint8(0x55);
2104   // Instruction Operands
2105   EmitXmmRegisterOperand(dst, src2);
2106 }
2107 
2108 /* VEX.128.66.0F 55 /r VANDNPD xmm1, xmm2, xmm3/m128 */
vandnpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)2109 void X86Assembler::vandnpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2110   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2111   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2112   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2113   /* Instruction VEX Prefix */
2114   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2115   /* REX prefix is necessary only if an instruction references one of extended
2116   registers or uses a 64-bit operand. */
2117   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2118                                  X86ManagedRegister::FromXmmRegister(src1),
2119                                  SET_VEX_L_128,
2120                                  SET_VEX_PP_66);
2121   EmitUint8(ByteZero);
2122   EmitUint8(ByteOne);
2123   // Instruction Opcode
2124   EmitUint8(0x55);
2125   // Instruction Operands
2126   EmitXmmRegisterOperand(dst, src2);
2127 }
2128 
orpd(XmmRegister dst,XmmRegister src)2129 void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
2130   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2131   EmitUint8(0x66);
2132   EmitUint8(0x0F);
2133   EmitUint8(0x56);
2134   EmitXmmRegisterOperand(dst, src);
2135 }
2136 
2137 
orps(XmmRegister dst,XmmRegister src)2138 void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
2139   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2140   EmitUint8(0x0F);
2141   EmitUint8(0x56);
2142   EmitXmmRegisterOperand(dst, src);
2143 }
2144 
andn(Register dst,Register src1,Register src2)2145 void X86Assembler::andn(Register dst, Register src1, Register src2) {
2146   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2147   uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
2148   uint8_t byte_one = EmitVexPrefixByteOne(/*R=*/ false,
2149                                           /*X=*/ false,
2150                                           /*B=*/ false,
2151                                           SET_VEX_M_0F_38);
2152   uint8_t byte_two = EmitVexPrefixByteTwo(/*W=*/ false,
2153                                           X86ManagedRegister::FromCpuRegister(src1),
2154                                           SET_VEX_L_128,
2155                                           SET_VEX_PP_NONE);
2156   EmitUint8(byte_zero);
2157   EmitUint8(byte_one);
2158   EmitUint8(byte_two);
2159   // Opcode field
2160   EmitUint8(0xF2);
2161   EmitRegisterOperand(dst, src2);
2162 }
2163 
por(XmmRegister dst,XmmRegister src)2164 void X86Assembler::por(XmmRegister dst, XmmRegister src) {
2165   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2166   EmitUint8(0x66);
2167   EmitUint8(0x0F);
2168   EmitUint8(0xEB);
2169   EmitXmmRegisterOperand(dst, src);
2170 }
2171 
2172 /* VEX.128.66.0F.WIG EB /r VPOR xmm1, xmm2, xmm3/m128 */
vpor(XmmRegister dst,XmmRegister src1,XmmRegister src2)2173 void X86Assembler::vpor(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2174   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2175   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2176   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2177   /* Instruction VEX Prefix */
2178   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2179   /* REX prefix is necessary only if an instruction references one of extended
2180   registers or uses a 64-bit operand. */
2181   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2182                                  X86ManagedRegister::FromXmmRegister(src1),
2183                                  SET_VEX_L_128,
2184                                  SET_VEX_PP_66);
2185   EmitUint8(ByteZero);
2186   EmitUint8(ByteOne);
2187   // Instruction Opcode
2188   EmitUint8(0xEB);
2189   // Instruction Operands
2190   EmitXmmRegisterOperand(dst, src2);
2191 }
2192 
2193 /* VEX.128.0F 56 /r VORPS xmm1,xmm2, xmm3/m128 */
vorps(XmmRegister dst,XmmRegister src1,XmmRegister src2)2194 void X86Assembler::vorps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2195   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2196   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2197   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2198   /* Instruction VEX Prefix */
2199   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2200   /* REX prefix is necessary only if an instruction references one of extended
2201   registers or uses a 64-bit operand. */
2202   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2203                                  X86ManagedRegister::FromXmmRegister(src1),
2204                                  SET_VEX_L_128,
2205                                  SET_VEX_PP_NONE);
2206   EmitUint8(ByteZero);
2207   EmitUint8(ByteOne);
2208   // Instruction Opcode
2209   EmitUint8(0x56);
2210   // Instruction Operands
2211   EmitXmmRegisterOperand(dst, src2);
2212 }
2213 
2214 /* VEX.128.66.0F 56 /r VORPD xmm1,xmm2, xmm3/m128 */
vorpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)2215 void X86Assembler::vorpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2216   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2217   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2218   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2219   /* Instruction VEX Prefix */
2220   ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2221   /* REX prefix is necessary only if an instruction references one of extended
2222   registers or uses a 64-bit operand. */
2223   ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2224                                  X86ManagedRegister::FromXmmRegister(src1),
2225                                  SET_VEX_L_128,
2226                                  SET_VEX_PP_66);
2227   EmitUint8(ByteZero);
2228   EmitUint8(ByteOne);
2229   // Instruction Opcode
2230   EmitUint8(0x56);
2231   // Instruction Operands
2232   EmitXmmRegisterOperand(dst, src2);
2233 }
2234 
pavgb(XmmRegister dst,XmmRegister src)2235 void X86Assembler::pavgb(XmmRegister dst, XmmRegister src) {
2236   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2237   EmitUint8(0x66);
2238   EmitUint8(0x0F);
2239   EmitUint8(0xE0);
2240   EmitXmmRegisterOperand(dst, src);
2241 }
2242 
2243 
pavgw(XmmRegister dst,XmmRegister src)2244 void X86Assembler::pavgw(XmmRegister dst, XmmRegister src) {
2245   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2246   EmitUint8(0x66);
2247   EmitUint8(0x0F);
2248   EmitUint8(0xE3);
2249   EmitXmmRegisterOperand(dst, src);
2250 }
2251 
2252 
psadbw(XmmRegister dst,XmmRegister src)2253 void X86Assembler::psadbw(XmmRegister dst, XmmRegister src) {
2254   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2255   EmitUint8(0x66);
2256   EmitUint8(0x0F);
2257   EmitUint8(0xF6);
2258   EmitXmmRegisterOperand(dst, src);
2259 }
2260 
2261 
pmaddwd(XmmRegister dst,XmmRegister src)2262 void X86Assembler::pmaddwd(XmmRegister dst, XmmRegister src) {
2263   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2264   EmitUint8(0x66);
2265   EmitUint8(0x0F);
2266   EmitUint8(0xF5);
2267   EmitXmmRegisterOperand(dst, src);
2268 }
2269 
2270 
vpmaddwd(XmmRegister dst,XmmRegister src1,XmmRegister src2)2271 void X86Assembler::vpmaddwd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2272   DCHECK(CpuHasAVXorAVX2FeatureFlag());
2273   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2274   uint8_t ByteZero = 0x00, ByteOne = 0x00;
2275   ByteZero = EmitVexPrefixByteZero(/* is_twobyte_form=*/ true);
2276   X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(src1);
2277   ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
2278   EmitUint8(ByteZero);
2279   EmitUint8(ByteOne);
2280   EmitUint8(0xF5);
2281   EmitXmmRegisterOperand(dst, src2);
2282 }
2283 
2284 
phaddw(XmmRegister dst,XmmRegister src)2285 void X86Assembler::phaddw(XmmRegister dst, XmmRegister src) {
2286   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2287   EmitUint8(0x66);
2288   EmitUint8(0x0F);
2289   EmitUint8(0x38);
2290   EmitUint8(0x01);
2291   EmitXmmRegisterOperand(dst, src);
2292 }
2293 
2294 
phaddd(XmmRegister dst,XmmRegister src)2295 void X86Assembler::phaddd(XmmRegister dst, XmmRegister src) {
2296   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2297   EmitUint8(0x66);
2298   EmitUint8(0x0F);
2299   EmitUint8(0x38);
2300   EmitUint8(0x02);
2301   EmitXmmRegisterOperand(dst, src);
2302 }
2303 
2304 
haddps(XmmRegister dst,XmmRegister src)2305 void X86Assembler::haddps(XmmRegister dst, XmmRegister src) {
2306   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2307   EmitUint8(0xF2);
2308   EmitUint8(0x0F);
2309   EmitUint8(0x7C);
2310   EmitXmmRegisterOperand(dst, src);
2311 }
2312 
2313 
haddpd(XmmRegister dst,XmmRegister src)2314 void X86Assembler::haddpd(XmmRegister dst, XmmRegister src) {
2315   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2316   EmitUint8(0x66);
2317   EmitUint8(0x0F);
2318   EmitUint8(0x7C);
2319   EmitXmmRegisterOperand(dst, src);
2320 }
2321 
2322 
phsubw(XmmRegister dst,XmmRegister src)2323 void X86Assembler::phsubw(XmmRegister dst, XmmRegister src) {
2324   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2325   EmitUint8(0x66);
2326   EmitUint8(0x0F);
2327   EmitUint8(0x38);
2328   EmitUint8(0x05);
2329   EmitXmmRegisterOperand(dst, src);
2330 }
2331 
2332 
phsubd(XmmRegister dst,XmmRegister src)2333 void X86Assembler::phsubd(XmmRegister dst, XmmRegister src) {
2334   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2335   EmitUint8(0x66);
2336   EmitUint8(0x0F);
2337   EmitUint8(0x38);
2338   EmitUint8(0x06);
2339   EmitXmmRegisterOperand(dst, src);
2340 }
2341 
2342 
hsubps(XmmRegister dst,XmmRegister src)2343 void X86Assembler::hsubps(XmmRegister dst, XmmRegister src) {
2344   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2345   EmitUint8(0xF2);
2346   EmitUint8(0x0F);
2347   EmitUint8(0x7D);
2348   EmitXmmRegisterOperand(dst, src);
2349 }
2350 
2351 
hsubpd(XmmRegister dst,XmmRegister src)2352 void X86Assembler::hsubpd(XmmRegister dst, XmmRegister src) {
2353   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2354   EmitUint8(0x66);
2355   EmitUint8(0x0F);
2356   EmitUint8(0x7D);
2357   EmitXmmRegisterOperand(dst, src);
2358 }
2359 
2360 
pminsb(XmmRegister dst,XmmRegister src)2361 void X86Assembler::pminsb(XmmRegister dst, XmmRegister src) {
2362   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2363   EmitUint8(0x66);
2364   EmitUint8(0x0F);
2365   EmitUint8(0x38);
2366   EmitUint8(0x38);
2367   EmitXmmRegisterOperand(dst, src);
2368 }
2369 
pmaxsb(XmmRegister dst,XmmRegister src)2370 void X86Assembler::pmaxsb(XmmRegister dst, XmmRegister src) {
2371   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2372   EmitUint8(0x66);
2373   EmitUint8(0x0F);
2374   EmitUint8(0x38);
2375   EmitUint8(0x3C);
2376   EmitXmmRegisterOperand(dst, src);
2377 }
2378 
pminsw(XmmRegister dst,XmmRegister src)2379 void X86Assembler::pminsw(XmmRegister dst, XmmRegister src) {
2380   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2381   EmitUint8(0x66);
2382   EmitUint8(0x0F);
2383   EmitUint8(0xEA);
2384   EmitXmmRegisterOperand(dst, src);
2385 }
2386 
pmaxsw(XmmRegister dst,XmmRegister src)2387 void X86Assembler::pmaxsw(XmmRegister dst, XmmRegister src) {
2388   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2389   EmitUint8(0x66);
2390   EmitUint8(0x0F);
2391   EmitUint8(0xEE);
2392   EmitXmmRegisterOperand(dst, src);
2393 }
2394 
pminsd(XmmRegister dst,XmmRegister src)2395 void X86Assembler::pminsd(XmmRegister dst, XmmRegister src) {
2396   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2397   EmitUint8(0x66);
2398   EmitUint8(0x0F);
2399   EmitUint8(0x38);
2400   EmitUint8(0x39);
2401   EmitXmmRegisterOperand(dst, src);
2402 }
2403 
pmaxsd(XmmRegister dst,XmmRegister src)2404 void X86Assembler::pmaxsd(XmmRegister dst, XmmRegister src) {
2405   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2406   EmitUint8(0x66);
2407   EmitUint8(0x0F);
2408   EmitUint8(0x38);
2409   EmitUint8(0x3D);
2410   EmitXmmRegisterOperand(dst, src);
2411 }
2412 
pminub(XmmRegister dst,XmmRegister src)2413 void X86Assembler::pminub(XmmRegister dst, XmmRegister src) {
2414   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2415   EmitUint8(0x66);
2416   EmitUint8(0x0F);
2417   EmitUint8(0xDA);
2418   EmitXmmRegisterOperand(dst, src);
2419 }
2420 
pmaxub(XmmRegister dst,XmmRegister src)2421 void X86Assembler::pmaxub(XmmRegister dst, XmmRegister src) {
2422   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2423   EmitUint8(0x66);
2424   EmitUint8(0x0F);
2425   EmitUint8(0xDE);
2426   EmitXmmRegisterOperand(dst, src);
2427 }
2428 
pminuw(XmmRegister dst,XmmRegister src)2429 void X86Assembler::pminuw(XmmRegister dst, XmmRegister src) {
2430   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2431   EmitUint8(0x66);
2432   EmitUint8(0x0F);
2433   EmitUint8(0x38);
2434   EmitUint8(0x3A);
2435   EmitXmmRegisterOperand(dst, src);
2436 }
2437 
pmaxuw(XmmRegister dst,XmmRegister src)2438 void X86Assembler::pmaxuw(XmmRegister dst, XmmRegister src) {
2439   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2440   EmitUint8(0x66);
2441   EmitUint8(0x0F);
2442   EmitUint8(0x38);
2443   EmitUint8(0x3E);
2444   EmitXmmRegisterOperand(dst, src);
2445 }
2446 
pminud(XmmRegister dst,XmmRegister src)2447 void X86Assembler::pminud(XmmRegister dst, XmmRegister src) {
2448   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2449   EmitUint8(0x66);
2450   EmitUint8(0x0F);
2451   EmitUint8(0x38);
2452   EmitUint8(0x3B);
2453   EmitXmmRegisterOperand(dst, src);
2454 }
2455 
pmaxud(XmmRegister dst,XmmRegister src)2456 void X86Assembler::pmaxud(XmmRegister dst, XmmRegister src) {
2457   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2458   EmitUint8(0x66);
2459   EmitUint8(0x0F);
2460   EmitUint8(0x38);
2461   EmitUint8(0x3F);
2462   EmitXmmRegisterOperand(dst, src);
2463 }
2464 
minps(XmmRegister dst,XmmRegister src)2465 void X86Assembler::minps(XmmRegister dst, XmmRegister src) {
2466   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2467   EmitUint8(0x0F);
2468   EmitUint8(0x5D);
2469   EmitXmmRegisterOperand(dst, src);
2470 }
2471 
maxps(XmmRegister dst,XmmRegister src)2472 void X86Assembler::maxps(XmmRegister dst, XmmRegister src) {
2473   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2474   EmitUint8(0x0F);
2475   EmitUint8(0x5F);
2476   EmitXmmRegisterOperand(dst, src);
2477 }
2478 
minpd(XmmRegister dst,XmmRegister src)2479 void X86Assembler::minpd(XmmRegister dst, XmmRegister src) {
2480   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2481   EmitUint8(0x66);
2482   EmitUint8(0x0F);
2483   EmitUint8(0x5D);
2484   EmitXmmRegisterOperand(dst, src);
2485 }
2486 
maxpd(XmmRegister dst,XmmRegister src)2487 void X86Assembler::maxpd(XmmRegister dst, XmmRegister src) {
2488   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2489   EmitUint8(0x66);
2490   EmitUint8(0x0F);
2491   EmitUint8(0x5F);
2492   EmitXmmRegisterOperand(dst, src);
2493 }
2494 
pcmpeqb(XmmRegister dst,XmmRegister src)2495 void X86Assembler::pcmpeqb(XmmRegister dst, XmmRegister src) {
2496   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2497   EmitUint8(0x66);
2498   EmitUint8(0x0F);
2499   EmitUint8(0x74);
2500   EmitXmmRegisterOperand(dst, src);
2501 }
2502 
2503 
pcmpeqw(XmmRegister dst,XmmRegister src)2504 void X86Assembler::pcmpeqw(XmmRegister dst, XmmRegister src) {
2505   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2506   EmitUint8(0x66);
2507   EmitUint8(0x0F);
2508   EmitUint8(0x75);
2509   EmitXmmRegisterOperand(dst, src);
2510 }
2511 
2512 
pcmpeqd(XmmRegister dst,XmmRegister src)2513 void X86Assembler::pcmpeqd(XmmRegister dst, XmmRegister src) {
2514   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2515   EmitUint8(0x66);
2516   EmitUint8(0x0F);
2517   EmitUint8(0x76);
2518   EmitXmmRegisterOperand(dst, src);
2519 }
2520 
2521 
pcmpeqq(XmmRegister dst,XmmRegister src)2522 void X86Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
2523   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2524   EmitUint8(0x66);
2525   EmitUint8(0x0F);
2526   EmitUint8(0x38);
2527   EmitUint8(0x29);
2528   EmitXmmRegisterOperand(dst, src);
2529 }
2530 
2531 
pcmpgtb(XmmRegister dst,XmmRegister src)2532 void X86Assembler::pcmpgtb(XmmRegister dst, XmmRegister src) {
2533   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2534   EmitUint8(0x66);
2535   EmitUint8(0x0F);
2536   EmitUint8(0x64);
2537   EmitXmmRegisterOperand(dst, src);
2538 }
2539 
2540 
pcmpgtw(XmmRegister dst,XmmRegister src)2541 void X86Assembler::pcmpgtw(XmmRegister dst, XmmRegister src) {
2542   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2543   EmitUint8(0x66);
2544   EmitUint8(0x0F);
2545   EmitUint8(0x65);
2546   EmitXmmRegisterOperand(dst, src);
2547 }
2548 
2549 
pcmpgtd(XmmRegister dst,XmmRegister src)2550 void X86Assembler::pcmpgtd(XmmRegister dst, XmmRegister src) {
2551   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2552   EmitUint8(0x66);
2553   EmitUint8(0x0F);
2554   EmitUint8(0x66);
2555   EmitXmmRegisterOperand(dst, src);
2556 }
2557 
2558 
pcmpgtq(XmmRegister dst,XmmRegister src)2559 void X86Assembler::pcmpgtq(XmmRegister dst, XmmRegister src) {
2560   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2561   EmitUint8(0x66);
2562   EmitUint8(0x0F);
2563   EmitUint8(0x38);
2564   EmitUint8(0x37);
2565   EmitXmmRegisterOperand(dst, src);
2566 }
2567 
2568 
shufpd(XmmRegister dst,XmmRegister src,const Immediate & imm)2569 void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
2570   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2571   EmitUint8(0x66);
2572   EmitUint8(0x0F);
2573   EmitUint8(0xC6);
2574   EmitXmmRegisterOperand(dst, src);
2575   EmitUint8(imm.value());
2576 }
2577 
2578 
shufps(XmmRegister dst,XmmRegister src,const Immediate & imm)2579 void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
2580   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2581   EmitUint8(0x0F);
2582   EmitUint8(0xC6);
2583   EmitXmmRegisterOperand(dst, src);
2584   EmitUint8(imm.value());
2585 }
2586 
2587 
pshufd(XmmRegister dst,XmmRegister src,const Immediate & imm)2588 void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
2589   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2590   EmitUint8(0x66);
2591   EmitUint8(0x0F);
2592   EmitUint8(0x70);
2593   EmitXmmRegisterOperand(dst, src);
2594   EmitUint8(imm.value());
2595 }
2596 
2597 
punpcklbw(XmmRegister dst,XmmRegister src)2598 void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
2599   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2600   EmitUint8(0x66);
2601   EmitUint8(0x0F);
2602   EmitUint8(0x60);
2603   EmitXmmRegisterOperand(dst, src);
2604 }
2605 
2606 
punpcklwd(XmmRegister dst,XmmRegister src)2607 void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
2608   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2609   EmitUint8(0x66);
2610   EmitUint8(0x0F);
2611   EmitUint8(0x61);
2612   EmitXmmRegisterOperand(dst, src);
2613 }
2614 
2615 
punpckldq(XmmRegister dst,XmmRegister src)2616 void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
2617   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2618   EmitUint8(0x66);
2619   EmitUint8(0x0F);
2620   EmitUint8(0x62);
2621   EmitXmmRegisterOperand(dst, src);
2622 }
2623 
2624 
punpcklqdq(XmmRegister dst,XmmRegister src)2625 void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
2626   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2627   EmitUint8(0x66);
2628   EmitUint8(0x0F);
2629   EmitUint8(0x6C);
2630   EmitXmmRegisterOperand(dst, src);
2631 }
2632 
2633 
punpckhbw(XmmRegister dst,XmmRegister src)2634 void X86Assembler::punpckhbw(XmmRegister dst, XmmRegister src) {
2635   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2636   EmitUint8(0x66);
2637   EmitUint8(0x0F);
2638   EmitUint8(0x68);
2639   EmitXmmRegisterOperand(dst, src);
2640 }
2641 
2642 
punpckhwd(XmmRegister dst,XmmRegister src)2643 void X86Assembler::punpckhwd(XmmRegister dst, XmmRegister src) {
2644   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2645   EmitUint8(0x66);
2646   EmitUint8(0x0F);
2647   EmitUint8(0x69);
2648   EmitXmmRegisterOperand(dst, src);
2649 }
2650 
2651 
punpckhdq(XmmRegister dst,XmmRegister src)2652 void X86Assembler::punpckhdq(XmmRegister dst, XmmRegister src) {
2653   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2654   EmitUint8(0x66);
2655   EmitUint8(0x0F);
2656   EmitUint8(0x6A);
2657   EmitXmmRegisterOperand(dst, src);
2658 }
2659 
2660 
punpckhqdq(XmmRegister dst,XmmRegister src)2661 void X86Assembler::punpckhqdq(XmmRegister dst, XmmRegister src) {
2662   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2663   EmitUint8(0x66);
2664   EmitUint8(0x0F);
2665   EmitUint8(0x6D);
2666   EmitXmmRegisterOperand(dst, src);
2667 }
2668 
2669 
psllw(XmmRegister reg,const Immediate & shift_count)2670 void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
2671   DCHECK(shift_count.is_uint8());
2672   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2673   EmitUint8(0x66);
2674   EmitUint8(0x0F);
2675   EmitUint8(0x71);
2676   EmitXmmRegisterOperand(6, reg);
2677   EmitUint8(shift_count.value());
2678 }
2679 
2680 
pslld(XmmRegister reg,const Immediate & shift_count)2681 void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
2682   DCHECK(shift_count.is_uint8());
2683   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2684   EmitUint8(0x66);
2685   EmitUint8(0x0F);
2686   EmitUint8(0x72);
2687   EmitXmmRegisterOperand(6, reg);
2688   EmitUint8(shift_count.value());
2689 }
2690 
2691 
psllq(XmmRegister reg,const Immediate & shift_count)2692 void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
2693   DCHECK(shift_count.is_uint8());
2694   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2695   EmitUint8(0x66);
2696   EmitUint8(0x0F);
2697   EmitUint8(0x73);
2698   EmitXmmRegisterOperand(6, reg);
2699   EmitUint8(shift_count.value());
2700 }
2701 
2702 
psraw(XmmRegister reg,const Immediate & shift_count)2703 void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
2704   DCHECK(shift_count.is_uint8());
2705   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2706   EmitUint8(0x66);
2707   EmitUint8(0x0F);
2708   EmitUint8(0x71);
2709   EmitXmmRegisterOperand(4, reg);
2710   EmitUint8(shift_count.value());
2711 }
2712 
2713 
psrad(XmmRegister reg,const Immediate & shift_count)2714 void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
2715   DCHECK(shift_count.is_uint8());
2716   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2717   EmitUint8(0x66);
2718   EmitUint8(0x0F);
2719   EmitUint8(0x72);
2720   EmitXmmRegisterOperand(4, reg);
2721   EmitUint8(shift_count.value());
2722 }
2723 
2724 
psrlw(XmmRegister reg,const Immediate & shift_count)2725 void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
2726   DCHECK(shift_count.is_uint8());
2727   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2728   EmitUint8(0x66);
2729   EmitUint8(0x0F);
2730   EmitUint8(0x71);
2731   EmitXmmRegisterOperand(2, reg);
2732   EmitUint8(shift_count.value());
2733 }
2734 
2735 
psrld(XmmRegister reg,const Immediate & shift_count)2736 void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
2737   DCHECK(shift_count.is_uint8());
2738   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2739   EmitUint8(0x66);
2740   EmitUint8(0x0F);
2741   EmitUint8(0x72);
2742   EmitXmmRegisterOperand(2, reg);
2743   EmitUint8(shift_count.value());
2744 }
2745 
2746 
psrlq(XmmRegister reg,const Immediate & shift_count)2747 void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
2748   DCHECK(shift_count.is_uint8());
2749   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2750   EmitUint8(0x66);
2751   EmitUint8(0x0F);
2752   EmitUint8(0x73);
2753   EmitXmmRegisterOperand(2, reg);
2754   EmitUint8(shift_count.value());
2755 }
2756 
2757 
psrldq(XmmRegister reg,const Immediate & shift_count)2758 void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
2759   DCHECK(shift_count.is_uint8());
2760   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2761   EmitUint8(0x66);
2762   EmitUint8(0x0F);
2763   EmitUint8(0x73);
2764   EmitXmmRegisterOperand(3, reg);
2765   EmitUint8(shift_count.value());
2766 }
2767 
2768 
fldl(const Address & src)2769 void X86Assembler::fldl(const Address& src) {
2770   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2771   EmitUint8(0xDD);
2772   EmitOperand(0, src);
2773 }
2774 
2775 
fstl(const Address & dst)2776 void X86Assembler::fstl(const Address& dst) {
2777   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2778   EmitUint8(0xDD);
2779   EmitOperand(2, dst);
2780 }
2781 
2782 
fstpl(const Address & dst)2783 void X86Assembler::fstpl(const Address& dst) {
2784   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2785   EmitUint8(0xDD);
2786   EmitOperand(3, dst);
2787 }
2788 
2789 
fstsw()2790 void X86Assembler::fstsw() {
2791   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2792   EmitUint8(0x9B);
2793   EmitUint8(0xDF);
2794   EmitUint8(0xE0);
2795 }
2796 
2797 
fnstcw(const Address & dst)2798 void X86Assembler::fnstcw(const Address& dst) {
2799   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2800   EmitUint8(0xD9);
2801   EmitOperand(7, dst);
2802 }
2803 
2804 
fldcw(const Address & src)2805 void X86Assembler::fldcw(const Address& src) {
2806   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2807   EmitUint8(0xD9);
2808   EmitOperand(5, src);
2809 }
2810 
2811 
fistpl(const Address & dst)2812 void X86Assembler::fistpl(const Address& dst) {
2813   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2814   EmitUint8(0xDF);
2815   EmitOperand(7, dst);
2816 }
2817 
2818 
fistps(const Address & dst)2819 void X86Assembler::fistps(const Address& dst) {
2820   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2821   EmitUint8(0xDB);
2822   EmitOperand(3, dst);
2823 }
2824 
2825 
fildl(const Address & src)2826 void X86Assembler::fildl(const Address& src) {
2827   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2828   EmitUint8(0xDF);
2829   EmitOperand(5, src);
2830 }
2831 
2832 
filds(const Address & src)2833 void X86Assembler::filds(const Address& src) {
2834   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2835   EmitUint8(0xDB);
2836   EmitOperand(0, src);
2837 }
2838 
2839 
fincstp()2840 void X86Assembler::fincstp() {
2841   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2842   EmitUint8(0xD9);
2843   EmitUint8(0xF7);
2844 }
2845 
2846 
ffree(const Immediate & index)2847 void X86Assembler::ffree(const Immediate& index) {
2848   CHECK_LT(index.value(), 7);
2849   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2850   EmitUint8(0xDD);
2851   EmitUint8(0xC0 + index.value());
2852 }
2853 
2854 
fsin()2855 void X86Assembler::fsin() {
2856   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2857   EmitUint8(0xD9);
2858   EmitUint8(0xFE);
2859 }
2860 
2861 
fcos()2862 void X86Assembler::fcos() {
2863   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2864   EmitUint8(0xD9);
2865   EmitUint8(0xFF);
2866 }
2867 
2868 
fptan()2869 void X86Assembler::fptan() {
2870   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2871   EmitUint8(0xD9);
2872   EmitUint8(0xF2);
2873 }
2874 
2875 
fucompp()2876 void X86Assembler::fucompp() {
2877   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2878   EmitUint8(0xDA);
2879   EmitUint8(0xE9);
2880 }
2881 
2882 
fprem()2883 void X86Assembler::fprem() {
2884   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2885   EmitUint8(0xD9);
2886   EmitUint8(0xF8);
2887 }
2888 
2889 
xchgl(Register dst,Register src)2890 void X86Assembler::xchgl(Register dst, Register src) {
2891   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2892   EmitUint8(0x87);
2893   EmitRegisterOperand(dst, src);
2894 }
2895 
2896 
xchgl(Register reg,const Address & address)2897 void X86Assembler::xchgl(Register reg, const Address& address) {
2898   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2899   EmitUint8(0x87);
2900   EmitOperand(reg, address);
2901 }
2902 
2903 
cmpb(const Address & address,const Immediate & imm)2904 void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
2905   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2906   EmitUint8(0x80);
2907   EmitOperand(7, address);
2908   EmitUint8(imm.value() & 0xFF);
2909 }
2910 
2911 
cmpw(const Address & address,const Immediate & imm)2912 void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
2913   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2914   EmitUint8(0x66);
2915   EmitComplex(7, address, imm, /* is_16_op= */ true);
2916 }
2917 
2918 
cmpl(Register reg,const Immediate & imm)2919 void X86Assembler::cmpl(Register reg, const Immediate& imm) {
2920   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2921   EmitComplex(7, Operand(reg), imm);
2922 }
2923 
2924 
cmpl(Register reg0,Register reg1)2925 void X86Assembler::cmpl(Register reg0, Register reg1) {
2926   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2927   EmitUint8(0x3B);
2928   EmitOperand(reg0, Operand(reg1));
2929 }
2930 
2931 
cmpl(Register reg,const Address & address)2932 void X86Assembler::cmpl(Register reg, const Address& address) {
2933   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2934   EmitUint8(0x3B);
2935   EmitOperand(reg, address);
2936 }
2937 
2938 
addl(Register dst,Register src)2939 void X86Assembler::addl(Register dst, Register src) {
2940   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2941   EmitUint8(0x03);
2942   EmitRegisterOperand(dst, src);
2943 }
2944 
2945 
addl(Register reg,const Address & address)2946 void X86Assembler::addl(Register reg, const Address& address) {
2947   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2948   EmitUint8(0x03);
2949   EmitOperand(reg, address);
2950 }
2951 
2952 
cmpl(const Address & address,Register reg)2953 void X86Assembler::cmpl(const Address& address, Register reg) {
2954   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2955   EmitUint8(0x39);
2956   EmitOperand(reg, address);
2957 }
2958 
2959 
cmpl(const Address & address,const Immediate & imm)2960 void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
2961   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2962   EmitComplex(7, address, imm);
2963 }
2964 
2965 
testl(Register reg1,Register reg2)2966 void X86Assembler::testl(Register reg1, Register reg2) {
2967   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2968   EmitUint8(0x85);
2969   EmitRegisterOperand(reg1, reg2);
2970 }
2971 
2972 
testl(Register reg,const Address & address)2973 void X86Assembler::testl(Register reg, const Address& address) {
2974   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2975   EmitUint8(0x85);
2976   EmitOperand(reg, address);
2977 }
2978 
2979 
testl(Register reg,const Immediate & immediate)2980 void X86Assembler::testl(Register reg, const Immediate& immediate) {
2981   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2982   // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
2983   // we only test the byte register to keep the encoding short.
2984   if (immediate.is_uint8() && reg < 4) {
2985     // Use zero-extended 8-bit immediate.
2986     if (reg == EAX) {
2987       EmitUint8(0xA8);
2988     } else {
2989       EmitUint8(0xF6);
2990       EmitUint8(0xC0 + reg);
2991     }
2992     EmitUint8(immediate.value() & 0xFF);
2993   } else if (reg == EAX) {
2994     // Use short form if the destination is EAX.
2995     EmitUint8(0xA9);
2996     EmitImmediate(immediate);
2997   } else {
2998     EmitUint8(0xF7);
2999     EmitOperand(0, Operand(reg));
3000     EmitImmediate(immediate);
3001   }
3002 }
3003 
3004 
testb(const Address & dst,const Immediate & imm)3005 void X86Assembler::testb(const Address& dst, const Immediate& imm) {
3006   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3007   EmitUint8(0xF6);
3008   EmitOperand(EAX, dst);
3009   CHECK(imm.is_int8());
3010   EmitUint8(imm.value() & 0xFF);
3011 }
3012 
3013 
testl(const Address & dst,const Immediate & imm)3014 void X86Assembler::testl(const Address& dst, const Immediate& imm) {
3015   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3016   EmitUint8(0xF7);
3017   EmitOperand(0, dst);
3018   EmitImmediate(imm);
3019 }
3020 
3021 
andl(Register dst,Register src)3022 void X86Assembler::andl(Register dst, Register src) {
3023   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3024   EmitUint8(0x23);
3025   EmitOperand(dst, Operand(src));
3026 }
3027 
3028 
andl(Register reg,const Address & address)3029 void X86Assembler::andl(Register reg, const Address& address) {
3030   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3031   EmitUint8(0x23);
3032   EmitOperand(reg, address);
3033 }
3034 
3035 
andl(Register dst,const Immediate & imm)3036 void X86Assembler::andl(Register dst, const Immediate& imm) {
3037   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3038   EmitComplex(4, Operand(dst), imm);
3039 }
3040 
3041 
orl(Register dst,Register src)3042 void X86Assembler::orl(Register dst, Register src) {
3043   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3044   EmitUint8(0x0B);
3045   EmitOperand(dst, Operand(src));
3046 }
3047 
3048 
orl(Register reg,const Address & address)3049 void X86Assembler::orl(Register reg, const Address& address) {
3050   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3051   EmitUint8(0x0B);
3052   EmitOperand(reg, address);
3053 }
3054 
3055 
orl(Register dst,const Immediate & imm)3056 void X86Assembler::orl(Register dst, const Immediate& imm) {
3057   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3058   EmitComplex(1, Operand(dst), imm);
3059 }
3060 
3061 
xorl(Register dst,Register src)3062 void X86Assembler::xorl(Register dst, Register src) {
3063   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3064   EmitUint8(0x33);
3065   EmitOperand(dst, Operand(src));
3066 }
3067 
3068 
xorl(Register reg,const Address & address)3069 void X86Assembler::xorl(Register reg, const Address& address) {
3070   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3071   EmitUint8(0x33);
3072   EmitOperand(reg, address);
3073 }
3074 
3075 
xorl(Register dst,const Immediate & imm)3076 void X86Assembler::xorl(Register dst, const Immediate& imm) {
3077   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3078   EmitComplex(6, Operand(dst), imm);
3079 }
3080 
3081 
addl(Register reg,const Immediate & imm)3082 void X86Assembler::addl(Register reg, const Immediate& imm) {
3083   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3084   EmitComplex(0, Operand(reg), imm);
3085 }
3086 
3087 
addl(const Address & address,Register reg)3088 void X86Assembler::addl(const Address& address, Register reg) {
3089   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3090   EmitUint8(0x01);
3091   EmitOperand(reg, address);
3092 }
3093 
3094 
addl(const Address & address,const Immediate & imm)3095 void X86Assembler::addl(const Address& address, const Immediate& imm) {
3096   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3097   EmitComplex(0, address, imm);
3098 }
3099 
3100 
addw(const Address & address,const Immediate & imm)3101 void X86Assembler::addw(const Address& address, const Immediate& imm) {
3102   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3103   CHECK(imm.is_uint16() || imm.is_int16()) << imm.value();
3104   EmitUint8(0x66);
3105   EmitComplex(0, address, imm, /* is_16_op= */ true);
3106 }
3107 
3108 
adcl(Register reg,const Immediate & imm)3109 void X86Assembler::adcl(Register reg, const Immediate& imm) {
3110   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3111   EmitComplex(2, Operand(reg), imm);
3112 }
3113 
3114 
adcl(Register dst,Register src)3115 void X86Assembler::adcl(Register dst, Register src) {
3116   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3117   EmitUint8(0x13);
3118   EmitOperand(dst, Operand(src));
3119 }
3120 
3121 
adcl(Register dst,const Address & address)3122 void X86Assembler::adcl(Register dst, const Address& address) {
3123   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3124   EmitUint8(0x13);
3125   EmitOperand(dst, address);
3126 }
3127 
3128 
subl(Register dst,Register src)3129 void X86Assembler::subl(Register dst, Register src) {
3130   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3131   EmitUint8(0x2B);
3132   EmitOperand(dst, Operand(src));
3133 }
3134 
3135 
subl(Register reg,const Immediate & imm)3136 void X86Assembler::subl(Register reg, const Immediate& imm) {
3137   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3138   EmitComplex(5, Operand(reg), imm);
3139 }
3140 
3141 
subl(Register reg,const Address & address)3142 void X86Assembler::subl(Register reg, const Address& address) {
3143   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3144   EmitUint8(0x2B);
3145   EmitOperand(reg, address);
3146 }
3147 
3148 
subl(const Address & address,Register reg)3149 void X86Assembler::subl(const Address& address, Register reg) {
3150   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3151   EmitUint8(0x29);
3152   EmitOperand(reg, address);
3153 }
3154 
3155 
cdq()3156 void X86Assembler::cdq() {
3157   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3158   EmitUint8(0x99);
3159 }
3160 
3161 
idivl(Register reg)3162 void X86Assembler::idivl(Register reg) {
3163   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3164   EmitUint8(0xF7);
3165   EmitUint8(0xF8 | reg);
3166 }
3167 
3168 
imull(Register dst,Register src)3169 void X86Assembler::imull(Register dst, Register src) {
3170   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3171   EmitUint8(0x0F);
3172   EmitUint8(0xAF);
3173   EmitOperand(dst, Operand(src));
3174 }
3175 
3176 
imull(Register dst,Register src,const Immediate & imm)3177 void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
3178   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3179   // See whether imm can be represented as a sign-extended 8bit value.
3180   int32_t v32 = static_cast<int32_t>(imm.value());
3181   if (IsInt<8>(v32)) {
3182     // Sign-extension works.
3183     EmitUint8(0x6B);
3184     EmitOperand(dst, Operand(src));
3185     EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
3186   } else {
3187     // Not representable, use full immediate.
3188     EmitUint8(0x69);
3189     EmitOperand(dst, Operand(src));
3190     EmitImmediate(imm);
3191   }
3192 }
3193 
3194 
imull(Register reg,const Immediate & imm)3195 void X86Assembler::imull(Register reg, const Immediate& imm) {
3196   imull(reg, reg, imm);
3197 }
3198 
3199 
imull(Register reg,const Address & address)3200 void X86Assembler::imull(Register reg, const Address& address) {
3201   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3202   EmitUint8(0x0F);
3203   EmitUint8(0xAF);
3204   EmitOperand(reg, address);
3205 }
3206 
3207 
imull(Register reg)3208 void X86Assembler::imull(Register reg) {
3209   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3210   EmitUint8(0xF7);
3211   EmitOperand(5, Operand(reg));
3212 }
3213 
3214 
imull(const Address & address)3215 void X86Assembler::imull(const Address& address) {
3216   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3217   EmitUint8(0xF7);
3218   EmitOperand(5, address);
3219 }
3220 
3221 
mull(Register reg)3222 void X86Assembler::mull(Register reg) {
3223   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3224   EmitUint8(0xF7);
3225   EmitOperand(4, Operand(reg));
3226 }
3227 
3228 
mull(const Address & address)3229 void X86Assembler::mull(const Address& address) {
3230   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3231   EmitUint8(0xF7);
3232   EmitOperand(4, address);
3233 }
3234 
3235 
sbbl(Register dst,Register src)3236 void X86Assembler::sbbl(Register dst, Register src) {
3237   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3238   EmitUint8(0x1B);
3239   EmitOperand(dst, Operand(src));
3240 }
3241 
3242 
sbbl(Register reg,const Immediate & imm)3243 void X86Assembler::sbbl(Register reg, const Immediate& imm) {
3244   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3245   EmitComplex(3, Operand(reg), imm);
3246 }
3247 
3248 
sbbl(Register dst,const Address & address)3249 void X86Assembler::sbbl(Register dst, const Address& address) {
3250   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3251   EmitUint8(0x1B);
3252   EmitOperand(dst, address);
3253 }
3254 
3255 
sbbl(const Address & address,Register src)3256 void X86Assembler::sbbl(const Address& address, Register src) {
3257   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3258   EmitUint8(0x19);
3259   EmitOperand(src, address);
3260 }
3261 
3262 
incl(Register reg)3263 void X86Assembler::incl(Register reg) {
3264   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3265   EmitUint8(0x40 + reg);
3266 }
3267 
3268 
incl(const Address & address)3269 void X86Assembler::incl(const Address& address) {
3270   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3271   EmitUint8(0xFF);
3272   EmitOperand(0, address);
3273 }
3274 
3275 
decl(Register reg)3276 void X86Assembler::decl(Register reg) {
3277   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3278   EmitUint8(0x48 + reg);
3279 }
3280 
3281 
decl(const Address & address)3282 void X86Assembler::decl(const Address& address) {
3283   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3284   EmitUint8(0xFF);
3285   EmitOperand(1, address);
3286 }
3287 
3288 
shll(Register reg,const Immediate & imm)3289 void X86Assembler::shll(Register reg, const Immediate& imm) {
3290   EmitGenericShift(4, Operand(reg), imm);
3291 }
3292 
3293 
shll(Register operand,Register shifter)3294 void X86Assembler::shll(Register operand, Register shifter) {
3295   EmitGenericShift(4, Operand(operand), shifter);
3296 }
3297 
3298 
shll(const Address & address,const Immediate & imm)3299 void X86Assembler::shll(const Address& address, const Immediate& imm) {
3300   EmitGenericShift(4, address, imm);
3301 }
3302 
3303 
shll(const Address & address,Register shifter)3304 void X86Assembler::shll(const Address& address, Register shifter) {
3305   EmitGenericShift(4, address, shifter);
3306 }
3307 
3308 
shrl(Register reg,const Immediate & imm)3309 void X86Assembler::shrl(Register reg, const Immediate& imm) {
3310   EmitGenericShift(5, Operand(reg), imm);
3311 }
3312 
3313 
shrl(Register operand,Register shifter)3314 void X86Assembler::shrl(Register operand, Register shifter) {
3315   EmitGenericShift(5, Operand(operand), shifter);
3316 }
3317 
3318 
shrl(const Address & address,const Immediate & imm)3319 void X86Assembler::shrl(const Address& address, const Immediate& imm) {
3320   EmitGenericShift(5, address, imm);
3321 }
3322 
3323 
shrl(const Address & address,Register shifter)3324 void X86Assembler::shrl(const Address& address, Register shifter) {
3325   EmitGenericShift(5, address, shifter);
3326 }
3327 
3328 
sarl(Register reg,const Immediate & imm)3329 void X86Assembler::sarl(Register reg, const Immediate& imm) {
3330   EmitGenericShift(7, Operand(reg), imm);
3331 }
3332 
3333 
sarl(Register operand,Register shifter)3334 void X86Assembler::sarl(Register operand, Register shifter) {
3335   EmitGenericShift(7, Operand(operand), shifter);
3336 }
3337 
3338 
sarl(const Address & address,const Immediate & imm)3339 void X86Assembler::sarl(const Address& address, const Immediate& imm) {
3340   EmitGenericShift(7, address, imm);
3341 }
3342 
3343 
sarl(const Address & address,Register shifter)3344 void X86Assembler::sarl(const Address& address, Register shifter) {
3345   EmitGenericShift(7, address, shifter);
3346 }
3347 
3348 
shld(Register dst,Register src,Register shifter)3349 void X86Assembler::shld(Register dst, Register src, Register shifter) {
3350   DCHECK_EQ(ECX, shifter);
3351   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3352   EmitUint8(0x0F);
3353   EmitUint8(0xA5);
3354   EmitRegisterOperand(src, dst);
3355 }
3356 
3357 
shld(Register dst,Register src,const Immediate & imm)3358 void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
3359   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3360   EmitUint8(0x0F);
3361   EmitUint8(0xA4);
3362   EmitRegisterOperand(src, dst);
3363   EmitUint8(imm.value() & 0xFF);
3364 }
3365 
3366 
shrd(Register dst,Register src,Register shifter)3367 void X86Assembler::shrd(Register dst, Register src, Register shifter) {
3368   DCHECK_EQ(ECX, shifter);
3369   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3370   EmitUint8(0x0F);
3371   EmitUint8(0xAD);
3372   EmitRegisterOperand(src, dst);
3373 }
3374 
3375 
shrd(Register dst,Register src,const Immediate & imm)3376 void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
3377   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3378   EmitUint8(0x0F);
3379   EmitUint8(0xAC);
3380   EmitRegisterOperand(src, dst);
3381   EmitUint8(imm.value() & 0xFF);
3382 }
3383 
3384 
roll(Register reg,const Immediate & imm)3385 void X86Assembler::roll(Register reg, const Immediate& imm) {
3386   EmitGenericShift(0, Operand(reg), imm);
3387 }
3388 
3389 
roll(Register operand,Register shifter)3390 void X86Assembler::roll(Register operand, Register shifter) {
3391   EmitGenericShift(0, Operand(operand), shifter);
3392 }
3393 
3394 
rorl(Register reg,const Immediate & imm)3395 void X86Assembler::rorl(Register reg, const Immediate& imm) {
3396   EmitGenericShift(1, Operand(reg), imm);
3397 }
3398 
3399 
rorl(Register operand,Register shifter)3400 void X86Assembler::rorl(Register operand, Register shifter) {
3401   EmitGenericShift(1, Operand(operand), shifter);
3402 }
3403 
3404 
negl(Register reg)3405 void X86Assembler::negl(Register reg) {
3406   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3407   EmitUint8(0xF7);
3408   EmitOperand(3, Operand(reg));
3409 }
3410 
3411 
notl(Register reg)3412 void X86Assembler::notl(Register reg) {
3413   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3414   EmitUint8(0xF7);
3415   EmitUint8(0xD0 | reg);
3416 }
3417 
3418 
enter(const Immediate & imm)3419 void X86Assembler::enter(const Immediate& imm) {
3420   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3421   EmitUint8(0xC8);
3422   CHECK(imm.is_uint16());
3423   EmitUint8(imm.value() & 0xFF);
3424   EmitUint8((imm.value() >> 8) & 0xFF);
3425   EmitUint8(0x00);
3426 }
3427 
3428 
leave()3429 void X86Assembler::leave() {
3430   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3431   EmitUint8(0xC9);
3432 }
3433 
3434 
ret()3435 void X86Assembler::ret() {
3436   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3437   EmitUint8(0xC3);
3438 }
3439 
3440 
ret(const Immediate & imm)3441 void X86Assembler::ret(const Immediate& imm) {
3442   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3443   EmitUint8(0xC2);
3444   CHECK(imm.is_uint16());
3445   EmitUint8(imm.value() & 0xFF);
3446   EmitUint8((imm.value() >> 8) & 0xFF);
3447 }
3448 
3449 
3450 
nop()3451 void X86Assembler::nop() {
3452   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3453   EmitUint8(0x90);
3454 }
3455 
3456 
int3()3457 void X86Assembler::int3() {
3458   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3459   EmitUint8(0xCC);
3460 }
3461 
3462 
hlt()3463 void X86Assembler::hlt() {
3464   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3465   EmitUint8(0xF4);
3466 }
3467 
3468 
j(Condition condition,Label * label)3469 void X86Assembler::j(Condition condition, Label* label) {
3470   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3471   if (label->IsBound()) {
3472     static const int kShortSize = 2;
3473     static const int kLongSize = 6;
3474     int offset = label->Position() - buffer_.Size();
3475     CHECK_LE(offset, 0);
3476     if (IsInt<8>(offset - kShortSize)) {
3477       EmitUint8(0x70 + condition);
3478       EmitUint8((offset - kShortSize) & 0xFF);
3479     } else {
3480       EmitUint8(0x0F);
3481       EmitUint8(0x80 + condition);
3482       EmitInt32(offset - kLongSize);
3483     }
3484   } else {
3485     EmitUint8(0x0F);
3486     EmitUint8(0x80 + condition);
3487     EmitLabelLink(label);
3488   }
3489 }
3490 
3491 
j(Condition condition,NearLabel * label)3492 void X86Assembler::j(Condition condition, NearLabel* label) {
3493   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3494   if (label->IsBound()) {
3495     static const int kShortSize = 2;
3496     int offset = label->Position() - buffer_.Size();
3497     CHECK_LE(offset, 0);
3498     CHECK(IsInt<8>(offset - kShortSize));
3499     EmitUint8(0x70 + condition);
3500     EmitUint8((offset - kShortSize) & 0xFF);
3501   } else {
3502     EmitUint8(0x70 + condition);
3503     EmitLabelLink(label);
3504   }
3505 }
3506 
3507 
jecxz(NearLabel * label)3508 void X86Assembler::jecxz(NearLabel* label) {
3509   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3510   if (label->IsBound()) {
3511     static const int kShortSize = 2;
3512     int offset = label->Position() - buffer_.Size();
3513     CHECK_LE(offset, 0);
3514     CHECK(IsInt<8>(offset - kShortSize));
3515     EmitUint8(0xE3);
3516     EmitUint8((offset - kShortSize) & 0xFF);
3517   } else {
3518     EmitUint8(0xE3);
3519     EmitLabelLink(label);
3520   }
3521 }
3522 
3523 
jmp(Register reg)3524 void X86Assembler::jmp(Register reg) {
3525   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3526   EmitUint8(0xFF);
3527   EmitRegisterOperand(4, reg);
3528 }
3529 
jmp(const Address & address)3530 void X86Assembler::jmp(const Address& address) {
3531   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3532   EmitUint8(0xFF);
3533   EmitOperand(4, address);
3534 }
3535 
jmp(Label * label)3536 void X86Assembler::jmp(Label* label) {
3537   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3538   if (label->IsBound()) {
3539     static const int kShortSize = 2;
3540     static const int kLongSize = 5;
3541     int offset = label->Position() - buffer_.Size();
3542     CHECK_LE(offset, 0);
3543     if (IsInt<8>(offset - kShortSize)) {
3544       EmitUint8(0xEB);
3545       EmitUint8((offset - kShortSize) & 0xFF);
3546     } else {
3547       EmitUint8(0xE9);
3548       EmitInt32(offset - kLongSize);
3549     }
3550   } else {
3551     EmitUint8(0xE9);
3552     EmitLabelLink(label);
3553   }
3554 }
3555 
3556 
jmp(NearLabel * label)3557 void X86Assembler::jmp(NearLabel* label) {
3558   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3559   if (label->IsBound()) {
3560     static const int kShortSize = 2;
3561     int offset = label->Position() - buffer_.Size();
3562     CHECK_LE(offset, 0);
3563     CHECK(IsInt<8>(offset - kShortSize));
3564     EmitUint8(0xEB);
3565     EmitUint8((offset - kShortSize) & 0xFF);
3566   } else {
3567     EmitUint8(0xEB);
3568     EmitLabelLink(label);
3569   }
3570 }
3571 
3572 
repne_scasb()3573 void X86Assembler::repne_scasb() {
3574   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3575   EmitUint8(0xF2);
3576   EmitUint8(0xAE);
3577 }
3578 
3579 
repne_scasw()3580 void X86Assembler::repne_scasw() {
3581   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3582   EmitUint8(0x66);
3583   EmitUint8(0xF2);
3584   EmitUint8(0xAF);
3585 }
3586 
3587 
repe_cmpsb()3588 void X86Assembler::repe_cmpsb() {
3589   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3590   EmitUint8(0xF2);
3591   EmitUint8(0xA6);
3592 }
3593 
3594 
repe_cmpsw()3595 void X86Assembler::repe_cmpsw() {
3596   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3597   EmitUint8(0x66);
3598   EmitUint8(0xF3);
3599   EmitUint8(0xA7);
3600 }
3601 
3602 
repe_cmpsl()3603 void X86Assembler::repe_cmpsl() {
3604   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3605   EmitUint8(0xF3);
3606   EmitUint8(0xA7);
3607 }
3608 
3609 
rep_movsb()3610 void X86Assembler::rep_movsb() {
3611   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3612   EmitUint8(0xF3);
3613   EmitUint8(0xA4);
3614 }
3615 
3616 
rep_movsw()3617 void X86Assembler::rep_movsw() {
3618   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3619   EmitUint8(0x66);
3620   EmitUint8(0xF3);
3621   EmitUint8(0xA5);
3622 }
3623 
3624 
lock()3625 X86Assembler* X86Assembler::lock() {
3626   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3627   EmitUint8(0xF0);
3628   return this;
3629 }
3630 
3631 
cmpxchgl(const Address & address,Register reg)3632 void X86Assembler::cmpxchgl(const Address& address, Register reg) {
3633   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3634   EmitUint8(0x0F);
3635   EmitUint8(0xB1);
3636   EmitOperand(reg, address);
3637 }
3638 
3639 
cmpxchg8b(const Address & address)3640 void X86Assembler::cmpxchg8b(const Address& address) {
3641   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3642   EmitUint8(0x0F);
3643   EmitUint8(0xC7);
3644   EmitOperand(1, address);
3645 }
3646 
3647 
mfence()3648 void X86Assembler::mfence() {
3649   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3650   EmitUint8(0x0F);
3651   EmitUint8(0xAE);
3652   EmitUint8(0xF0);
3653 }
3654 
fs()3655 X86Assembler* X86Assembler::fs() {
3656   // TODO: fs is a prefix and not an instruction
3657   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3658   EmitUint8(0x64);
3659   return this;
3660 }
3661 
gs()3662 X86Assembler* X86Assembler::gs() {
3663   // TODO: fs is a prefix and not an instruction
3664   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3665   EmitUint8(0x65);
3666   return this;
3667 }
3668 
AddImmediate(Register reg,const Immediate & imm)3669 void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
3670   int value = imm.value();
3671   if (value > 0) {
3672     if (value == 1) {
3673       incl(reg);
3674     } else if (value != 0) {
3675       addl(reg, imm);
3676     }
3677   } else if (value < 0) {
3678     value = -value;
3679     if (value == 1) {
3680       decl(reg);
3681     } else if (value != 0) {
3682       subl(reg, Immediate(value));
3683     }
3684   }
3685 }
3686 
3687 
LoadLongConstant(XmmRegister dst,int64_t value)3688 void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
3689   // TODO: Need to have a code constants table.
3690   pushl(Immediate(High32Bits(value)));
3691   pushl(Immediate(Low32Bits(value)));
3692   movsd(dst, Address(ESP, 0));
3693   addl(ESP, Immediate(2 * sizeof(int32_t)));
3694 }
3695 
3696 
LoadDoubleConstant(XmmRegister dst,double value)3697 void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
3698   // TODO: Need to have a code constants table.
3699   int64_t constant = bit_cast<int64_t, double>(value);
3700   LoadLongConstant(dst, constant);
3701 }
3702 
3703 
Align(int alignment,int offset)3704 void X86Assembler::Align(int alignment, int offset) {
3705   CHECK(IsPowerOfTwo(alignment));
3706   // Emit nop instruction until the real position is aligned.
3707   while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
3708     nop();
3709   }
3710 }
3711 
3712 
Bind(Label * label)3713 void X86Assembler::Bind(Label* label) {
3714   int bound = buffer_.Size();
3715   CHECK(!label->IsBound());  // Labels can only be bound once.
3716   while (label->IsLinked()) {
3717     int position = label->LinkPosition();
3718     int next = buffer_.Load<int32_t>(position);
3719     buffer_.Store<int32_t>(position, bound - (position + 4));
3720     label->position_ = next;
3721   }
3722   label->BindTo(bound);
3723 }
3724 
3725 
Bind(NearLabel * label)3726 void X86Assembler::Bind(NearLabel* label) {
3727   int bound = buffer_.Size();
3728   CHECK(!label->IsBound());  // Labels can only be bound once.
3729   while (label->IsLinked()) {
3730     int position = label->LinkPosition();
3731     uint8_t delta = buffer_.Load<uint8_t>(position);
3732     int offset = bound - (position + 1);
3733     CHECK(IsInt<8>(offset));
3734     buffer_.Store<int8_t>(position, offset);
3735     label->position_ = delta != 0u ? label->position_ - delta : 0;
3736   }
3737   label->BindTo(bound);
3738 }
3739 
3740 
EmitOperand(int reg_or_opcode,const Operand & operand)3741 void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
3742   CHECK_GE(reg_or_opcode, 0);
3743   CHECK_LT(reg_or_opcode, 8);
3744   const int length = operand.length_;
3745   CHECK_GT(length, 0);
3746   // Emit the ModRM byte updated with the given reg value.
3747   CHECK_EQ(operand.encoding_[0] & 0x38, 0);
3748   EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
3749   // Emit the rest of the encoded operand.
3750   for (int i = 1; i < length; i++) {
3751     EmitUint8(operand.encoding_[i]);
3752   }
3753   AssemblerFixup* fixup = operand.GetFixup();
3754   if (fixup != nullptr) {
3755     EmitFixup(fixup);
3756   }
3757 }
3758 
3759 
EmitImmediate(const Immediate & imm,bool is_16_op)3760 void X86Assembler::EmitImmediate(const Immediate& imm, bool is_16_op) {
3761   if (is_16_op) {
3762     EmitUint8(imm.value() & 0xFF);
3763     EmitUint8(imm.value() >> 8);
3764   } else {
3765     EmitInt32(imm.value());
3766   }
3767 }
3768 
3769 
EmitComplex(int reg_or_opcode,const Operand & operand,const Immediate & immediate,bool is_16_op)3770 void X86Assembler::EmitComplex(int reg_or_opcode,
3771                                const Operand& operand,
3772                                const Immediate& immediate,
3773                                bool is_16_op) {
3774   CHECK_GE(reg_or_opcode, 0);
3775   CHECK_LT(reg_or_opcode, 8);
3776   if (immediate.is_int8()) {
3777     // Use sign-extended 8-bit immediate.
3778     EmitUint8(0x83);
3779     EmitOperand(reg_or_opcode, operand);
3780     EmitUint8(immediate.value() & 0xFF);
3781   } else if (operand.IsRegister(EAX)) {
3782     // Use short form if the destination is eax.
3783     EmitUint8(0x05 + (reg_or_opcode << 3));
3784     EmitImmediate(immediate, is_16_op);
3785   } else {
3786     EmitUint8(0x81);
3787     EmitOperand(reg_or_opcode, operand);
3788     EmitImmediate(immediate, is_16_op);
3789   }
3790 }
3791 
3792 
EmitLabel(Label * label,int instruction_size)3793 void X86Assembler::EmitLabel(Label* label, int instruction_size) {
3794   if (label->IsBound()) {
3795     int offset = label->Position() - buffer_.Size();
3796     CHECK_LE(offset, 0);
3797     EmitInt32(offset - instruction_size);
3798   } else {
3799     EmitLabelLink(label);
3800   }
3801 }
3802 
3803 
EmitLabelLink(Label * label)3804 void X86Assembler::EmitLabelLink(Label* label) {
3805   CHECK(!label->IsBound());
3806   int position = buffer_.Size();
3807   EmitInt32(label->position_);
3808   label->LinkTo(position);
3809 }
3810 
3811 
EmitLabelLink(NearLabel * label)3812 void X86Assembler::EmitLabelLink(NearLabel* label) {
3813   CHECK(!label->IsBound());
3814   int position = buffer_.Size();
3815   if (label->IsLinked()) {
3816     // Save the delta in the byte that we have to play with.
3817     uint32_t delta = position - label->LinkPosition();
3818     CHECK(IsUint<8>(delta));
3819     EmitUint8(delta & 0xFF);
3820   } else {
3821     EmitUint8(0);
3822   }
3823   label->LinkTo(position);
3824 }
3825 
3826 
EmitGenericShift(int reg_or_opcode,const Operand & operand,const Immediate & imm)3827 void X86Assembler::EmitGenericShift(int reg_or_opcode,
3828                                     const Operand& operand,
3829                                     const Immediate& imm) {
3830   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3831   CHECK(imm.is_int8());
3832   if (imm.value() == 1) {
3833     EmitUint8(0xD1);
3834     EmitOperand(reg_or_opcode, operand);
3835   } else {
3836     EmitUint8(0xC1);
3837     EmitOperand(reg_or_opcode, operand);
3838     EmitUint8(imm.value() & 0xFF);
3839   }
3840 }
3841 
3842 
EmitGenericShift(int reg_or_opcode,const Operand & operand,Register shifter)3843 void X86Assembler::EmitGenericShift(int reg_or_opcode,
3844                                     const Operand& operand,
3845                                     Register shifter) {
3846   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3847   CHECK_EQ(shifter, ECX);
3848   EmitUint8(0xD3);
3849   EmitOperand(reg_or_opcode, operand);
3850 }
3851 
AddConstantArea()3852 void X86Assembler::AddConstantArea() {
3853   ArrayRef<const int32_t> area = constant_area_.GetBuffer();
3854   // Generate the data for the literal area.
3855   for (size_t i = 0, e = area.size(); i < e; i++) {
3856     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3857     EmitInt32(area[i]);
3858   }
3859 }
3860 
AppendInt32(int32_t v)3861 size_t ConstantArea::AppendInt32(int32_t v) {
3862   size_t result = buffer_.size() * elem_size_;
3863   buffer_.push_back(v);
3864   return result;
3865 }
3866 
AddInt32(int32_t v)3867 size_t ConstantArea::AddInt32(int32_t v) {
3868   for (size_t i = 0, e = buffer_.size(); i < e; i++) {
3869     if (v == buffer_[i]) {
3870       return i * elem_size_;
3871     }
3872   }
3873 
3874   // Didn't match anything.
3875   return AppendInt32(v);
3876 }
3877 
AddInt64(int64_t v)3878 size_t ConstantArea::AddInt64(int64_t v) {
3879   int32_t v_low = Low32Bits(v);
3880   int32_t v_high = High32Bits(v);
3881   if (buffer_.size() > 1) {
3882     // Ensure we don't pass the end of the buffer.
3883     for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
3884       if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
3885         return i * elem_size_;
3886       }
3887     }
3888   }
3889 
3890   // Didn't match anything.
3891   size_t result = buffer_.size() * elem_size_;
3892   buffer_.push_back(v_low);
3893   buffer_.push_back(v_high);
3894   return result;
3895 }
3896 
AddDouble(double v)3897 size_t ConstantArea::AddDouble(double v) {
3898   // Treat the value as a 64-bit integer value.
3899   return AddInt64(bit_cast<int64_t, double>(v));
3900 }
3901 
AddFloat(float v)3902 size_t ConstantArea::AddFloat(float v) {
3903   // Treat the value as a 32-bit integer value.
3904   return AddInt32(bit_cast<int32_t, float>(v));
3905 }
3906 
EmitVexPrefixByteZero(bool is_twobyte_form)3907 uint8_t X86Assembler::EmitVexPrefixByteZero(bool is_twobyte_form) {
3908   /**Vex Byte 0,
3909   Bits [7:0] must contain the value 11000101b (0xC5) for 2-byte Vex
3910   Bits [7:0] must contain the value 11000100b (0xC4) for 3-byte Vex */
3911   uint8_t vex_prefix = 0xC0;
3912   if (is_twobyte_form) {
3913     // 2-Byte Vex
3914     vex_prefix |= TWO_BYTE_VEX;
3915   } else {
3916     // 3-Byte Vex
3917     vex_prefix |= THREE_BYTE_VEX;
3918   }
3919   return vex_prefix;
3920 }
3921 
EmitVexPrefixByteOne(bool R,bool X,bool B,int SET_VEX_M)3922 uint8_t X86Assembler::EmitVexPrefixByteOne(bool R,
3923                                            bool X,
3924                                            bool B,
3925                                            int SET_VEX_M) {
3926   /**Vex Byte 1, */
3927   uint8_t vex_prefix = VEX_INIT;
3928   /** Bit[7] This bit needs to be set to '1'
3929   otherwise the instruction is LES or LDS */
3930   if (!R) {
3931     // R .
3932     vex_prefix |= SET_VEX_R;
3933   }
3934   /** Bit[6] This bit needs to be set to '1'
3935   otherwise the instruction is LES or LDS */
3936   if (!X) {
3937     // X .
3938     vex_prefix |= SET_VEX_X;
3939   }
3940   /** Bit[5] This bit needs to be set to '1' */
3941   if (!B) {
3942     // B .
3943     vex_prefix |= SET_VEX_B;
3944   }
3945   /** Bits[4:0], */
3946   vex_prefix |= SET_VEX_M;
3947   return vex_prefix;
3948 }
3949 
EmitVexPrefixByteOne(bool R,X86ManagedRegister operand,int SET_VEX_L,int SET_VEX_PP)3950 uint8_t X86Assembler::EmitVexPrefixByteOne(bool R,
3951                                            X86ManagedRegister operand,
3952                                            int SET_VEX_L,
3953                                            int SET_VEX_PP) {
3954   /**Vex Byte 1, */
3955   uint8_t vex_prefix = VEX_INIT;
3956   /** Bit[7] This bit needs to be set to '1'
3957   otherwise the instruction is LES or LDS */
3958   if (!R) {
3959     // R .
3960     vex_prefix |= SET_VEX_R;
3961   }
3962   /**Bits[6:3] - 'vvvv' the source or dest register specifier */
3963   if (operand.IsNoRegister()) {
3964     vex_prefix |= 0x78;
3965   } else if (operand.IsXmmRegister()) {
3966     XmmRegister vvvv = operand.AsXmmRegister();
3967     int inverted_reg = 15 - static_cast<int>(vvvv);
3968     uint8_t reg = static_cast<uint8_t>(inverted_reg);
3969     vex_prefix |= ((reg & 0x0F) << 3);
3970   } else if (operand.IsCpuRegister()) {
3971     Register vvvv = operand.AsCpuRegister();
3972     int inverted_reg = 15 - static_cast<int>(vvvv);
3973     uint8_t reg = static_cast<uint8_t>(inverted_reg);
3974     vex_prefix |= ((reg & 0x0F) << 3);
3975   }
3976   /** Bit[2] - "L" If VEX.L = 1 indicates 256-bit vector operation ,
3977   VEX.L = 0 indicates 128 bit vector operation */
3978   vex_prefix |= SET_VEX_L;
3979   /** Bits[1:0] -  "pp" */
3980   vex_prefix |= SET_VEX_PP;
3981   return vex_prefix;
3982 }
3983 
EmitVexPrefixByteTwo(bool W,X86ManagedRegister operand,int SET_VEX_L,int SET_VEX_PP)3984 uint8_t X86Assembler::EmitVexPrefixByteTwo(bool W,
3985                                            X86ManagedRegister operand,
3986                                            int SET_VEX_L,
3987                                            int SET_VEX_PP) {
3988   /** Vex Byte 2, */
3989   uint8_t vex_prefix = VEX_INIT;
3990   /** Bit[7] This bits needs to be set to '1' with default value.
3991   When using C4H form of VEX prefix, W value is ignored */
3992   if (W) {
3993     vex_prefix |= SET_VEX_W;
3994   }
3995   /** Bits[6:3] - 'vvvv' the source or dest register specifier */
3996   if (operand.IsXmmRegister()) {
3997     XmmRegister vvvv = operand.AsXmmRegister();
3998     int inverted_reg = 15 - static_cast<int>(vvvv);
3999     uint8_t reg = static_cast<uint8_t>(inverted_reg);
4000     vex_prefix |= ((reg & 0x0F) << 3);
4001   } else if (operand.IsCpuRegister()) {
4002     Register vvvv = operand.AsCpuRegister();
4003     int inverted_reg = 15 - static_cast<int>(vvvv);
4004     uint8_t reg = static_cast<uint8_t>(inverted_reg);
4005     vex_prefix |= ((reg & 0x0F) << 3);
4006   }
4007   /** Bit[2] - "L" If VEX.L = 1 indicates 256-bit vector operation ,
4008   VEX.L = 0 indicates 128 bit vector operation */
4009   vex_prefix |= SET_VEX_L;
4010   // Bits[1:0] -  "pp"
4011   vex_prefix |= SET_VEX_PP;
4012   return vex_prefix;
4013 }
4014 
EmitVexPrefixByteTwo(bool W,int SET_VEX_L,int SET_VEX_PP)4015 uint8_t X86Assembler::EmitVexPrefixByteTwo(bool W,
4016                                            int SET_VEX_L,
4017                                            int SET_VEX_PP) {
4018   /**Vex Byte 2, */
4019   uint8_t vex_prefix = VEX_INIT;
4020 
4021   /** Bit[7] This bits needs to be set to '1' with default value.
4022   When using C4H form of VEX prefix, W value is ignored */
4023   if (W) {
4024     vex_prefix |= SET_VEX_W;
4025   }
4026   /** Bits[6:3] - 'vvvv' the source or dest register specifier,
4027   if unused set 1111 */
4028   vex_prefix |= (0x0F << 3);
4029 
4030   /** Bit[2] - "L" If VEX.L = 1 indicates 256-bit vector operation ,
4031   VEX.L = 0 indicates 128 bit vector operation */
4032   vex_prefix |= SET_VEX_L;
4033 
4034   /** Bits[1:0] -  "pp" */
4035   if (SET_VEX_PP != SET_VEX_PP_NONE) {
4036     vex_prefix |= SET_VEX_PP;
4037   }
4038   return vex_prefix;
4039 }
4040 
4041 }  // namespace x86
4042 }  // namespace art
4043