1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define MSM_PIPE_NONE 0x00 26 #define MSM_PIPE_2D0 0x01 27 #define MSM_PIPE_2D1 0x02 28 #define MSM_PIPE_3D0 0x10 29 #define MSM_PIPE_ID_MASK 0xffff 30 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 31 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 32 struct drm_msm_timespec { 33 __s64 tv_sec; 34 __s64 tv_nsec; 35 }; 36 #define MSM_PARAM_GPU_ID 0x01 37 #define MSM_PARAM_GMEM_SIZE 0x02 38 #define MSM_PARAM_CHIP_ID 0x03 39 #define MSM_PARAM_MAX_FREQ 0x04 40 #define MSM_PARAM_TIMESTAMP 0x05 41 #define MSM_PARAM_GMEM_BASE 0x06 42 #define MSM_PARAM_NR_RINGS 0x07 43 #define MSM_PARAM_PP_PGTABLE 0x08 44 #define MSM_PARAM_FAULTS 0x09 45 struct drm_msm_param { 46 __u32 pipe; 47 __u32 param; 48 __u64 value; 49 }; 50 #define MSM_BO_SCANOUT 0x00000001 51 #define MSM_BO_GPU_READONLY 0x00000002 52 #define MSM_BO_CACHE_MASK 0x000f0000 53 #define MSM_BO_CACHED 0x00010000 54 #define MSM_BO_WC 0x00020000 55 #define MSM_BO_UNCACHED 0x00040000 56 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) 57 struct drm_msm_gem_new { 58 __u64 size; 59 __u32 flags; 60 __u32 handle; 61 }; 62 #define MSM_INFO_GET_OFFSET 0x00 63 #define MSM_INFO_GET_IOVA 0x01 64 #define MSM_INFO_SET_NAME 0x02 65 #define MSM_INFO_GET_NAME 0x03 66 struct drm_msm_gem_info { 67 __u32 handle; 68 __u32 info; 69 __u64 value; 70 __u32 len; 71 __u32 pad; 72 }; 73 #define MSM_PREP_READ 0x01 74 #define MSM_PREP_WRITE 0x02 75 #define MSM_PREP_NOSYNC 0x04 76 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 77 struct drm_msm_gem_cpu_prep { 78 __u32 handle; 79 __u32 op; 80 struct drm_msm_timespec timeout; 81 }; 82 struct drm_msm_gem_cpu_fini { 83 __u32 handle; 84 }; 85 struct drm_msm_gem_submit_reloc { 86 __u32 submit_offset; 87 __u32 or; 88 __s32 shift; 89 __u32 reloc_idx; 90 __u64 reloc_offset; 91 }; 92 #define MSM_SUBMIT_CMD_BUF 0x0001 93 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 94 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 95 struct drm_msm_gem_submit_cmd { 96 __u32 type; 97 __u32 submit_idx; 98 __u32 submit_offset; 99 __u32 size; 100 __u32 pad; 101 __u32 nr_relocs; 102 __u64 relocs; 103 }; 104 #define MSM_SUBMIT_BO_READ 0x0001 105 #define MSM_SUBMIT_BO_WRITE 0x0002 106 #define MSM_SUBMIT_BO_DUMP 0x0004 107 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP) 108 struct drm_msm_gem_submit_bo { 109 __u32 flags; 110 __u32 handle; 111 __u64 presumed; 112 }; 113 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 114 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 115 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 116 #define MSM_SUBMIT_SUDO 0x10000000 117 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | 0) 118 struct drm_msm_gem_submit { 119 __u32 flags; 120 __u32 fence; 121 __u32 nr_bos; 122 __u32 nr_cmds; 123 __u64 bos; 124 __u64 cmds; 125 __s32 fence_fd; 126 __u32 queueid; 127 }; 128 struct drm_msm_wait_fence { 129 __u32 fence; 130 __u32 pad; 131 struct drm_msm_timespec timeout; 132 __u32 queueid; 133 }; 134 #define MSM_MADV_WILLNEED 0 135 #define MSM_MADV_DONTNEED 1 136 #define __MSM_MADV_PURGED 2 137 struct drm_msm_gem_madvise { 138 __u32 handle; 139 __u32 madv; 140 __u32 retained; 141 }; 142 #define MSM_SUBMITQUEUE_FLAGS (0) 143 struct drm_msm_submitqueue { 144 __u32 flags; 145 __u32 prio; 146 __u32 id; 147 }; 148 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0 149 struct drm_msm_submitqueue_query { 150 __u64 data; 151 __u32 id; 152 __u32 param; 153 __u32 len; 154 __u32 pad; 155 }; 156 #define DRM_MSM_GET_PARAM 0x00 157 #define DRM_MSM_GEM_NEW 0x02 158 #define DRM_MSM_GEM_INFO 0x03 159 #define DRM_MSM_GEM_CPU_PREP 0x04 160 #define DRM_MSM_GEM_CPU_FINI 0x05 161 #define DRM_MSM_GEM_SUBMIT 0x06 162 #define DRM_MSM_WAIT_FENCE 0x07 163 #define DRM_MSM_GEM_MADVISE 0x08 164 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 165 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 166 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 167 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 168 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 169 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 170 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 171 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 172 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 173 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 174 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 175 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 176 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 177 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 178 #ifdef __cplusplus 179 } 180 #endif 181 #endif 182