1 #include <gtest/gtest.h> 2 3 #include <cstdint> 4 5 #include <cpuinfo.h> 6 extern "C" { 7 #include <arm/api.h> 8 } 9 10 11 TEST(QUALCOMM, snapdragon_410_msm) { 12 const struct cpuinfo_arm_chipset chipset = { 13 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 14 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 15 .model = 8916, 16 }; 17 18 struct cpuinfo_cache l1i = { 0 }; 19 struct cpuinfo_cache l1d = { 0 }; 20 struct cpuinfo_cache l2 = { 0 }; 21 struct cpuinfo_cache l3 = { 0 }; 22 cpuinfo_arm_decode_cache( 23 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD030), 24 &chipset, 0, 8, 25 &l1i, &l1d, &l2, &l3); 26 EXPECT_EQ(32 * 1024, l1i.size); 27 EXPECT_EQ(32 * 1024, l1d.size); 28 EXPECT_EQ(512 * 1024, l2.size); 29 EXPECT_EQ(0, l3.size); 30 } 31 32 TEST(QUALCOMM, snapdragon_410_apq) { 33 const struct cpuinfo_arm_chipset chipset = { 34 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 35 .series = cpuinfo_arm_chipset_series_qualcomm_apq, 36 .model = 8016, 37 }; 38 39 struct cpuinfo_cache l1i = { 0 }; 40 struct cpuinfo_cache l1d = { 0 }; 41 struct cpuinfo_cache l2 = { 0 }; 42 struct cpuinfo_cache l3 = { 0 }; 43 cpuinfo_arm_decode_cache( 44 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD030), 45 &chipset, 0, 8, 46 &l1i, &l1d, &l2, &l3); 47 EXPECT_EQ(32 * 1024, l1i.size); 48 EXPECT_EQ(32 * 1024, l1d.size); 49 EXPECT_EQ(512 * 1024, l2.size); 50 EXPECT_EQ(0, l3.size); 51 } 52 53 TEST(QUALCOMM, snapdragon_415) { 54 const struct cpuinfo_arm_chipset chipset = { 55 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 56 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 57 .model = 8929, 58 }; 59 60 for (uint32_t cluster = 0; cluster < 2; cluster++) { 61 struct cpuinfo_cache l1i = { 0 }; 62 struct cpuinfo_cache l1d = { 0 }; 63 struct cpuinfo_cache l2 = { 0 }; 64 struct cpuinfo_cache l3 = { 0 }; 65 cpuinfo_arm_decode_cache( 66 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD031), 67 &chipset, cluster, 8, 68 &l1i, &l1d, &l2, &l3); 69 EXPECT_EQ(32 * 1024, l1i.size); 70 EXPECT_EQ(32 * 1024, l1d.size); 71 EXPECT_EQ(512 * 1024, l2.size); 72 EXPECT_EQ(0, l3.size); 73 } 74 } 75 76 TEST(QUALCOMM, snapdragon_425) { 77 const struct cpuinfo_arm_chipset chipset = { 78 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 79 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 80 .model = 8917, 81 }; 82 83 struct cpuinfo_cache l1i = { 0 }; 84 struct cpuinfo_cache l1d = { 0 }; 85 struct cpuinfo_cache l2 = { 0 }; 86 struct cpuinfo_cache l3 = { 0 }; 87 cpuinfo_arm_decode_cache( 88 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 89 &chipset, 0, 8, 90 &l1i, &l1d, &l2, &l3); 91 EXPECT_EQ(32 * 1024, l1i.size); 92 EXPECT_EQ(32 * 1024, l1d.size); 93 EXPECT_EQ(512 * 1024, l2.size); 94 EXPECT_EQ(0, l3.size); 95 } 96 97 TEST(QUALCOMM, snapdragon_427) { 98 const struct cpuinfo_arm_chipset chipset = { 99 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 100 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 101 .model = 8920, 102 }; 103 104 struct cpuinfo_cache l1i = { 0 }; 105 struct cpuinfo_cache l1d = { 0 }; 106 struct cpuinfo_cache l2 = { 0 }; 107 struct cpuinfo_cache l3 = { 0 }; 108 cpuinfo_arm_decode_cache( 109 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 110 &chipset, 0, 8, 111 &l1i, &l1d, &l2, &l3); 112 EXPECT_EQ(32 * 1024, l1i.size); 113 EXPECT_EQ(32 * 1024, l1d.size); 114 EXPECT_EQ(512 * 1024, l2.size); 115 EXPECT_EQ(0, l3.size); 116 } 117 118 TEST(QUALCOMM, snapdragon_430) { 119 const struct cpuinfo_arm_chipset chipset = { 120 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 121 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 122 .model = 8937, 123 }; 124 125 struct cpuinfo_cache big_l1i = { 0 }; 126 struct cpuinfo_cache big_l1d = { 0 }; 127 struct cpuinfo_cache big_l2 = { 0 }; 128 struct cpuinfo_cache big_l3 = { 0 }; 129 cpuinfo_arm_decode_cache( 130 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 131 &chipset, 0, 8, 132 &big_l1i, &big_l1d, &big_l2, &big_l3); 133 134 struct cpuinfo_cache little_l1i = { 0 }; 135 struct cpuinfo_cache little_l1d = { 0 }; 136 struct cpuinfo_cache little_l2 = { 0 }; 137 struct cpuinfo_cache little_l3 = { 0 }; 138 cpuinfo_arm_decode_cache( 139 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 140 &chipset, 1, 8, 141 &little_l1i, &little_l1d, &little_l2, &little_l3); 142 143 EXPECT_EQ(32 * 1024, big_l1i.size); 144 EXPECT_EQ(32 * 1024, big_l1d.size); 145 EXPECT_EQ(1024 * 1024, big_l2.size); 146 EXPECT_EQ(0, big_l3.size); 147 148 EXPECT_EQ(32 * 1024, little_l1i.size); 149 EXPECT_EQ(32 * 1024, little_l1d.size); 150 EXPECT_EQ(512 * 1024, little_l2.size); 151 EXPECT_EQ(0, little_l3.size); 152 } 153 154 TEST(QUALCOMM, snapdragon_435) { 155 const struct cpuinfo_arm_chipset chipset = { 156 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 157 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 158 .model = 8940, 159 }; 160 161 struct cpuinfo_cache big_l1i = { 0 }; 162 struct cpuinfo_cache big_l1d = { 0 }; 163 struct cpuinfo_cache big_l2 = { 0 }; 164 struct cpuinfo_cache big_l3 = { 0 }; 165 cpuinfo_arm_decode_cache( 166 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 167 &chipset, 0, 8, 168 &big_l1i, &big_l1d, &big_l2, &big_l3); 169 170 struct cpuinfo_cache little_l1i = { 0 }; 171 struct cpuinfo_cache little_l1d = { 0 }; 172 struct cpuinfo_cache little_l2 = { 0 }; 173 struct cpuinfo_cache little_l3 = { 0 }; 174 cpuinfo_arm_decode_cache( 175 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 176 &chipset, 1, 8, 177 &little_l1i, &little_l1d, &little_l2, &little_l3); 178 179 EXPECT_EQ(32 * 1024, big_l1i.size); 180 EXPECT_EQ(32 * 1024, big_l1d.size); 181 EXPECT_EQ(1024 * 1024, big_l2.size); 182 EXPECT_EQ(0, big_l3.size); 183 184 EXPECT_EQ(32 * 1024, little_l1i.size); 185 EXPECT_EQ(32 * 1024, little_l1d.size); 186 EXPECT_EQ(512 * 1024, little_l2.size); 187 EXPECT_EQ(0, little_l3.size); 188 } 189 190 TEST(QUALCOMM, snapdragon_450) { 191 const struct cpuinfo_arm_chipset chipset = { 192 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 193 .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, 194 .model = 450, 195 }; 196 197 struct cpuinfo_cache big_l1i = { 0 }; 198 struct cpuinfo_cache big_l1d = { 0 }; 199 struct cpuinfo_cache big_l2 = { 0 }; 200 struct cpuinfo_cache big_l3 = { 0 }; 201 cpuinfo_arm_decode_cache( 202 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 203 &chipset, 0, 8, 204 &big_l1i, &big_l1d, &big_l2, &big_l3); 205 206 struct cpuinfo_cache little_l1i = { 0 }; 207 struct cpuinfo_cache little_l1d = { 0 }; 208 struct cpuinfo_cache little_l2 = { 0 }; 209 struct cpuinfo_cache little_l3 = { 0 }; 210 cpuinfo_arm_decode_cache( 211 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 212 &chipset, 1, 8, 213 &little_l1i, &little_l1d, &little_l2, &little_l3); 214 215 EXPECT_EQ(32 * 1024, big_l1i.size); 216 EXPECT_EQ(32 * 1024, big_l1d.size); 217 EXPECT_EQ(1024 * 1024, big_l2.size); 218 EXPECT_EQ(0, big_l3.size); 219 220 EXPECT_EQ(32 * 1024, little_l1i.size); 221 EXPECT_EQ(32 * 1024, little_l1d.size); 222 EXPECT_EQ(512 * 1024, little_l2.size); 223 EXPECT_EQ(0, little_l3.size); 224 } 225 226 TEST(QUALCOMM, snapdragon_617) { 227 const struct cpuinfo_arm_chipset chipset = { 228 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 229 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 230 .model = 8952, 231 }; 232 233 struct cpuinfo_cache big_l1i = { 0 }; 234 struct cpuinfo_cache big_l1d = { 0 }; 235 struct cpuinfo_cache big_l2 = { 0 }; 236 struct cpuinfo_cache big_l3 = { 0 }; 237 cpuinfo_arm_decode_cache( 238 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 239 &chipset, 0, 8, 240 &big_l1i, &big_l1d, &big_l2, &big_l3); 241 242 struct cpuinfo_cache little_l1i = { 0 }; 243 struct cpuinfo_cache little_l1d = { 0 }; 244 struct cpuinfo_cache little_l2 = { 0 }; 245 struct cpuinfo_cache little_l3 = { 0 }; 246 cpuinfo_arm_decode_cache( 247 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 248 &chipset, 1, 8, 249 &little_l1i, &little_l1d, &little_l2, &little_l3); 250 251 EXPECT_EQ(32 * 1024, big_l1i.size); 252 EXPECT_EQ(32 * 1024, big_l1d.size); 253 EXPECT_EQ(512 * 1024, big_l2.size); 254 EXPECT_EQ(0, big_l3.size); 255 256 EXPECT_EQ(32 * 1024, little_l1i.size); 257 EXPECT_EQ(32 * 1024, little_l1d.size); 258 EXPECT_EQ(256 * 1024, little_l2.size); 259 EXPECT_EQ(0, little_l3.size); 260 } 261 262 TEST(QUALCOMM, snapdragon_625) { 263 const struct cpuinfo_arm_chipset chipset = { 264 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 265 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 266 .model = 8953, 267 }; 268 269 struct cpuinfo_cache big_l1i = { 0 }; 270 struct cpuinfo_cache big_l1d = { 0 }; 271 struct cpuinfo_cache big_l2 = { 0 }; 272 struct cpuinfo_cache big_l3 = { 0 }; 273 cpuinfo_arm_decode_cache( 274 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 275 &chipset, 0, 8, 276 &big_l1i, &big_l1d, &big_l2, &big_l3); 277 278 struct cpuinfo_cache little_l1i = { 0 }; 279 struct cpuinfo_cache little_l1d = { 0 }; 280 struct cpuinfo_cache little_l2 = { 0 }; 281 struct cpuinfo_cache little_l3 = { 0 }; 282 cpuinfo_arm_decode_cache( 283 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 284 &chipset, 1, 8, 285 &little_l1i, &little_l1d, &little_l2, &little_l3); 286 287 EXPECT_EQ(32 * 1024, big_l1i.size); 288 EXPECT_EQ(32 * 1024, big_l1d.size); 289 EXPECT_EQ(1024 * 1024, big_l2.size); 290 EXPECT_EQ(0, big_l3.size); 291 292 EXPECT_EQ(32 * 1024, little_l1i.size); 293 EXPECT_EQ(32 * 1024, little_l1d.size); 294 EXPECT_EQ(512 * 1024, little_l2.size); 295 EXPECT_EQ(0, little_l3.size); 296 } 297 298 TEST(QUALCOMM, snapdragon_626) { 299 const struct cpuinfo_arm_chipset chipset = { 300 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 301 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 302 .model = 8953, 303 .suffix = { 304 [0] = 'P', 305 [1] = 'R', 306 [2] = 'O', 307 }, 308 }; 309 310 struct cpuinfo_cache big_l1i = { 0 }; 311 struct cpuinfo_cache big_l1d = { 0 }; 312 struct cpuinfo_cache big_l2 = { 0 }; 313 struct cpuinfo_cache big_l3 = { 0 }; 314 cpuinfo_arm_decode_cache( 315 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 316 &chipset, 0, 8, 317 &big_l1i, &big_l1d, &big_l2, &big_l3); 318 319 struct cpuinfo_cache little_l1i = { 0 }; 320 struct cpuinfo_cache little_l1d = { 0 }; 321 struct cpuinfo_cache little_l2 = { 0 }; 322 struct cpuinfo_cache little_l3 = { 0 }; 323 cpuinfo_arm_decode_cache( 324 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 325 &chipset, 1, 8, 326 &little_l1i, &little_l1d, &little_l2, &little_l3); 327 328 EXPECT_EQ(32 * 1024, big_l1i.size); 329 EXPECT_EQ(32 * 1024, big_l1d.size); 330 EXPECT_EQ(1024 * 1024, big_l2.size); 331 EXPECT_EQ(0, big_l3.size); 332 333 EXPECT_EQ(32 * 1024, little_l1i.size); 334 EXPECT_EQ(32 * 1024, little_l1d.size); 335 EXPECT_EQ(512 * 1024, little_l2.size); 336 EXPECT_EQ(0, little_l3.size); 337 } 338 339 TEST(QUALCOMM, snapdragon_630) { 340 const struct cpuinfo_arm_chipset chipset = { 341 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 342 .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, 343 .model = 630, 344 }; 345 346 struct cpuinfo_cache big_l1i = { 0 }; 347 struct cpuinfo_cache big_l1d = { 0 }; 348 struct cpuinfo_cache big_l2 = { 0 }; 349 struct cpuinfo_cache big_l3 = { 0 }; 350 cpuinfo_arm_decode_cache( 351 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), 352 &chipset, 0, 8, 353 &big_l1i, &big_l1d, &big_l2, &big_l3); 354 355 struct cpuinfo_cache little_l1i = { 0 }; 356 struct cpuinfo_cache little_l1d = { 0 }; 357 struct cpuinfo_cache little_l2 = { 0 }; 358 struct cpuinfo_cache little_l3 = { 0 }; 359 cpuinfo_arm_decode_cache( 360 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), 361 &chipset, 1, 8, 362 &little_l1i, &little_l1d, &little_l2, &little_l3); 363 364 EXPECT_EQ(32 * 1024, big_l1i.size); 365 EXPECT_EQ(32 * 1024, big_l1d.size); 366 EXPECT_EQ(1024 * 1024, big_l2.size); 367 EXPECT_EQ(0, big_l3.size); 368 369 EXPECT_EQ(32 * 1024, little_l1i.size); 370 EXPECT_EQ(32 * 1024, little_l1d.size); 371 EXPECT_EQ(512 * 1024, little_l2.size); 372 EXPECT_EQ(0, little_l3.size); 373 } 374 375 TEST(QUALCOMM, snapdragon_636) { 376 const struct cpuinfo_arm_chipset chipset = { 377 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 378 .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, 379 .model = 636, 380 }; 381 382 struct cpuinfo_cache big_l1i = { 0 }; 383 struct cpuinfo_cache big_l1d = { 0 }; 384 struct cpuinfo_cache big_l2 = { 0 }; 385 struct cpuinfo_cache big_l3 = { 0 }; 386 cpuinfo_arm_decode_cache( 387 cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x51AF8002), 388 &chipset, 0, 8, 389 &big_l1i, &big_l1d, &big_l2, &big_l3); 390 391 struct cpuinfo_cache little_l1i = { 0 }; 392 struct cpuinfo_cache little_l1d = { 0 }; 393 struct cpuinfo_cache little_l2 = { 0 }; 394 struct cpuinfo_cache little_l3 = { 0 }; 395 cpuinfo_arm_decode_cache( 396 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), 397 &chipset, 1, 8, 398 &little_l1i, &little_l1d, &little_l2, &little_l3); 399 400 EXPECT_EQ(64 * 1024, big_l1i.size); 401 EXPECT_EQ(64 * 1024, big_l1d.size); 402 EXPECT_EQ(1024 * 1024, big_l2.size); 403 EXPECT_EQ(0, big_l3.size); 404 405 EXPECT_EQ(32 * 1024, little_l1i.size); 406 EXPECT_EQ(32 * 1024, little_l1d.size); 407 EXPECT_EQ(1024 * 1024, little_l2.size); 408 EXPECT_EQ(0, little_l3.size); 409 } 410 411 TEST(QUALCOMM, snapdragon_650) { 412 const struct cpuinfo_arm_chipset chipset = { 413 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 414 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 415 .model = 8956, 416 }; 417 418 struct cpuinfo_cache big_l1i = { 0 }; 419 struct cpuinfo_cache big_l1d = { 0 }; 420 struct cpuinfo_cache big_l2 = { 0 }; 421 struct cpuinfo_cache big_l3 = { 0 }; 422 cpuinfo_arm_decode_cache( 423 cpuinfo_uarch_cortex_a72, 2, UINT32_C(0x410FD080), 424 &chipset, 0, 8, 425 &big_l1i, &big_l1d, &big_l2, &big_l3); 426 427 struct cpuinfo_cache little_l1i = { 0 }; 428 struct cpuinfo_cache little_l1d = { 0 }; 429 struct cpuinfo_cache little_l2 = { 0 }; 430 struct cpuinfo_cache little_l3 = { 0 }; 431 cpuinfo_arm_decode_cache( 432 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 433 &chipset, 1, 8, 434 &little_l1i, &little_l1d, &little_l2, &little_l3); 435 436 EXPECT_EQ(48 * 1024, big_l1i.size); 437 EXPECT_EQ(32 * 1024, big_l1d.size); 438 EXPECT_EQ(1024 * 1024, big_l2.size); 439 EXPECT_EQ(0, big_l3.size); 440 441 EXPECT_EQ(32 * 1024, little_l1i.size); 442 EXPECT_EQ(32 * 1024, little_l1d.size); 443 EXPECT_EQ(512 * 1024, little_l2.size); 444 EXPECT_EQ(0, little_l3.size); 445 } 446 447 TEST(QUALCOMM, snapdragon_652) { 448 const struct cpuinfo_arm_chipset chipset = { 449 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 450 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 451 .model = 8976, 452 }; 453 454 struct cpuinfo_cache big_l1i = { 0 }; 455 struct cpuinfo_cache big_l1d = { 0 }; 456 struct cpuinfo_cache big_l2 = { 0 }; 457 struct cpuinfo_cache big_l3 = { 0 }; 458 cpuinfo_arm_decode_cache( 459 cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD080), 460 &chipset, 0, 8, 461 &big_l1i, &big_l1d, &big_l2, &big_l3); 462 463 struct cpuinfo_cache little_l1i = { 0 }; 464 struct cpuinfo_cache little_l1d = { 0 }; 465 struct cpuinfo_cache little_l2 = { 0 }; 466 struct cpuinfo_cache little_l3 = { 0 }; 467 cpuinfo_arm_decode_cache( 468 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 469 &chipset, 1, 8, 470 &little_l1i, &little_l1d, &little_l2, &little_l3); 471 472 EXPECT_EQ(48 * 1024, big_l1i.size); 473 EXPECT_EQ(32 * 1024, big_l1d.size); 474 EXPECT_EQ(1024 * 1024, big_l2.size); 475 EXPECT_EQ(0, big_l3.size); 476 477 EXPECT_EQ(32 * 1024, little_l1i.size); 478 EXPECT_EQ(32 * 1024, little_l1d.size); 479 EXPECT_EQ(512 * 1024, little_l2.size); 480 EXPECT_EQ(0, little_l3.size); 481 } 482 483 TEST(QUALCOMM, snapdragon_653) { 484 const struct cpuinfo_arm_chipset chipset = { 485 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 486 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 487 .model = 8976, 488 .suffix = { 489 [0] = 'P', 490 [1] = 'R', 491 [2] = 'O', 492 }, 493 }; 494 495 struct cpuinfo_cache big_l1i = { 0 }; 496 struct cpuinfo_cache big_l1d = { 0 }; 497 struct cpuinfo_cache big_l2 = { 0 }; 498 struct cpuinfo_cache big_l3 = { 0 }; 499 cpuinfo_arm_decode_cache( 500 cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD080), 501 &chipset, 0, 8, 502 &big_l1i, &big_l1d, &big_l2, &big_l3); 503 504 struct cpuinfo_cache little_l1i = { 0 }; 505 struct cpuinfo_cache little_l1d = { 0 }; 506 struct cpuinfo_cache little_l2 = { 0 }; 507 struct cpuinfo_cache little_l3 = { 0 }; 508 cpuinfo_arm_decode_cache( 509 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 510 &chipset, 1, 8, 511 &little_l1i, &little_l1d, &little_l2, &little_l3); 512 513 EXPECT_EQ(48 * 1024, big_l1i.size); 514 EXPECT_EQ(32 * 1024, big_l1d.size); 515 EXPECT_EQ(1024 * 1024, big_l2.size); 516 EXPECT_EQ(0, big_l3.size); 517 518 EXPECT_EQ(32 * 1024, little_l1i.size); 519 EXPECT_EQ(32 * 1024, little_l1d.size); 520 EXPECT_EQ(512 * 1024, little_l2.size); 521 EXPECT_EQ(0, little_l3.size); 522 } 523 524 TEST(QUALCOMM, snapdragon_660) { 525 const struct cpuinfo_arm_chipset chipset = { 526 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 527 .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, 528 .model = 660, 529 }; 530 531 struct cpuinfo_cache big_l1i = { 0 }; 532 struct cpuinfo_cache big_l1d = { 0 }; 533 struct cpuinfo_cache big_l2 = { 0 }; 534 struct cpuinfo_cache big_l3 = { 0 }; 535 cpuinfo_arm_decode_cache( 536 cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x51AF8002), 537 &chipset, 0, 8, 538 &big_l1i, &big_l1d, &big_l2, &big_l3); 539 540 struct cpuinfo_cache little_l1i = { 0 }; 541 struct cpuinfo_cache little_l1d = { 0 }; 542 struct cpuinfo_cache little_l2 = { 0 }; 543 struct cpuinfo_cache little_l3 = { 0 }; 544 cpuinfo_arm_decode_cache( 545 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), 546 &chipset, 1, 8, 547 &little_l1i, &little_l1d, &little_l2, &little_l3); 548 549 EXPECT_EQ(64 * 1024, big_l1i.size); 550 EXPECT_EQ(64 * 1024, big_l1d.size); 551 EXPECT_EQ(1024 * 1024, big_l2.size); 552 EXPECT_EQ(0, big_l3.size); 553 554 EXPECT_EQ(32 * 1024, little_l1i.size); 555 EXPECT_EQ(32 * 1024, little_l1d.size); 556 EXPECT_EQ(1024 * 1024, little_l2.size); 557 EXPECT_EQ(0, little_l3.size); 558 } 559 560 TEST(QUALCOMM, snapdragon_808) { 561 const struct cpuinfo_arm_chipset chipset = { 562 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 563 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 564 .model = 8992, 565 }; 566 567 struct cpuinfo_cache big_l1i = { 0 }; 568 struct cpuinfo_cache big_l1d = { 0 }; 569 struct cpuinfo_cache big_l2 = { 0 }; 570 struct cpuinfo_cache big_l3 = { 0 }; 571 cpuinfo_arm_decode_cache( 572 cpuinfo_uarch_cortex_a57, 2, UINT32_C(0x410FD033), 573 &chipset, 0, 8, 574 &big_l1i, &big_l1d, &big_l2, &big_l3); 575 576 struct cpuinfo_cache little_l1i = { 0 }; 577 struct cpuinfo_cache little_l1d = { 0 }; 578 struct cpuinfo_cache little_l2 = { 0 }; 579 struct cpuinfo_cache little_l3 = { 0 }; 580 cpuinfo_arm_decode_cache( 581 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), 582 &chipset, 1, 8, 583 &little_l1i, &little_l1d, &little_l2, &little_l3); 584 585 EXPECT_EQ(48 * 1024, big_l1i.size); 586 EXPECT_EQ(32 * 1024, big_l1d.size); 587 EXPECT_EQ(1024 * 1024, big_l2.size); 588 EXPECT_EQ(0, big_l3.size); 589 590 EXPECT_EQ(32 * 1024, little_l1i.size); 591 EXPECT_EQ(32 * 1024, little_l1d.size); 592 EXPECT_EQ(512 * 1024, little_l2.size); 593 EXPECT_EQ(0, little_l3.size); 594 } 595 596 TEST(QUALCOMM, snapdragon_810) { 597 const struct cpuinfo_arm_chipset chipset = { 598 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 599 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 600 .model = 8994, 601 }; 602 603 struct cpuinfo_cache big_l1i = { 0 }; 604 struct cpuinfo_cache big_l1d = { 0 }; 605 struct cpuinfo_cache big_l2 = { 0 }; 606 struct cpuinfo_cache big_l3 = { 0 }; 607 cpuinfo_arm_decode_cache( 608 cpuinfo_uarch_cortex_a57, 4, UINT32_C(0x410FD033), 609 &chipset, 0, 8, 610 &big_l1i, &big_l1d, &big_l2, &big_l3); 611 612 struct cpuinfo_cache little_l1i = { 0 }; 613 struct cpuinfo_cache little_l1d = { 0 }; 614 struct cpuinfo_cache little_l2 = { 0 }; 615 struct cpuinfo_cache little_l3 = { 0 }; 616 cpuinfo_arm_decode_cache( 617 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), 618 &chipset, 1, 8, 619 &little_l1i, &little_l1d, &little_l2, &little_l3); 620 621 EXPECT_EQ(48 * 1024, big_l1i.size); 622 EXPECT_EQ(32 * 1024, big_l1d.size); 623 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 624 EXPECT_EQ(0, big_l3.size); 625 626 EXPECT_EQ(32 * 1024, little_l1i.size); 627 EXPECT_EQ(32 * 1024, little_l1d.size); 628 EXPECT_EQ(512 * 1024, little_l2.size); 629 EXPECT_EQ(0, little_l3.size); 630 } 631 632 TEST(QUALCOMM, snapdragon_820) { 633 const struct cpuinfo_arm_chipset chipset = { 634 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 635 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 636 .model = 8996, 637 }; 638 639 struct cpuinfo_cache big_l1i = { 0 }; 640 struct cpuinfo_cache big_l1d = { 0 }; 641 struct cpuinfo_cache big_l2 = { 0 }; 642 struct cpuinfo_cache big_l3 = { 0 }; 643 cpuinfo_arm_decode_cache( 644 cpuinfo_uarch_kryo, 4, UINT32_C(0x511F2052), 645 &chipset, 0, 8, 646 &big_l1i, &big_l1d, &big_l2, &big_l3); 647 648 struct cpuinfo_cache little_l1i = { 0 }; 649 struct cpuinfo_cache little_l1d = { 0 }; 650 struct cpuinfo_cache little_l2 = { 0 }; 651 struct cpuinfo_cache little_l3 = { 0 }; 652 cpuinfo_arm_decode_cache( 653 cpuinfo_uarch_kryo, 4, UINT32_C(0x511F2112), 654 &chipset, 1, 8, 655 &little_l1i, &little_l1d, &little_l2, &little_l3); 656 657 EXPECT_EQ(32 * 1024, big_l1i.size); 658 EXPECT_EQ(24 * 1024, big_l1d.size); 659 EXPECT_EQ(1024 * 1024, big_l2.size); 660 EXPECT_EQ(0, big_l3.size); 661 662 EXPECT_EQ(32 * 1024, little_l1i.size); 663 EXPECT_EQ(24 * 1024, little_l1d.size); 664 EXPECT_EQ(512 * 1024, little_l2.size); 665 EXPECT_EQ(0, little_l3.size); 666 } 667 668 TEST(QUALCOMM, snapdragon_821) { 669 const struct cpuinfo_arm_chipset chipset = { 670 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 671 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 672 .model = 8996, 673 .suffix = { 674 [0] = 'P', 675 [1] = 'R', 676 [2] = 'O', 677 [3] = '-', 678 [4] = 'A', 679 [5] = 'C', 680 }, 681 }; 682 683 struct cpuinfo_cache big_l1i = { 0 }; 684 struct cpuinfo_cache big_l1d = { 0 }; 685 struct cpuinfo_cache big_l2 = { 0 }; 686 struct cpuinfo_cache big_l3 = { 0 }; 687 cpuinfo_arm_decode_cache( 688 cpuinfo_uarch_kryo, 4, UINT32_C(0x512F2051), 689 &chipset, 0, 8, 690 &big_l1i, &big_l1d, &big_l2, &big_l3); 691 692 struct cpuinfo_cache little_l1i = { 0 }; 693 struct cpuinfo_cache little_l1d = { 0 }; 694 struct cpuinfo_cache little_l2 = { 0 }; 695 struct cpuinfo_cache little_l3 = { 0 }; 696 cpuinfo_arm_decode_cache( 697 cpuinfo_uarch_kryo, 4, UINT32_C(0x512F2011), 698 &chipset, 1, 8, 699 &little_l1i, &little_l1d, &little_l2, &little_l3); 700 701 EXPECT_EQ(32 * 1024, big_l1i.size); 702 EXPECT_EQ(24 * 1024, big_l1d.size); 703 EXPECT_EQ(1024 * 1024, big_l2.size); 704 EXPECT_EQ(0, big_l3.size); 705 706 EXPECT_EQ(32 * 1024, little_l1i.size); 707 EXPECT_EQ(24 * 1024, little_l1d.size); 708 EXPECT_EQ(512 * 1024, little_l2.size); 709 EXPECT_EQ(0, little_l3.size); 710 } 711 712 TEST(QUALCOMM, snapdragon_835) { 713 const struct cpuinfo_arm_chipset chipset = { 714 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 715 .series = cpuinfo_arm_chipset_series_qualcomm_msm, 716 .model = 8998, 717 }; 718 719 struct cpuinfo_cache big_l1i = { 0 }; 720 struct cpuinfo_cache big_l1d = { 0 }; 721 struct cpuinfo_cache big_l2 = { 0 }; 722 struct cpuinfo_cache big_l3 = { 0 }; 723 cpuinfo_arm_decode_cache( 724 cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x51AF8001), 725 &chipset, 0, 8, 726 &big_l1i, &big_l1d, &big_l2, &big_l3); 727 728 struct cpuinfo_cache little_l1i = { 0 }; 729 struct cpuinfo_cache little_l1d = { 0 }; 730 struct cpuinfo_cache little_l2 = { 0 }; 731 struct cpuinfo_cache little_l3 = { 0 }; 732 cpuinfo_arm_decode_cache( 733 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), 734 &chipset, 1, 8, 735 &little_l1i, &little_l1d, &little_l2, &little_l3); 736 737 EXPECT_EQ(64 * 1024, big_l1i.size); 738 EXPECT_EQ(64 * 1024, big_l1d.size); 739 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 740 EXPECT_EQ(0, big_l3.size); 741 742 EXPECT_EQ(32 * 1024, little_l1i.size); 743 EXPECT_EQ(32 * 1024, little_l1d.size); 744 EXPECT_EQ(1024 * 1024, little_l2.size); 745 EXPECT_EQ(0, little_l3.size); 746 } 747 748 TEST(QUALCOMM, snapdragon_845) { 749 const struct cpuinfo_arm_chipset chipset = { 750 .vendor = cpuinfo_arm_chipset_vendor_qualcomm, 751 .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, 752 .model = 845, 753 }; 754 755 struct cpuinfo_cache big_l1i = { 0 }; 756 struct cpuinfo_cache big_l1d = { 0 }; 757 struct cpuinfo_cache big_l2 = { 0 }; 758 struct cpuinfo_cache big_l3 = { 0 }; 759 cpuinfo_arm_decode_cache( 760 cpuinfo_uarch_cortex_a75, 4, UINT32_C(0x518F802D), 761 &chipset, 0, 8, 762 &big_l1i, &big_l1d, &big_l2, &big_l3); 763 764 struct cpuinfo_cache little_l1i = { 0 }; 765 struct cpuinfo_cache little_l1d = { 0 }; 766 struct cpuinfo_cache little_l2 = { 0 }; 767 struct cpuinfo_cache little_l3 = { 0 }; 768 cpuinfo_arm_decode_cache( 769 cpuinfo_uarch_cortex_a55, 4, UINT32_C(0x518F803C), 770 &chipset, 1, 8, 771 &little_l1i, &little_l1d, &little_l2, &little_l3); 772 773 EXPECT_EQ(64 * 1024, big_l1i.size); 774 EXPECT_EQ(64 * 1024, big_l1d.size); 775 EXPECT_EQ(256 * 1024, big_l2.size); 776 EXPECT_EQ(2 * 1024 * 1024, big_l3.size); 777 778 EXPECT_EQ(32 * 1024, little_l1i.size); 779 EXPECT_EQ(32 * 1024, little_l1d.size); 780 EXPECT_EQ(128 * 1024, little_l2.size); 781 EXPECT_EQ(2 * 1024 * 1024, little_l3.size); 782 } 783 784 TEST(SAMSUNG, exynos_7885) { 785 const struct cpuinfo_arm_chipset chipset = { 786 .vendor = cpuinfo_arm_chipset_vendor_samsung, 787 .series = cpuinfo_arm_chipset_series_samsung_exynos, 788 .model = 7885, 789 }; 790 791 struct cpuinfo_cache big_l1i = { 0 }; 792 struct cpuinfo_cache big_l1d = { 0 }; 793 struct cpuinfo_cache big_l2 = { 0 }; 794 struct cpuinfo_cache big_l3 = { 0 }; 795 cpuinfo_arm_decode_cache( 796 cpuinfo_uarch_cortex_a73, 2, UINT32_C(0x410FD092), 797 &chipset, 0, 8, 798 &big_l1i, &big_l1d, &big_l2, &big_l3); 799 800 struct cpuinfo_cache little_l1i = { 0 }; 801 struct cpuinfo_cache little_l1d = { 0 }; 802 struct cpuinfo_cache little_l2 = { 0 }; 803 struct cpuinfo_cache little_l3 = { 0 }; 804 cpuinfo_arm_decode_cache( 805 cpuinfo_uarch_cortex_a53, 6, UINT32_C(0x410FD034), 806 &chipset, 1, 8, 807 &little_l1i, &little_l1d, &little_l2, &little_l3); 808 809 EXPECT_EQ(64 * 1024, big_l1i.size); 810 EXPECT_EQ(32 * 1024, big_l1d.size); 811 EXPECT_EQ(512 * 1024, big_l2.size); 812 EXPECT_EQ(0, big_l3.size); 813 814 EXPECT_EQ(32 * 1024, little_l1i.size); 815 EXPECT_EQ(32 * 1024, little_l1d.size); 816 EXPECT_EQ(256 * 1024, little_l2.size); 817 EXPECT_EQ(0, little_l3.size); 818 } 819 820 TEST(SAMSUNG, exynos_8890) { 821 const struct cpuinfo_arm_chipset chipset = { 822 .vendor = cpuinfo_arm_chipset_vendor_samsung, 823 .series = cpuinfo_arm_chipset_series_samsung_exynos, 824 .model = 8890, 825 }; 826 827 struct cpuinfo_cache big_l1i = { 0 }; 828 struct cpuinfo_cache big_l1d = { 0 }; 829 struct cpuinfo_cache big_l2 = { 0 }; 830 struct cpuinfo_cache big_l3 = { 0 }; 831 cpuinfo_arm_decode_cache( 832 cpuinfo_uarch_mongoose_m1, 4, UINT32_C(0x531F0011), 833 &chipset, 0, 8, 834 &big_l1i, &big_l1d, &big_l2, &big_l3); 835 836 struct cpuinfo_cache little_l1i = { 0 }; 837 struct cpuinfo_cache little_l1d = { 0 }; 838 struct cpuinfo_cache little_l2 = { 0 }; 839 struct cpuinfo_cache little_l3 = { 0 }; 840 cpuinfo_arm_decode_cache( 841 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 842 &chipset, 1, 8, 843 &little_l1i, &little_l1d, &little_l2, &little_l3); 844 845 EXPECT_EQ(64 * 1024, big_l1i.size); 846 EXPECT_EQ(32 * 1024, big_l1d.size); 847 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 848 EXPECT_EQ(0, big_l3.size); 849 850 EXPECT_EQ(32 * 1024, little_l1i.size); 851 EXPECT_EQ(32 * 1024, little_l1d.size); 852 EXPECT_EQ(256 * 1024, little_l2.size); 853 EXPECT_EQ(0, little_l3.size); 854 } 855 856 TEST(SAMSUNG, exynos_8895) { 857 const struct cpuinfo_arm_chipset chipset = { 858 .vendor = cpuinfo_arm_chipset_vendor_samsung, 859 .series = cpuinfo_arm_chipset_series_samsung_exynos, 860 .model = 8890, 861 }; 862 863 struct cpuinfo_cache big_l1i = { 0 }; 864 struct cpuinfo_cache big_l1d = { 0 }; 865 struct cpuinfo_cache big_l2 = { 0 }; 866 struct cpuinfo_cache big_l3 = { 0 }; 867 cpuinfo_arm_decode_cache( 868 cpuinfo_uarch_mongoose_m2, 4, UINT32_C(0x534F0010), 869 &chipset, 0, 8, 870 &big_l1i, &big_l1d, &big_l2, &big_l3); 871 872 struct cpuinfo_cache little_l1i = { 0 }; 873 struct cpuinfo_cache little_l1d = { 0 }; 874 struct cpuinfo_cache little_l2 = { 0 }; 875 struct cpuinfo_cache little_l3 = { 0 }; 876 cpuinfo_arm_decode_cache( 877 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 878 &chipset, 1, 8, 879 &little_l1i, &little_l1d, &little_l2, &little_l3); 880 881 EXPECT_EQ(64 * 1024, big_l1i.size); 882 EXPECT_EQ(32 * 1024, big_l1d.size); 883 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 884 EXPECT_EQ(0, big_l3.size); 885 886 EXPECT_EQ(32 * 1024, little_l1i.size); 887 EXPECT_EQ(32 * 1024, little_l1d.size); 888 EXPECT_EQ(256 * 1024, little_l2.size); 889 EXPECT_EQ(0, little_l3.size); 890 } 891 892 TEST(SAMSUNG, exynos_9810) { 893 const struct cpuinfo_arm_chipset chipset = { 894 .vendor = cpuinfo_arm_chipset_vendor_samsung, 895 .series = cpuinfo_arm_chipset_series_samsung_exynos, 896 .model = 9810, 897 }; 898 899 struct cpuinfo_cache big_l1i = { 0 }; 900 struct cpuinfo_cache big_l1d = { 0 }; 901 struct cpuinfo_cache big_l2 = { 0 }; 902 struct cpuinfo_cache big_l3 = { 0 }; 903 cpuinfo_arm_decode_cache( 904 cpuinfo_uarch_meerkat_m3, 4, UINT32_C(0x531F0020), 905 &chipset, 0, 8, 906 &big_l1i, &big_l1d, &big_l2, &big_l3); 907 908 struct cpuinfo_cache little_l1i = { 0 }; 909 struct cpuinfo_cache little_l1d = { 0 }; 910 struct cpuinfo_cache little_l2 = { 0 }; 911 struct cpuinfo_cache little_l3 = { 0 }; 912 cpuinfo_arm_decode_cache( 913 cpuinfo_uarch_cortex_a55, 4, UINT32_C(0x410FD051), 914 &chipset, 1, 8, 915 &little_l1i, &little_l1d, &little_l2, &little_l3); 916 917 EXPECT_EQ(64 * 1024, big_l1i.size); 918 EXPECT_EQ(64 * 1024, big_l1d.size); 919 EXPECT_EQ(512 * 1024, big_l2.size); 920 EXPECT_EQ(4 * 1024 * 1024, big_l3.size); 921 922 EXPECT_EQ(32 * 1024, little_l1i.size); 923 EXPECT_EQ(32 * 1024, little_l1d.size); 924 EXPECT_EQ(512 * 1024, little_l2.size); 925 EXPECT_EQ(0, little_l3.size); 926 } 927 928 TEST(MEDIATEK, mediatek_mt8173) { 929 const struct cpuinfo_arm_chipset chipset = { 930 .vendor = cpuinfo_arm_chipset_vendor_mediatek, 931 .series = cpuinfo_arm_chipset_series_mediatek_mt, 932 .model = 8173, 933 }; 934 935 struct cpuinfo_cache big_l1i = { 0 }; 936 struct cpuinfo_cache big_l1d = { 0 }; 937 struct cpuinfo_cache big_l2 = { 0 }; 938 struct cpuinfo_cache big_l3 = { 0 }; 939 cpuinfo_arm_decode_cache( 940 cpuinfo_uarch_cortex_a72, 2, UINT32_C(0x410FD080), 941 &chipset, 0, 4, 942 &big_l1i, &big_l1d, &big_l2, &big_l3); 943 944 struct cpuinfo_cache little_l1i = { 0 }; 945 struct cpuinfo_cache little_l1d = { 0 }; 946 struct cpuinfo_cache little_l2 = { 0 }; 947 struct cpuinfo_cache little_l3 = { 0 }; 948 cpuinfo_arm_decode_cache( 949 cpuinfo_uarch_cortex_a53, 2, UINT32_C(0x410FD032), 950 &chipset, 1, 4, 951 &little_l1i, &little_l1d, &little_l2, &little_l3); 952 953 EXPECT_EQ(48 * 1024, big_l1i.size); 954 EXPECT_EQ(32 * 1024, big_l1d.size); 955 EXPECT_EQ(1024 * 1024, big_l2.size); 956 EXPECT_EQ(0, big_l3.size); 957 958 EXPECT_EQ(32 * 1024, little_l1i.size); 959 EXPECT_EQ(32 * 1024, little_l1d.size); 960 EXPECT_EQ(512 * 1024, little_l2.size); 961 EXPECT_EQ(0, little_l3.size); 962 } 963 964 TEST(MEDIATEK, mediatek_mt8173c) { 965 const struct cpuinfo_arm_chipset chipset = { 966 .vendor = cpuinfo_arm_chipset_vendor_mediatek, 967 .series = cpuinfo_arm_chipset_series_mediatek_mt, 968 .model = 8173, 969 .suffix = { 970 [0] = 'C', 971 }, 972 }; 973 974 struct cpuinfo_cache big_l1i = { 0 }; 975 struct cpuinfo_cache big_l1d = { 0 }; 976 struct cpuinfo_cache big_l2 = { 0 }; 977 struct cpuinfo_cache big_l3 = { 0 }; 978 cpuinfo_arm_decode_cache( 979 cpuinfo_uarch_cortex_a72, 2, UINT32_C(0x410FD080), 980 &chipset, 0, 4, 981 &big_l1i, &big_l1d, &big_l2, &big_l3); 982 983 struct cpuinfo_cache little_l1i = { 0 }; 984 struct cpuinfo_cache little_l1d = { 0 }; 985 struct cpuinfo_cache little_l2 = { 0 }; 986 struct cpuinfo_cache little_l3 = { 0 }; 987 cpuinfo_arm_decode_cache( 988 cpuinfo_uarch_cortex_a53, 2, UINT32_C(0x410FD032), 989 &chipset, 1, 4, 990 &little_l1i, &little_l1d, &little_l2, &little_l3); 991 992 EXPECT_EQ(48 * 1024, big_l1i.size); 993 EXPECT_EQ(32 * 1024, big_l1d.size); 994 EXPECT_EQ(1024 * 1024, big_l2.size); 995 EXPECT_EQ(0, big_l3.size); 996 997 EXPECT_EQ(32 * 1024, little_l1i.size); 998 EXPECT_EQ(32 * 1024, little_l1d.size); 999 EXPECT_EQ(512 * 1024, little_l2.size); 1000 EXPECT_EQ(0, little_l3.size); 1001 } 1002 1003 TEST(HISILICON, kirin_650) { 1004 const struct cpuinfo_arm_chipset chipset = { 1005 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1006 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1007 .model = 650, 1008 }; 1009 1010 struct cpuinfo_cache big_l1i = { 0 }; 1011 struct cpuinfo_cache big_l1d = { 0 }; 1012 struct cpuinfo_cache big_l2 = { 0 }; 1013 struct cpuinfo_cache big_l3 = { 0 }; 1014 cpuinfo_arm_decode_cache( 1015 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 1016 &chipset, 0, 8, 1017 &big_l1i, &big_l1d, &big_l2, &big_l3); 1018 1019 struct cpuinfo_cache little_l1i = { 0 }; 1020 struct cpuinfo_cache little_l1d = { 0 }; 1021 struct cpuinfo_cache little_l2 = { 0 }; 1022 struct cpuinfo_cache little_l3 = { 0 }; 1023 cpuinfo_arm_decode_cache( 1024 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 1025 &chipset, 1, 8, 1026 &little_l1i, &little_l1d, &little_l2, &little_l3); 1027 1028 EXPECT_EQ(32 * 1024, big_l1i.size); 1029 EXPECT_EQ(32 * 1024, big_l1d.size); 1030 EXPECT_EQ(512 * 1024, big_l2.size); 1031 EXPECT_EQ(0, big_l3.size); 1032 1033 EXPECT_EQ(32 * 1024, little_l1i.size); 1034 EXPECT_EQ(32 * 1024, little_l1d.size); 1035 EXPECT_EQ(512 * 1024, little_l2.size); 1036 EXPECT_EQ(0, little_l3.size); 1037 } 1038 1039 TEST(HISILICON, kirin_659) { 1040 const struct cpuinfo_arm_chipset chipset = { 1041 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1042 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1043 .model = 659, 1044 }; 1045 1046 struct cpuinfo_cache big_l1i = { 0 }; 1047 struct cpuinfo_cache big_l1d = { 0 }; 1048 struct cpuinfo_cache big_l2 = { 0 }; 1049 struct cpuinfo_cache big_l3 = { 0 }; 1050 cpuinfo_arm_decode_cache( 1051 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 1052 &chipset, 0, 8, 1053 &big_l1i, &big_l1d, &big_l2, &big_l3); 1054 1055 struct cpuinfo_cache little_l1i = { 0 }; 1056 struct cpuinfo_cache little_l1d = { 0 }; 1057 struct cpuinfo_cache little_l2 = { 0 }; 1058 struct cpuinfo_cache little_l3 = { 0 }; 1059 cpuinfo_arm_decode_cache( 1060 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 1061 &chipset, 1, 8, 1062 &little_l1i, &little_l1d, &little_l2, &little_l3); 1063 1064 EXPECT_EQ(32 * 1024, big_l1i.size); 1065 EXPECT_EQ(32 * 1024, big_l1d.size); 1066 EXPECT_EQ(512 * 1024, big_l2.size); 1067 EXPECT_EQ(0, big_l3.size); 1068 1069 EXPECT_EQ(32 * 1024, little_l1i.size); 1070 EXPECT_EQ(32 * 1024, little_l1d.size); 1071 EXPECT_EQ(512 * 1024, little_l2.size); 1072 EXPECT_EQ(0, little_l3.size); 1073 } 1074 1075 #if CPUINFO_ARCH_ARM 1076 TEST(HISILICON, kirin_920) { 1077 const struct cpuinfo_arm_chipset chipset = { 1078 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1079 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1080 .model = 920, 1081 }; 1082 1083 struct cpuinfo_cache big_l1i = { 0 }; 1084 struct cpuinfo_cache big_l1d = { 0 }; 1085 struct cpuinfo_cache big_l2 = { 0 }; 1086 struct cpuinfo_cache big_l3 = { 0 }; 1087 cpuinfo_arm_decode_cache( 1088 cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), 1089 &chipset, 0, 8, 1090 &big_l1i, &big_l1d, &big_l2, &big_l3); 1091 1092 struct cpuinfo_cache little_l1i = { 0 }; 1093 struct cpuinfo_cache little_l1d = { 0 }; 1094 struct cpuinfo_cache little_l2 = { 0 }; 1095 struct cpuinfo_cache little_l3 = { 0 }; 1096 cpuinfo_arm_decode_cache( 1097 cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), 1098 &chipset, 1, 8, 1099 &little_l1i, &little_l1d, &little_l2, &little_l3); 1100 1101 EXPECT_EQ(32 * 1024, big_l1i.size); 1102 EXPECT_EQ(32 * 1024, big_l1d.size); 1103 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 1104 EXPECT_EQ(0, big_l3.size); 1105 1106 EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ 1107 EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ 1108 EXPECT_EQ(512 * 1024, little_l2.size); 1109 EXPECT_EQ(0, little_l3.size); 1110 } 1111 1112 TEST(HISILICON, kirin_925) { 1113 const struct cpuinfo_arm_chipset chipset = { 1114 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1115 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1116 .model = 925, 1117 }; 1118 1119 struct cpuinfo_cache big_l1i = { 0 }; 1120 struct cpuinfo_cache big_l1d = { 0 }; 1121 struct cpuinfo_cache big_l2 = { 0 }; 1122 struct cpuinfo_cache big_l3 = { 0 }; 1123 cpuinfo_arm_decode_cache( 1124 cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), 1125 &chipset, 0, 8, 1126 &big_l1i, &big_l1d, &big_l2, &big_l3); 1127 1128 struct cpuinfo_cache little_l1i = { 0 }; 1129 struct cpuinfo_cache little_l1d = { 0 }; 1130 struct cpuinfo_cache little_l2 = { 0 }; 1131 struct cpuinfo_cache little_l3 = { 0 }; 1132 cpuinfo_arm_decode_cache( 1133 cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), 1134 &chipset, 1, 8, 1135 &little_l1i, &little_l1d, &little_l2, &little_l3); 1136 1137 EXPECT_EQ(32 * 1024, big_l1i.size); 1138 EXPECT_EQ(32 * 1024, big_l1d.size); 1139 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 1140 EXPECT_EQ(0, big_l3.size); 1141 1142 EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ 1143 EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ 1144 EXPECT_EQ(512 * 1024, little_l2.size); 1145 EXPECT_EQ(0, little_l3.size); 1146 } 1147 1148 TEST(HISILICON, kirin_928) { 1149 const struct cpuinfo_arm_chipset chipset = { 1150 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1151 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1152 .model = 928, 1153 }; 1154 1155 struct cpuinfo_cache big_l1i = { 0 }; 1156 struct cpuinfo_cache big_l1d = { 0 }; 1157 struct cpuinfo_cache big_l2 = { 0 }; 1158 struct cpuinfo_cache big_l3 = { 0 }; 1159 cpuinfo_arm_decode_cache( 1160 cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), 1161 &chipset, 0, 8, 1162 &big_l1i, &big_l1d, &big_l2, &big_l3); 1163 1164 struct cpuinfo_cache little_l1i = { 0 }; 1165 struct cpuinfo_cache little_l1d = { 0 }; 1166 struct cpuinfo_cache little_l2 = { 0 }; 1167 struct cpuinfo_cache little_l3 = { 0 }; 1168 cpuinfo_arm_decode_cache( 1169 cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), 1170 &chipset, 1, 8, 1171 &little_l1i, &little_l1d, &little_l2, &little_l3); 1172 1173 EXPECT_EQ(32 * 1024, big_l1i.size); 1174 EXPECT_EQ(32 * 1024, big_l1d.size); 1175 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 1176 EXPECT_EQ(0, big_l3.size); 1177 1178 EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ 1179 EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ 1180 EXPECT_EQ(512 * 1024, little_l2.size); 1181 EXPECT_EQ(0, little_l3.size); 1182 } 1183 #endif /* CPUINFO_ARCH_ARM */ 1184 1185 TEST(HISILICON, kirin_950) { 1186 const struct cpuinfo_arm_chipset chipset = { 1187 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1188 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1189 .model = 950, 1190 }; 1191 1192 struct cpuinfo_cache big_l1i = { 0 }; 1193 struct cpuinfo_cache big_l1d = { 0 }; 1194 struct cpuinfo_cache big_l2 = { 0 }; 1195 struct cpuinfo_cache big_l3 = { 0 }; 1196 cpuinfo_arm_decode_cache( 1197 cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD080), 1198 &chipset, 0, 8, 1199 &big_l1i, &big_l1d, &big_l2, &big_l3); 1200 1201 struct cpuinfo_cache little_l1i = { 0 }; 1202 struct cpuinfo_cache little_l1d = { 0 }; 1203 struct cpuinfo_cache little_l2 = { 0 }; 1204 struct cpuinfo_cache little_l3 = { 0 }; 1205 cpuinfo_arm_decode_cache( 1206 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 1207 &chipset, 1, 8, 1208 &little_l1i, &little_l1d, &little_l2, &little_l3); 1209 1210 EXPECT_EQ(48 * 1024, big_l1i.size); 1211 EXPECT_EQ(32 * 1024, big_l1d.size); 1212 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 1213 EXPECT_EQ(0, big_l3.size); 1214 1215 EXPECT_EQ(32 * 1024, little_l1i.size); 1216 EXPECT_EQ(32 * 1024, little_l1d.size); 1217 EXPECT_EQ(512 * 1024, little_l2.size); 1218 EXPECT_EQ(0, little_l3.size); 1219 } 1220 1221 TEST(HISILICON, kirin_955) { 1222 const struct cpuinfo_arm_chipset chipset = { 1223 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1224 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1225 .model = 955, 1226 }; 1227 1228 struct cpuinfo_cache big_l1i = { 0 }; 1229 struct cpuinfo_cache big_l1d = { 0 }; 1230 struct cpuinfo_cache big_l2 = { 0 }; 1231 struct cpuinfo_cache big_l3 = { 0 }; 1232 cpuinfo_arm_decode_cache( 1233 cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD080), 1234 &chipset, 0, 8, 1235 &big_l1i, &big_l1d, &big_l2, &big_l3); 1236 1237 struct cpuinfo_cache little_l1i = { 0 }; 1238 struct cpuinfo_cache little_l1d = { 0 }; 1239 struct cpuinfo_cache little_l2 = { 0 }; 1240 struct cpuinfo_cache little_l3 = { 0 }; 1241 cpuinfo_arm_decode_cache( 1242 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 1243 &chipset, 1, 8, 1244 &little_l1i, &little_l1d, &little_l2, &little_l3); 1245 1246 EXPECT_EQ(48 * 1024, big_l1i.size); 1247 EXPECT_EQ(32 * 1024, big_l1d.size); 1248 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 1249 EXPECT_EQ(0, big_l3.size); 1250 1251 EXPECT_EQ(32 * 1024, little_l1i.size); 1252 EXPECT_EQ(32 * 1024, little_l1d.size); 1253 EXPECT_EQ(512 * 1024, little_l2.size); 1254 EXPECT_EQ(0, little_l3.size); 1255 } 1256 1257 TEST(HISILICON, kirin_960) { 1258 const struct cpuinfo_arm_chipset chipset = { 1259 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1260 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1261 .model = 960, 1262 }; 1263 1264 struct cpuinfo_cache big_l1i = { 0 }; 1265 struct cpuinfo_cache big_l1d = { 0 }; 1266 struct cpuinfo_cache big_l2 = { 0 }; 1267 struct cpuinfo_cache big_l3 = { 0 }; 1268 cpuinfo_arm_decode_cache( 1269 cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x410FD091), 1270 &chipset, 0, 8, 1271 &big_l1i, &big_l1d, &big_l2, &big_l3); 1272 1273 struct cpuinfo_cache little_l1i = { 0 }; 1274 struct cpuinfo_cache little_l1d = { 0 }; 1275 struct cpuinfo_cache little_l2 = { 0 }; 1276 struct cpuinfo_cache little_l3 = { 0 }; 1277 cpuinfo_arm_decode_cache( 1278 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 1279 &chipset, 1, 8, 1280 &little_l1i, &little_l1d, &little_l2, &little_l3); 1281 1282 EXPECT_EQ(64 * 1024, big_l1i.size); 1283 EXPECT_EQ(64 * 1024, big_l1d.size); 1284 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 1285 EXPECT_EQ(0, big_l3.size); 1286 1287 EXPECT_EQ(32 * 1024, little_l1i.size); 1288 EXPECT_EQ(32 * 1024, little_l1d.size); 1289 EXPECT_EQ(512 * 1024, little_l2.size); 1290 EXPECT_EQ(0, little_l3.size); 1291 } 1292 1293 TEST(HISILICON, kirin_970) { 1294 const struct cpuinfo_arm_chipset chipset = { 1295 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1296 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1297 .model = 970, 1298 }; 1299 1300 struct cpuinfo_cache big_l1i = { 0 }; 1301 struct cpuinfo_cache big_l1d = { 0 }; 1302 struct cpuinfo_cache big_l2 = { 0 }; 1303 struct cpuinfo_cache big_l3 = { 0 }; 1304 cpuinfo_arm_decode_cache( 1305 cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x410FD092), 1306 &chipset, 0, 8, 1307 &big_l1i, &big_l1d, &big_l2, &big_l3); 1308 1309 struct cpuinfo_cache little_l1i = { 0 }; 1310 struct cpuinfo_cache little_l1d = { 0 }; 1311 struct cpuinfo_cache little_l2 = { 0 }; 1312 struct cpuinfo_cache little_l3 = { 0 }; 1313 cpuinfo_arm_decode_cache( 1314 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), 1315 &chipset, 1, 8, 1316 &little_l1i, &little_l1d, &little_l2, &little_l3); 1317 1318 EXPECT_EQ(64 * 1024, big_l1i.size); 1319 EXPECT_EQ(64 * 1024, big_l1d.size); 1320 EXPECT_EQ(2 * 1024 * 1024, big_l2.size); 1321 EXPECT_EQ(0, big_l3.size); 1322 1323 EXPECT_EQ(32 * 1024, little_l1i.size); 1324 EXPECT_EQ(32 * 1024, little_l1d.size); 1325 EXPECT_EQ(1024 * 1024, little_l2.size); 1326 EXPECT_EQ(0, little_l3.size); 1327 } 1328 1329 TEST(HISILICON, kirin_980) { 1330 const struct cpuinfo_arm_chipset chipset = { 1331 .vendor = cpuinfo_arm_chipset_vendor_hisilicon, 1332 .series = cpuinfo_arm_chipset_series_hisilicon_kirin, 1333 .model = 980, 1334 }; 1335 1336 struct cpuinfo_cache big_l1i = { 0 }; 1337 struct cpuinfo_cache big_l1d = { 0 }; 1338 struct cpuinfo_cache big_l2 = { 0 }; 1339 struct cpuinfo_cache big_l3 = { 0 }; 1340 cpuinfo_arm_decode_cache( 1341 cpuinfo_uarch_cortex_a76, 2, UINT32_C(0x481FD400), 1342 &chipset, 0, 2, 1343 &big_l1i, &big_l1d, &big_l2, &big_l3); 1344 1345 struct cpuinfo_cache middle_l1i = { 0 }; 1346 struct cpuinfo_cache middle_l1d = { 0 }; 1347 struct cpuinfo_cache middle_l2 = { 0 }; 1348 struct cpuinfo_cache middle_l3 = { 0 }; 1349 cpuinfo_arm_decode_cache( 1350 cpuinfo_uarch_cortex_a76, 2, UINT32_C(0x481FD400), 1351 &chipset, 1, 2, 1352 &middle_l1i, &middle_l1d, &middle_l2, &middle_l3); 1353 1354 struct cpuinfo_cache little_l1i = { 0 }; 1355 struct cpuinfo_cache little_l1d = { 0 }; 1356 struct cpuinfo_cache little_l2 = { 0 }; 1357 struct cpuinfo_cache little_l3 = { 0 }; 1358 cpuinfo_arm_decode_cache( 1359 cpuinfo_uarch_cortex_a55, 4, UINT32_C(0x411FD050), 1360 &chipset, 2, 4, 1361 &little_l1i, &little_l1d, &little_l2, &little_l3); 1362 1363 EXPECT_EQ(64 * 1024, big_l1i.size); 1364 EXPECT_EQ(64 * 1024, big_l1d.size); 1365 EXPECT_EQ(512 * 1024, big_l2.size); 1366 EXPECT_EQ(4 * 1024 * 1024, big_l3.size); 1367 1368 EXPECT_EQ(64 * 1024, middle_l1i.size); 1369 EXPECT_EQ(64 * 1024, middle_l1d.size); 1370 EXPECT_EQ(512 * 1024, middle_l2.size); 1371 EXPECT_EQ(4 * 1024 * 1024, middle_l3.size); 1372 1373 EXPECT_EQ(32 * 1024, little_l1i.size); 1374 EXPECT_EQ(32 * 1024, little_l1d.size); 1375 EXPECT_EQ(128 * 1024, little_l2.size); 1376 EXPECT_EQ(4 * 1024 * 1024, little_l3.size); 1377 } 1378 1379 #if CPUINFO_ARCH_ARM 1380 TEST(NVIDIA, tegra_ap20h) { 1381 const struct cpuinfo_arm_chipset chipset = { 1382 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1383 .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, 1384 .model = 20, 1385 .suffix = { 1386 [0] = 'H', 1387 }, 1388 }; 1389 1390 struct cpuinfo_cache l1i = { 0 }; 1391 struct cpuinfo_cache l1d = { 0 }; 1392 struct cpuinfo_cache l2 = { 0 }; 1393 struct cpuinfo_cache l3 = { 0 }; 1394 cpuinfo_arm_decode_cache( 1395 cpuinfo_uarch_cortex_a9, 2, UINT32_C(0x411FC090), 1396 &chipset, 0, 7, 1397 &l1i, &l1d, &l2, &l3); 1398 1399 EXPECT_EQ(32 * 1024, l1i.size); 1400 EXPECT_EQ(32 * 1024, l1d.size); 1401 EXPECT_EQ(1024 * 1024, l2.size); 1402 EXPECT_EQ(0, l3.size); 1403 } 1404 1405 TEST(NVIDIA, tegra_t20) { 1406 const struct cpuinfo_arm_chipset chipset = { 1407 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1408 .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, 1409 .model = 20, 1410 }; 1411 1412 struct cpuinfo_cache l1i = { 0 }; 1413 struct cpuinfo_cache l1d = { 0 }; 1414 struct cpuinfo_cache l2 = { 0 }; 1415 struct cpuinfo_cache l3 = { 0 }; 1416 cpuinfo_arm_decode_cache( 1417 cpuinfo_uarch_cortex_a9, 2, UINT32_C(0x411FC090), 1418 &chipset, 0, 7, 1419 &l1i, &l1d, &l2, &l3); 1420 1421 EXPECT_EQ(32 * 1024, l1i.size); 1422 EXPECT_EQ(32 * 1024, l1d.size); 1423 EXPECT_EQ(1024 * 1024, l2.size); 1424 EXPECT_EQ(0, l3.size); 1425 } 1426 1427 TEST(NVIDIA, tegra_t30l) { 1428 const struct cpuinfo_arm_chipset chipset = { 1429 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1430 .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, 1431 .model = 30, 1432 .suffix = { 1433 [0] = 'L', 1434 }, 1435 }; 1436 1437 struct cpuinfo_cache l1i = { 0 }; 1438 struct cpuinfo_cache l1d = { 0 }; 1439 struct cpuinfo_cache l2 = { 0 }; 1440 struct cpuinfo_cache l3 = { 0 }; 1441 cpuinfo_arm_decode_cache( 1442 cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), 1443 &chipset, 0, 7, 1444 &l1i, &l1d, &l2, &l3); 1445 1446 EXPECT_EQ(32 * 1024, l1i.size); 1447 EXPECT_EQ(32 * 1024, l1d.size); 1448 EXPECT_EQ(1024 * 1024, l2.size); 1449 EXPECT_EQ(0, l3.size); 1450 } 1451 1452 TEST(NVIDIA, tegra_t30) { 1453 const struct cpuinfo_arm_chipset chipset = { 1454 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1455 .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, 1456 .model = 30, 1457 }; 1458 1459 struct cpuinfo_cache l1i = { 0 }; 1460 struct cpuinfo_cache l1d = { 0 }; 1461 struct cpuinfo_cache l2 = { 0 }; 1462 struct cpuinfo_cache l3 = { 0 }; 1463 cpuinfo_arm_decode_cache( 1464 cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), 1465 &chipset, 0, 7, 1466 &l1i, &l1d, &l2, &l3); 1467 1468 EXPECT_EQ(32 * 1024, l1i.size); 1469 EXPECT_EQ(32 * 1024, l1d.size); 1470 EXPECT_EQ(1024 * 1024, l2.size); 1471 EXPECT_EQ(0, l3.size); 1472 } 1473 1474 TEST(NVIDIA, tegra_t33) { 1475 const struct cpuinfo_arm_chipset chipset = { 1476 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1477 .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, 1478 .model = 33, 1479 }; 1480 1481 struct cpuinfo_cache l1i = { 0 }; 1482 struct cpuinfo_cache l1d = { 0 }; 1483 struct cpuinfo_cache l2 = { 0 }; 1484 struct cpuinfo_cache l3 = { 0 }; 1485 cpuinfo_arm_decode_cache( 1486 cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), 1487 &chipset, 0, 7, 1488 &l1i, &l1d, &l2, &l3); 1489 1490 EXPECT_EQ(32 * 1024, l1i.size); 1491 EXPECT_EQ(32 * 1024, l1d.size); 1492 EXPECT_EQ(1024 * 1024, l2.size); 1493 EXPECT_EQ(0, l3.size); 1494 } 1495 1496 TEST(NVIDIA, tegra_ap33) { 1497 const struct cpuinfo_arm_chipset chipset = { 1498 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1499 .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, 1500 .model = 33, 1501 }; 1502 1503 struct cpuinfo_cache l1i = { 0 }; 1504 struct cpuinfo_cache l1d = { 0 }; 1505 struct cpuinfo_cache l2 = { 0 }; 1506 struct cpuinfo_cache l3 = { 0 }; 1507 cpuinfo_arm_decode_cache( 1508 cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), 1509 &chipset, 0, 7, 1510 &l1i, &l1d, &l2, &l3); 1511 1512 EXPECT_EQ(32 * 1024, l1i.size); 1513 EXPECT_EQ(32 * 1024, l1d.size); 1514 EXPECT_EQ(1024 * 1024, l2.size); 1515 EXPECT_EQ(0, l3.size); 1516 } 1517 1518 TEST(NVIDIA, tegra_t114) { 1519 const struct cpuinfo_arm_chipset chipset = { 1520 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1521 .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, 1522 .model = 114, 1523 }; 1524 1525 struct cpuinfo_cache l1i = { 0 }; 1526 struct cpuinfo_cache l1d = { 0 }; 1527 struct cpuinfo_cache l2 = { 0 }; 1528 struct cpuinfo_cache l3 = { 0 }; 1529 cpuinfo_arm_decode_cache( 1530 cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x412FC0F2), 1531 &chipset, 0, 7, 1532 &l1i, &l1d, &l2, &l3); 1533 1534 EXPECT_EQ(32 * 1024, l1i.size); 1535 EXPECT_EQ(32 * 1024, l1d.size); 1536 EXPECT_EQ(2 * 1024 * 1024, l2.size); 1537 EXPECT_EQ(0, l3.size); 1538 } 1539 1540 TEST(NVIDIA, tegra_sl460n) { 1541 const struct cpuinfo_arm_chipset chipset = { 1542 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1543 .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, 1544 .model = 460, 1545 .suffix = { 1546 [0] = 'N', 1547 }, 1548 }; 1549 1550 struct cpuinfo_cache l1i = { 0 }; 1551 struct cpuinfo_cache l1d = { 0 }; 1552 struct cpuinfo_cache l2 = { 0 }; 1553 struct cpuinfo_cache l3 = { 0 }; 1554 cpuinfo_arm_decode_cache( 1555 cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x414FC091), 1556 &chipset, 0, 7, 1557 &l1i, &l1d, &l2, &l3); 1558 1559 EXPECT_EQ(32 * 1024, l1i.size); 1560 EXPECT_EQ(32 * 1024, l1d.size); 1561 EXPECT_EQ(1 * 1024 * 1024, l2.size); 1562 EXPECT_EQ(0, l3.size); 1563 } 1564 1565 TEST(NVIDIA, tegra_t124) { 1566 const struct cpuinfo_arm_chipset chipset = { 1567 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1568 .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, 1569 .model = 124, 1570 }; 1571 1572 struct cpuinfo_cache l1i = { 0 }; 1573 struct cpuinfo_cache l1d = { 0 }; 1574 struct cpuinfo_cache l2 = { 0 }; 1575 struct cpuinfo_cache l3 = { 0 }; 1576 cpuinfo_arm_decode_cache( 1577 cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), 1578 &chipset, 0, 7, 1579 &l1i, &l1d, &l2, &l3); 1580 1581 EXPECT_EQ(32 * 1024, l1i.size); 1582 EXPECT_EQ(32 * 1024, l1d.size); 1583 EXPECT_EQ(2 * 1024 * 1024, l2.size); 1584 EXPECT_EQ(0, l3.size); 1585 } 1586 #endif /* CPUINFO_ARCH_ARM */ 1587 1588 TEST(NVIDIA, tegra_t132) { 1589 const struct cpuinfo_arm_chipset chipset = { 1590 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1591 .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, 1592 .model = 132, 1593 }; 1594 1595 struct cpuinfo_cache l1i = { 0 }; 1596 struct cpuinfo_cache l1d = { 0 }; 1597 struct cpuinfo_cache l2 = { 0 }; 1598 struct cpuinfo_cache l3 = { 0 }; 1599 cpuinfo_arm_decode_cache( 1600 cpuinfo_uarch_denver, 2, UINT32_C(0x4E0F0000), 1601 &chipset, 0, 8, 1602 &l1i, &l1d, &l2, &l3); 1603 1604 EXPECT_EQ(128 * 1024, l1i.size); 1605 EXPECT_EQ(64 * 1024, l1d.size); 1606 EXPECT_EQ(2 * 1024 * 1024, l2.size); 1607 EXPECT_EQ(0, l3.size); 1608 } 1609 1610 TEST(NVIDIA, tegra_t210) { 1611 const struct cpuinfo_arm_chipset chipset = { 1612 .vendor = cpuinfo_arm_chipset_vendor_nvidia, 1613 .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, 1614 .model = 210, 1615 }; 1616 1617 struct cpuinfo_cache l1i = { 0 }; 1618 struct cpuinfo_cache l1d = { 0 }; 1619 struct cpuinfo_cache l2 = { 0 }; 1620 struct cpuinfo_cache l3 = { 0 }; 1621 cpuinfo_arm_decode_cache( 1622 cpuinfo_uarch_cortex_a57, 4, UINT32_C(0x411FD071), 1623 &chipset, 0, 8, 1624 &l1i, &l1d, &l2, &l3); 1625 1626 EXPECT_EQ(48 * 1024, l1i.size); 1627 EXPECT_EQ(32 * 1024, l1d.size); 1628 EXPECT_EQ(2 * 1024 * 1024, l2.size); 1629 EXPECT_EQ(0, l3.size); 1630 } 1631 1632 TEST(ROCKCHIP, rk3368) { 1633 const struct cpuinfo_arm_chipset chipset = { 1634 .vendor = cpuinfo_arm_chipset_vendor_rockchip, 1635 .series = cpuinfo_arm_chipset_series_rockchip_rk, 1636 .model = 3368, 1637 }; 1638 1639 struct cpuinfo_cache big_l1i = { 0 }; 1640 struct cpuinfo_cache big_l1d = { 0 }; 1641 struct cpuinfo_cache big_l2 = { 0 }; 1642 struct cpuinfo_cache big_l3 = { 0 }; 1643 cpuinfo_arm_decode_cache( 1644 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), 1645 &chipset, 0, 8, 1646 &big_l1i, &big_l1d, &big_l2, &big_l3); 1647 1648 struct cpuinfo_cache little_l1i = { 0 }; 1649 struct cpuinfo_cache little_l1d = { 0 }; 1650 struct cpuinfo_cache little_l2 = { 0 }; 1651 struct cpuinfo_cache little_l3 = { 0 }; 1652 cpuinfo_arm_decode_cache( 1653 cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), 1654 &chipset, 1, 8, 1655 &little_l1i, &little_l1d, &little_l2, &little_l3); 1656 1657 EXPECT_EQ(32 * 1024, big_l1i.size); 1658 EXPECT_EQ(32 * 1024, big_l1d.size); 1659 EXPECT_EQ(512 * 1024, big_l2.size); 1660 EXPECT_EQ(0, big_l3.size); 1661 1662 EXPECT_EQ(32 * 1024, little_l1i.size); 1663 EXPECT_EQ(32 * 1024, little_l1d.size); 1664 EXPECT_EQ(256 * 1024, little_l2.size); 1665 EXPECT_EQ(0, little_l3.size); 1666 } 1667