1 #include <gtest/gtest.h> 2 3 #include <cpuinfo.h> 4 #include <cpuinfo-mock.h> 5 6 7 TEST(PROCESSORS, count) { 8 ASSERT_EQ(8, cpuinfo_get_processors_count()); 9 } 10 11 TEST(PROCESSORS, non_null) { 12 ASSERT_TRUE(cpuinfo_get_processors()); 13 } 14 15 TEST(PROCESSORS, smt_id) { 16 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id); 18 } 19 } 20 21 TEST(PROCESSORS, core) { 22 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core); 24 } 25 } 26 27 TEST(PROCESSORS, cluster) { 28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 29 switch (i) { 30 case 0: 31 case 1: 32 case 2: 33 case 3: 34 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster); 35 break; 36 case 4: 37 case 5: 38 case 6: 39 case 7: 40 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster); 41 break; 42 } 43 } 44 } 45 46 TEST(PROCESSORS, package) { 47 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 48 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package); 49 } 50 } 51 52 TEST(PROCESSORS, linux_id) { 53 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 54 switch (i) { 55 case 0: 56 case 1: 57 case 2: 58 case 3: 59 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id); 60 break; 61 case 4: 62 case 5: 63 case 6: 64 case 7: 65 ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id); 66 break; 67 } 68 } 69 } 70 71 TEST(PROCESSORS, l1i) { 72 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 73 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i); 74 } 75 } 76 77 TEST(PROCESSORS, l1d) { 78 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 79 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d); 80 } 81 } 82 83 TEST(PROCESSORS, l2) { 84 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 85 switch (i) { 86 case 0: 87 case 1: 88 case 2: 89 case 3: 90 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2); 91 break; 92 case 4: 93 case 5: 94 case 6: 95 case 7: 96 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2); 97 break; 98 } 99 } 100 } 101 102 TEST(PROCESSORS, l3) { 103 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 104 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3); 105 } 106 } 107 108 TEST(PROCESSORS, l4) { 109 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { 110 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4); 111 } 112 } 113 114 TEST(CORES, count) { 115 ASSERT_EQ(8, cpuinfo_get_cores_count()); 116 } 117 118 TEST(CORES, non_null) { 119 ASSERT_TRUE(cpuinfo_get_cores()); 120 } 121 122 TEST(CORES, processor_start) { 123 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 124 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start); 125 } 126 } 127 128 TEST(CORES, processor_count) { 129 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 130 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count); 131 } 132 } 133 134 TEST(CORES, core_id) { 135 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 136 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id); 137 } 138 } 139 140 TEST(CORES, cluster) { 141 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 142 switch (i) { 143 case 0: 144 case 1: 145 case 2: 146 case 3: 147 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster); 148 break; 149 case 4: 150 case 5: 151 case 6: 152 case 7: 153 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster); 154 break; 155 } 156 } 157 } 158 159 TEST(CORES, package) { 160 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 161 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package); 162 } 163 } 164 165 TEST(CORES, vendor) { 166 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 167 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor); 168 } 169 } 170 171 TEST(CORES, uarch) { 172 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 173 switch (i) { 174 case 0: 175 case 1: 176 case 2: 177 case 3: 178 ASSERT_EQ(cpuinfo_uarch_cortex_a15, cpuinfo_get_core(i)->uarch); 179 break; 180 case 4: 181 case 5: 182 case 6: 183 case 7: 184 ASSERT_EQ(cpuinfo_uarch_cortex_a7, cpuinfo_get_core(i)->uarch); 185 break; 186 } 187 } 188 } 189 190 TEST(CORES, midr) { 191 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 192 switch (i) { 193 case 0: 194 case 1: 195 case 2: 196 case 3: 197 ASSERT_EQ(UINT32_C(0x412FC0F3), cpuinfo_get_core(i)->midr); 198 break; 199 case 4: 200 case 5: 201 case 6: 202 case 7: 203 ASSERT_EQ(UINT32_C(0x410FC073), cpuinfo_get_core(i)->midr); 204 break; 205 } 206 } 207 } 208 209 TEST(CORES, DISABLED_frequency) { 210 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { 211 switch (i) { 212 case 0: 213 case 1: 214 case 2: 215 case 3: 216 ASSERT_EQ(UINT64_C(1900000000), cpuinfo_get_core(i)->frequency); 217 break; 218 case 4: 219 case 5: 220 case 6: 221 case 7: 222 ASSERT_EQ(UINT64_C(1300000000), cpuinfo_get_core(i)->frequency); 223 break; 224 } 225 } 226 } 227 228 TEST(CLUSTERS, count) { 229 ASSERT_EQ(2, cpuinfo_get_clusters_count()); 230 } 231 232 TEST(CLUSTERS, non_null) { 233 ASSERT_TRUE(cpuinfo_get_clusters()); 234 } 235 236 TEST(CLUSTERS, processor_start) { 237 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 238 switch (i) { 239 case 0: 240 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start); 241 break; 242 case 1: 243 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_start); 244 break; 245 } 246 } 247 } 248 249 TEST(CLUSTERS, processor_count) { 250 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 251 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count); 252 } 253 } 254 255 TEST(CLUSTERS, core_start) { 256 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 257 switch (i) { 258 case 0: 259 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start); 260 break; 261 case 1: 262 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_start); 263 break; 264 } 265 } 266 } 267 268 TEST(CLUSTERS, core_count) { 269 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 270 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count); 271 } 272 } 273 274 TEST(CLUSTERS, cluster_id) { 275 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 276 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id); 277 } 278 } 279 280 TEST(CLUSTERS, package) { 281 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 282 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package); 283 } 284 } 285 286 TEST(CLUSTERS, vendor) { 287 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 288 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor); 289 } 290 } 291 292 TEST(CLUSTERS, uarch) { 293 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 294 switch (i) { 295 case 0: 296 ASSERT_EQ(cpuinfo_uarch_cortex_a15, cpuinfo_get_cluster(i)->uarch); 297 break; 298 case 1: 299 ASSERT_EQ(cpuinfo_uarch_cortex_a7, cpuinfo_get_cluster(i)->uarch); 300 break; 301 } 302 } 303 } 304 305 TEST(CLUSTERS, midr) { 306 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 307 switch (i) { 308 case 0: 309 ASSERT_EQ(UINT32_C(0x412FC0F3), cpuinfo_get_cluster(i)->midr); 310 break; 311 case 1: 312 ASSERT_EQ(UINT32_C(0x410FC073), cpuinfo_get_cluster(i)->midr); 313 break; 314 } 315 } 316 } 317 318 TEST(CLUSTERS, DISABLED_frequency) { 319 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { 320 switch (i) { 321 case 0: 322 ASSERT_EQ(UINT64_C(1900000000), cpuinfo_get_cluster(i)->frequency); 323 break; 324 case 1: 325 ASSERT_EQ(UINT64_C(1300000000), cpuinfo_get_cluster(i)->frequency); 326 break; 327 } 328 } 329 } 330 331 TEST(PACKAGES, count) { 332 ASSERT_EQ(1, cpuinfo_get_packages_count()); 333 } 334 335 TEST(PACKAGES, name) { 336 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { 337 ASSERT_EQ("Samsung Exynos 5422", 338 std::string(cpuinfo_get_package(i)->name, 339 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); 340 } 341 } 342 343 TEST(PACKAGES, processor_start) { 344 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { 345 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start); 346 } 347 } 348 349 TEST(PACKAGES, processor_count) { 350 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { 351 ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count); 352 } 353 } 354 355 TEST(PACKAGES, core_start) { 356 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { 357 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start); 358 } 359 } 360 361 TEST(PACKAGES, core_count) { 362 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { 363 ASSERT_EQ(8, cpuinfo_get_package(i)->core_count); 364 } 365 } 366 367 TEST(PACKAGES, cluster_start) { 368 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { 369 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start); 370 } 371 } 372 373 TEST(PACKAGES, cluster_count) { 374 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { 375 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count); 376 } 377 } 378 379 TEST(ISA, thumb) { 380 ASSERT_TRUE(cpuinfo_has_arm_thumb()); 381 } 382 383 TEST(ISA, thumb2) { 384 ASSERT_TRUE(cpuinfo_has_arm_thumb2()); 385 } 386 387 TEST(ISA, armv5e) { 388 ASSERT_TRUE(cpuinfo_has_arm_v5e()); 389 } 390 391 TEST(ISA, armv6) { 392 ASSERT_TRUE(cpuinfo_has_arm_v6()); 393 } 394 395 TEST(ISA, armv6k) { 396 ASSERT_TRUE(cpuinfo_has_arm_v6k()); 397 } 398 399 TEST(ISA, armv7) { 400 ASSERT_TRUE(cpuinfo_has_arm_v7()); 401 } 402 403 TEST(ISA, armv7mp) { 404 ASSERT_TRUE(cpuinfo_has_arm_v7mp()); 405 } 406 407 TEST(ISA, idiv) { 408 ASSERT_TRUE(cpuinfo_has_arm_idiv()); 409 } 410 411 TEST(ISA, vfpv2) { 412 ASSERT_FALSE(cpuinfo_has_arm_vfpv2()); 413 } 414 415 TEST(ISA, vfpv3) { 416 ASSERT_TRUE(cpuinfo_has_arm_vfpv3()); 417 } 418 419 TEST(ISA, vfpv3_d32) { 420 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32()); 421 } 422 423 TEST(ISA, vfpv3_fp16) { 424 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16()); 425 } 426 427 TEST(ISA, vfpv3_fp16_d32) { 428 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32()); 429 } 430 431 TEST(ISA, vfpv4) { 432 ASSERT_TRUE(cpuinfo_has_arm_vfpv4()); 433 } 434 435 TEST(ISA, vfpv4_d32) { 436 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32()); 437 } 438 439 TEST(ISA, wmmx) { 440 ASSERT_FALSE(cpuinfo_has_arm_wmmx()); 441 } 442 443 TEST(ISA, wmmx2) { 444 ASSERT_FALSE(cpuinfo_has_arm_wmmx2()); 445 } 446 447 TEST(ISA, neon) { 448 ASSERT_TRUE(cpuinfo_has_arm_neon()); 449 } 450 451 TEST(ISA, neon_fp16) { 452 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16()); 453 } 454 455 TEST(ISA, neon_fma) { 456 ASSERT_TRUE(cpuinfo_has_arm_neon_fma()); 457 } 458 459 TEST(ISA, atomics) { 460 ASSERT_FALSE(cpuinfo_has_arm_atomics()); 461 } 462 463 TEST(ISA, neon_rdm) { 464 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm()); 465 } 466 467 TEST(ISA, fp16_arith) { 468 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith()); 469 } 470 471 TEST(ISA, neon_fp16_arith) { 472 ASSERT_FALSE(cpuinfo_has_arm_neon_fp16_arith()); 473 } 474 475 TEST(ISA, neon_dot) { 476 ASSERT_FALSE(cpuinfo_has_arm_neon_dot()); 477 } 478 479 TEST(ISA, jscvt) { 480 ASSERT_FALSE(cpuinfo_has_arm_jscvt()); 481 } 482 483 TEST(ISA, fcma) { 484 ASSERT_FALSE(cpuinfo_has_arm_fcma()); 485 } 486 487 TEST(ISA, aes) { 488 ASSERT_FALSE(cpuinfo_has_arm_aes()); 489 } 490 491 TEST(ISA, sha1) { 492 ASSERT_FALSE(cpuinfo_has_arm_sha1()); 493 } 494 495 TEST(ISA, sha2) { 496 ASSERT_FALSE(cpuinfo_has_arm_sha2()); 497 } 498 499 TEST(ISA, pmull) { 500 ASSERT_FALSE(cpuinfo_has_arm_pmull()); 501 } 502 503 TEST(ISA, crc32) { 504 ASSERT_FALSE(cpuinfo_has_arm_crc32()); 505 } 506 507 TEST(L1I, count) { 508 ASSERT_EQ(8, cpuinfo_get_l1i_caches_count()); 509 } 510 511 TEST(L1I, non_null) { 512 ASSERT_TRUE(cpuinfo_get_l1i_caches()); 513 } 514 515 TEST(L1I, size) { 516 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { 517 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size); 518 } 519 } 520 521 TEST(L1I, associativity) { 522 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { 523 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity); 524 } 525 } 526 527 TEST(L1I, sets) { 528 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { 529 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, 530 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); 531 } 532 } 533 534 TEST(L1I, partitions) { 535 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { 536 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions); 537 } 538 } 539 540 TEST(L1I, line_size) { 541 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { 542 switch (i) { 543 case 0: 544 case 1: 545 case 2: 546 case 3: 547 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size); 548 break; 549 case 4: 550 case 5: 551 case 6: 552 case 7: 553 ASSERT_EQ(32, cpuinfo_get_l1i_cache(i)->line_size); 554 break; 555 } 556 } 557 } 558 559 TEST(L1I, flags) { 560 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { 561 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags); 562 } 563 } 564 565 TEST(L1I, processors) { 566 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { 567 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start); 568 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count); 569 } 570 } 571 572 TEST(L1D, count) { 573 ASSERT_EQ(8, cpuinfo_get_l1d_caches_count()); 574 } 575 576 TEST(L1D, non_null) { 577 ASSERT_TRUE(cpuinfo_get_l1d_caches()); 578 } 579 580 TEST(L1D, size) { 581 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { 582 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size); 583 } 584 } 585 586 TEST(L1D, associativity) { 587 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { 588 switch (i) { 589 case 0: 590 case 1: 591 case 2: 592 case 3: 593 ASSERT_EQ(2, cpuinfo_get_l1d_cache(i)->associativity); 594 break; 595 case 4: 596 case 5: 597 case 6: 598 case 7: 599 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity); 600 break; 601 } 602 } 603 } 604 605 TEST(L1D, sets) { 606 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { 607 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, 608 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); 609 } 610 } 611 612 TEST(L1D, partitions) { 613 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { 614 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions); 615 } 616 } 617 618 TEST(L1D, line_size) { 619 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { 620 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size); 621 } 622 } 623 624 TEST(L1D, flags) { 625 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { 626 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags); 627 } 628 } 629 630 TEST(L1D, processors) { 631 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { 632 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start); 633 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count); 634 } 635 } 636 637 TEST(L2, count) { 638 ASSERT_EQ(2, cpuinfo_get_l2_caches_count()); 639 } 640 641 TEST(L2, non_null) { 642 ASSERT_TRUE(cpuinfo_get_l2_caches()); 643 } 644 645 TEST(L2, size) { 646 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { 647 switch (i) { 648 case 0: 649 ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); 650 break; 651 case 1: 652 ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size); 653 break; 654 } 655 } 656 } 657 658 TEST(L2, associativity) { 659 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { 660 switch (i) { 661 case 0: 662 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity); 663 break; 664 case 1: 665 ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity); 666 break; 667 } 668 } 669 } 670 671 TEST(L2, sets) { 672 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { 673 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, 674 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); 675 } 676 } 677 678 TEST(L2, partitions) { 679 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { 680 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions); 681 } 682 } 683 684 TEST(L2, line_size) { 685 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { 686 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size); 687 } 688 } 689 690 TEST(L2, flags) { 691 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { 692 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags); 693 } 694 } 695 696 TEST(L2, processors) { 697 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { 698 switch (i) { 699 case 0: 700 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start); 701 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count); 702 break; 703 case 1: 704 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_start); 705 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count); 706 break; 707 } 708 } 709 } 710 711 TEST(L3, none) { 712 ASSERT_EQ(0, cpuinfo_get_l3_caches_count()); 713 ASSERT_FALSE(cpuinfo_get_l3_caches()); 714 } 715 716 TEST(L4, none) { 717 ASSERT_EQ(0, cpuinfo_get_l4_caches_count()); 718 ASSERT_FALSE(cpuinfo_get_l4_caches()); 719 } 720 721 #include <galaxy-s5-global.h> 722 723 int main(int argc, char* argv[]) { 724 #if CPUINFO_ARCH_ARM 725 cpuinfo_set_hwcap(UINT32_C(0x0007B0D7)); 726 #endif 727 cpuinfo_mock_filesystem(filesystem); 728 #ifdef __ANDROID__ 729 cpuinfo_mock_android_properties(properties); 730 #endif 731 cpuinfo_initialize(); 732 ::testing::InitGoogleTest(&argc, argv); 733 return RUN_ALL_TESTS(); 734 }