Lines Matching refs:pwr_domain
174 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; in imx_gpc_pm_domain_enable() local
186 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
199 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
202 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
205 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()
228 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
230 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
233 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
244 if (pwr_domain->always_on) { in imx_gpc_pm_domain_enable()
248 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
253 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
255 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
258 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
263 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
283 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
286 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()