1 /*
2 * Copyright 2019-2020 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdbool.h>
8 #include <stdint.h>
9 #include <stdlib.h>
10
11 #include <common/debug.h>
12 #include <drivers/delay_timer.h>
13 #include <lib/mmio.h>
14 #include <lib/psci/psci.h>
15 #include <lib/smccc.h>
16 #include <services/std_svc.h>
17
18 #include <gpc.h>
19 #include <imx_aipstz.h>
20 #include <imx_sip_svc.h>
21 #include <platform_def.h>
22
23 #define CCGR(x) (0x4000 + (x) * 0x10)
24 #define IMR_NUM U(5)
25
26 struct imx_noc_setting {
27 uint32_t domain_id;
28 uint32_t start;
29 uint32_t end;
30 uint32_t prioriy;
31 uint32_t mode;
32 uint32_t socket_qos_en;
33 };
34
35 enum clk_type {
36 CCM_ROOT_SLICE,
37 CCM_CCGR,
38 };
39
40 struct clk_setting {
41 uint32_t offset;
42 uint32_t val;
43 enum clk_type type;
44 };
45
46 enum pu_domain_id {
47 /* hsio ss */
48 HSIOMIX,
49 PCIE_PHY,
50 USB1_PHY,
51 USB2_PHY,
52 MLMIX,
53 AUDIOMIX,
54 /* gpu ss */
55 GPUMIX,
56 GPU2D,
57 GPU3D,
58 /* vpu ss */
59 VPUMIX,
60 VPU_G1,
61 VPU_G2,
62 VPU_H1,
63 /* media ss */
64 MEDIAMIX,
65 MEDIAMIX_ISPDWP,
66 MIPI_PHY1,
67 MIPI_PHY2,
68 /* HDMI ss */
69 HDMIMIX,
70 HDMI_PHY,
71 DDRMIX,
72 };
73
74 /* PU domain, add some hole to minimize the uboot change */
75 static struct imx_pwr_domain pu_domains[20] = {
76 [MIPI_PHY1] = IMX_PD_DOMAIN(MIPI_PHY1, false),
77 [PCIE_PHY] = IMX_PD_DOMAIN(PCIE_PHY, false),
78 [USB1_PHY] = IMX_PD_DOMAIN(USB1_PHY, true),
79 [USB2_PHY] = IMX_PD_DOMAIN(USB2_PHY, true),
80 [MLMIX] = IMX_MIX_DOMAIN(MLMIX, false),
81 [AUDIOMIX] = IMX_MIX_DOMAIN(AUDIOMIX, false),
82 [GPU2D] = IMX_PD_DOMAIN(GPU2D, false),
83 [GPUMIX] = IMX_MIX_DOMAIN(GPUMIX, false),
84 [VPUMIX] = IMX_MIX_DOMAIN(VPUMIX, false),
85 [GPU3D] = IMX_PD_DOMAIN(GPU3D, false),
86 [MEDIAMIX] = IMX_MIX_DOMAIN(MEDIAMIX, false),
87 [VPU_G1] = IMX_PD_DOMAIN(VPU_G1, false),
88 [VPU_G2] = IMX_PD_DOMAIN(VPU_G2, false),
89 [VPU_H1] = IMX_PD_DOMAIN(VPU_H1, false),
90 [HDMIMIX] = IMX_MIX_DOMAIN(HDMIMIX, false),
91 [HDMI_PHY] = IMX_PD_DOMAIN(HDMI_PHY, false),
92 [MIPI_PHY2] = IMX_PD_DOMAIN(MIPI_PHY2, false),
93 [HSIOMIX] = IMX_MIX_DOMAIN(HSIOMIX, false),
94 [MEDIAMIX_ISPDWP] = IMX_PD_DOMAIN(MEDIAMIX_ISPDWP, false),
95 };
96
97 static struct imx_noc_setting noc_setting[] = {
98 {MLMIX, 0x180, 0x180, 0x80000303, 0x0, 0x0},
99 {AUDIOMIX, 0x200, 0x200, 0x80000303, 0x0, 0x0},
100 {AUDIOMIX, 0x280, 0x480, 0x80000404, 0x0, 0x0},
101 {GPUMIX, 0x500, 0x580, 0x80000303, 0x0, 0x0},
102 {HDMIMIX, 0x600, 0x680, 0x80000202, 0x0, 0x1},
103 {HDMIMIX, 0x700, 0x700, 0x80000505, 0x0, 0x0},
104 {HSIOMIX, 0x780, 0x900, 0x80000303, 0x0, 0x0},
105 {MEDIAMIX, 0x980, 0xb80, 0x80000202, 0x0, 0x1},
106 {MEDIAMIX_ISPDWP, 0xc00, 0xd00, 0x80000505, 0x0, 0x0},
107 {VPU_G1, 0xd80, 0xd80, 0x80000303, 0x0, 0x0},
108 {VPU_G2, 0xe00, 0xe00, 0x80000303, 0x0, 0x0},
109 {VPU_H1, 0xe80, 0xe80, 0x80000303, 0x0, 0x0}
110 };
111
112 static struct clk_setting hsiomix_clk[] = {
113 { 0x8380, 0x0, CCM_ROOT_SLICE },
114 { 0x44d0, 0x0, CCM_CCGR },
115 { 0x45c0, 0x0, CCM_CCGR },
116 };
117
118 static struct aipstz_cfg aipstz5[] = {
119 {IMX_AIPSTZ5, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
120 {0},
121 };
122
123 static unsigned int pu_domain_status;
124
imx_noc_qos(unsigned int domain_id)125 static void imx_noc_qos(unsigned int domain_id)
126 {
127 unsigned int i;
128 uint32_t hurry;
129
130 if (domain_id == HDMIMIX) {
131 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22018);
132 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22010);
133
134 /* set GPR to make lcdif read hurry level 0x7 */
135 hurry = mmio_read_32(IMX_HDMI_CTL_BASE + TX_CONTROL0);
136 hurry |= 0x00077000;
137 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL0, hurry);
138 }
139
140 if (domain_id == MEDIAMIX) {
141 /* handle mediamix special */
142 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RSTn_CSR, 0x1FFFFFF);
143 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + CLK_EN_CSR, 0x1FFFFFF);
144 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RST_DIV, 0x40030000);
145
146 /* set GPR to make lcdif read hurry level 0x7 */
147 hurry = mmio_read_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL);
148 hurry |= 0xfc00;
149 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL, hurry);
150 /* set GPR to make isi write hurry level 0x7 */
151 hurry = mmio_read_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL);
152 hurry |= 0x1ff00000;
153 mmio_write_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL, hurry);
154 }
155
156 /* set MIX NoC */
157 for (i = 0; i < ARRAY_SIZE(noc_setting); i++) {
158 if (noc_setting[i].domain_id == domain_id) {
159 udelay(50);
160 uint32_t offset = noc_setting[i].start;
161
162 while (offset <= noc_setting[i].end) {
163 mmio_write_32(IMX_NOC_BASE + offset + 0x8, noc_setting[i].prioriy);
164 mmio_write_32(IMX_NOC_BASE + offset + 0xc, noc_setting[i].mode);
165 mmio_write_32(IMX_NOC_BASE + offset + 0x18, noc_setting[i].socket_qos_en);
166 offset += 0x80;
167 }
168 }
169 }
170 }
171
imx_gpc_pm_domain_enable(uint32_t domain_id,bool on)172 static void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on)
173 {
174 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id];
175 unsigned int i;
176
177 if (domain_id == HSIOMIX) {
178 for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) {
179 hsiomix_clk[i].val = mmio_read_32(IMX_CCM_BASE + hsiomix_clk[i].offset);
180 mmio_setbits_32(IMX_CCM_BASE + hsiomix_clk[i].offset,
181 hsiomix_clk[i].type == CCM_ROOT_SLICE ? BIT(28) : 0x3);
182 }
183 }
184
185 if (on) {
186 if (pwr_domain->need_sync) {
187 pu_domain_status |= (1 << domain_id);
188 }
189
190 if (domain_id == HDMIMIX) {
191 /* assert the reset */
192 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0x0);
193 /* enable all th function clock */
194 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF);
195 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e);
196 }
197
198 /* clear the PGC bit */
199 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
200
201 /* power up the domain */
202 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req);
203
204 /* wait for power request done */
205 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req)
206 ;
207
208 if (domain_id == HDMIMIX) {
209 /* wait for memory repair done for HDMIMIX */
210 while (!(mmio_read_32(IMX_SRC_BASE + 0x94) & BIT(8)))
211 ;
212 /* disable all the function clock */
213 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0x0);
214 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x0);
215 /* deassert the reset */
216 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0xffffffff);
217 /* enable all the clock again */
218 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF);
219 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e);
220 }
221
222 if (domain_id == HSIOMIX) {
223 /* enable HSIOMIX clock */
224 mmio_write_32(IMX_HSIOMIX_CTL_BASE, 0x2);
225 }
226
227 /* handle the ADB400 sync */
228 if (pwr_domain->need_sync) {
229 /* clear adb power down request */
230 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
231
232 /* wait for adb power request ack */
233 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))
234 ;
235 }
236
237 imx_noc_qos(domain_id);
238
239 /* AIPS5 config is lost when audiomix is off, so need to re-init it */
240 if (domain_id == AUDIOMIX) {
241 imx_aipstz_init(aipstz5);
242 }
243 } else {
244 if (pwr_domain->always_on) {
245 return;
246 }
247
248 if (pwr_domain->need_sync) {
249 pu_domain_status &= ~(1 << domain_id);
250 }
251
252 /* handle the ADB400 sync */
253 if (pwr_domain->need_sync) {
254 /* set adb power down request */
255 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
256
257 /* wait for adb power request ack */
258 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))
259 ;
260 }
261
262 /* set the PGC bit */
263 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
264
265 /*
266 * leave the G1, G2, H1 power domain on until VPUMIX power off,
267 * otherwise system will hang due to VPUMIX ACK
268 */
269 if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) {
270 return;
271 }
272
273 if (domain_id == VPUMIX) {
274 mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |
275 VPU_G2_PWR_REQ | VPU_H1_PWR_REQ);
276
277 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |
278 VPU_G2_PWR_REQ | VPU_H1_PWR_REQ))
279 ;
280 }
281
282 /* power down the domain */
283 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
284
285 /* wait for power request done */
286 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req)
287 ;
288
289 if (domain_id == HDMIMIX) {
290 /* disable all the clocks of HDMIMIX */
291 mmio_write_32(IMX_HDMI_CTL_BASE + 0x40, 0x0);
292 mmio_write_32(IMX_HDMI_CTL_BASE + 0x50, 0x0);
293 }
294 }
295
296 if (domain_id == HSIOMIX) {
297 for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) {
298 mmio_write_32(IMX_CCM_BASE + hsiomix_clk[i].offset, hsiomix_clk[i].val);
299 }
300 }
301 }
302
imx_gpc_init(void)303 void imx_gpc_init(void)
304 {
305 uint32_t val;
306 unsigned int i;
307
308 /* mask all the wakeup irq by default */
309 for (i = 0; i < IMR_NUM; i++) {
310 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
311 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
312 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
313 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
314 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
315 }
316
317 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
318 /* use GIC wake_request to wakeup C0~C3 from LPM */
319 val |= CORE_WKUP_FROM_GIC;
320 /* clear the MASTER0 LPM handshake */
321 val &= ~MASTER0_LPM_HSK;
322 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
323
324 /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
325 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
326 MASTER2_MAPPING));
327
328 /* set all mix/PU in A53 domain */
329 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0x3fffff);
330
331 /*
332 * Set the CORE & SCU power up timing:
333 * SW = 0x1, SW2ISO = 0x1;
334 * the CPU CORE and SCU power up timming counter
335 * is drived by 32K OSC, each domain's power up
336 * latency is (SW + SW2ISO) / 32768
337 */
338 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401);
339 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401);
340 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401);
341 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401);
342 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401);
343 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
344 (0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT));
345
346 /* set DUMMY PDN/PUP ACK by default for A53 domain */
347 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
348 A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
349
350 /* clear DSM by default */
351 val = mmio_read_32(IMX_GPC_BASE + SLPCR);
352 val &= ~SLPCR_EN_DSM;
353 /* enable the fast wakeup wait/stop mode */
354 val |= SLPCR_A53_FASTWUP_WAIT_MODE;
355 val |= SLPCR_A53_FASTWUP_STOP_MODE;
356 /* clear the RBC */
357 val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
358 /* set the STBY_COUNT to 0x5, (128 * 30)us */
359 val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
360 val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
361 mmio_write_32(IMX_GPC_BASE + SLPCR, val);
362
363 /*
364 * USB PHY power up needs to make sure RESET bit in SRC is clear,
365 * otherwise, the PU power up bit in GPC will NOT self-cleared.
366 * only need to do it once.
367 */
368 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
369 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
370
371 /* enable all the power domain by default */
372 for (i = 0; i < 101; i++) {
373 mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3);
374 }
375
376 for (i = 0; i < 20; i++) {
377 imx_gpc_pm_domain_enable(i, true);
378 }
379 }
380