Lines Matching full:disabled

4 …fiji -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare %s | FileCheck -check-prefix=DISABLED %s
18 ; DISABLED-LABEL: @mul_i16(
19 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
20 ; DISABLED-NEXT:    ret i16 [[MUL]]
43 ; DISABLED-LABEL: @smul24_i32(
44 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8
45 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8
46 ; DISABLED-NEXT:    [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8
47 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i32 [[LHS]], 8
48 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
49 ; DISABLED-NEXT:    ret i32 [[MUL]]
90 ; DISABLED-LABEL: @smul24_v2i32(
91 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8>
92 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8>
93 ; DISABLED-NEXT:    [[LSHR_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8>
94 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr <2 x i32> [[LHS]], <i32 8, i32 8>
95 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
96 ; DISABLED-NEXT:    ret <2 x i32> [[MUL]]
119 ; DISABLED-LABEL: @umul24_i32(
120 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215
121 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215
122 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
123 ; DISABLED-NEXT:    ret i32 [[MUL]]
158 ; DISABLED-LABEL: @umul24_v2i32(
159 ; DISABLED-NEXT:    [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215>
160 ; DISABLED-NEXT:    [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215>
161 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
162 ; DISABLED-NEXT:    ret <2 x i32> [[MUL]]
193 ; DISABLED-LABEL: @smul24_i64(
194 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40
195 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40
196 ; DISABLED-NEXT:    [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 40
197 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i64 [[LHS]], 40
198 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
199 ; DISABLED-NEXT:    ret i64 [[MUL]]
228 ; DISABLED-LABEL: @umul24_i64(
229 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215
230 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215
231 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
232 ; DISABLED-NEXT:    ret i64 [[MUL]]
263 ; DISABLED-LABEL: @smul24_i31(
264 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7
265 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7
266 ; DISABLED-NEXT:    [[LSHR_RHS:%.*]] = shl i31 [[RHS:%.*]], 7
267 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i31 [[LHS]], 7
268 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
269 ; DISABLED-NEXT:    ret i31 [[MUL]]
298 ; DISABLED-LABEL: @umul24_i31(
299 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215
300 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215
301 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
302 ; DISABLED-NEXT:    ret i31 [[MUL]]
349 ; DISABLED-LABEL: @umul24_v2i31(
350 ; DISABLED-NEXT:    [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215>
351 ; DISABLED-NEXT:    [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215>
352 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
353 ; DISABLED-NEXT:    ret <2 x i31> [[MUL]]
404 ; DISABLED-LABEL: @smul24_v2i31(
405 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8>
406 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8>
407 ; DISABLED-NEXT:    [[LSHR_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8>
408 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr <2 x i31> [[LHS]], <i31 8, i31 8>
409 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
410 ; DISABLED-NEXT:    ret <2 x i31> [[MUL]]
443 ; DISABLED-LABEL: @smul24_i33(
444 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9
445 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9
446 ; DISABLED-NEXT:    [[LSHR_RHS:%.*]] = shl i33 [[RHS:%.*]], 9
447 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i33 [[LHS]], 9
448 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
449 ; DISABLED-NEXT:    ret i33 [[MUL]]
478 ; DISABLED-LABEL: @umul24_i33(
479 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215
480 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215
481 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
482 ; DISABLED-NEXT:    ret i33 [[MUL]]
507 ; DISABLED-LABEL: @smul25_i32(
508 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7
509 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7
510 ; DISABLED-NEXT:    [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 7
511 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i32 [[LHS]], 7
512 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
513 ; DISABLED-NEXT:    ret i32 [[MUL]]
536 ; DISABLED-LABEL: @umul25_i32(
537 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431
538 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431
539 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
540 ; DISABLED-NEXT:    ret i32 [[MUL]]
591 ; DISABLED-LABEL: @smul24_v2i33(
592 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9>
593 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9>
594 ; DISABLED-NEXT:    [[LSHR_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9>
595 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr <2 x i33> [[LHS]], <i33 9, i33 9>
596 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]]
597 ; DISABLED-NEXT:    ret <2 x i33> [[MUL]]