1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare %s | FileCheck -check-prefix=SI %s 3; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=VI %s 4; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare %s | FileCheck -check-prefix=DISABLED %s 5 6define i16 @mul_i16(i16 %lhs, i16 %rhs) { 7; SI-LABEL: @mul_i16( 8; SI-NEXT: [[TMP1:%.*]] = zext i16 [[LHS:%.*]] to i32 9; SI-NEXT: [[TMP2:%.*]] = zext i16 [[RHS:%.*]] to i32 10; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 11; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i16 12; SI-NEXT: ret i16 [[MUL]] 13; 14; VI-LABEL: @mul_i16( 15; VI-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]] 16; VI-NEXT: ret i16 [[MUL]] 17; 18; DISABLED-LABEL: @mul_i16( 19; DISABLED-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]] 20; DISABLED-NEXT: ret i16 [[MUL]] 21; 22 %mul = mul i16 %lhs, %rhs 23 ret i16 %mul 24} 25 26define i32 @smul24_i32(i32 %lhs, i32 %rhs) { 27; SI-LABEL: @smul24_i32( 28; SI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 29; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 30; SI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 31; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8 32; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]]) 33; SI-NEXT: ret i32 [[MUL]] 34; 35; VI-LABEL: @smul24_i32( 36; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 37; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 38; VI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 39; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8 40; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]]) 41; VI-NEXT: ret i32 [[MUL]] 42; 43; DISABLED-LABEL: @smul24_i32( 44; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8 45; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8 46; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8 47; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8 48; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 49; DISABLED-NEXT: ret i32 [[MUL]] 50; 51 %shl.lhs = shl i32 %lhs, 8 52 %lhs24 = ashr i32 %shl.lhs, 8 53 %lshr.rhs = shl i32 %rhs, 8 54 %rhs24 = ashr i32 %lhs, 8 55 %mul = mul i32 %lhs24, %rhs24 56 ret i32 %mul 57} 58 59define <2 x i32> @smul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 60; SI-LABEL: @smul24_v2i32( 61; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8> 62; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8> 63; SI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8> 64; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[LHS]], <i32 8, i32 8> 65; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 66; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 67; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 68; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 69; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP3]]) 70; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP2]], i32 [[TMP4]]) 71; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0 72; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 73; SI-NEXT: ret <2 x i32> [[MUL]] 74; 75; VI-LABEL: @smul24_v2i32( 76; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8> 77; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8> 78; VI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8> 79; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[LHS]], <i32 8, i32 8> 80; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 81; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 82; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 83; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 84; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP3]]) 85; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP2]], i32 [[TMP4]]) 86; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0 87; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 88; VI-NEXT: ret <2 x i32> [[MUL]] 89; 90; DISABLED-LABEL: @smul24_v2i32( 91; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8> 92; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8> 93; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8> 94; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[LHS]], <i32 8, i32 8> 95; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]] 96; DISABLED-NEXT: ret <2 x i32> [[MUL]] 97; 98 %shl.lhs = shl <2 x i32> %lhs, <i32 8, i32 8> 99 %lhs24 = ashr <2 x i32> %shl.lhs, <i32 8, i32 8> 100 %lshr.rhs = shl <2 x i32> %rhs, <i32 8, i32 8> 101 %rhs24 = ashr <2 x i32> %lhs, <i32 8, i32 8> 102 %mul = mul <2 x i32> %lhs24, %rhs24 103 ret <2 x i32> %mul 104} 105 106define i32 @umul24_i32(i32 %lhs, i32 %rhs) { 107; SI-LABEL: @umul24_i32( 108; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 109; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 110; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]]) 111; SI-NEXT: ret i32 [[MUL]] 112; 113; VI-LABEL: @umul24_i32( 114; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 115; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 116; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]]) 117; VI-NEXT: ret i32 [[MUL]] 118; 119; DISABLED-LABEL: @umul24_i32( 120; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215 121; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215 122; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 123; DISABLED-NEXT: ret i32 [[MUL]] 124; 125 %lhs24 = and i32 %lhs, 16777215 126 %rhs24 = and i32 %rhs, 16777215 127 %mul = mul i32 %lhs24, %rhs24 128 ret i32 %mul 129} 130 131define <2 x i32> @umul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 132; SI-LABEL: @umul24_v2i32( 133; SI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215> 134; SI-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215> 135; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 136; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 137; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 138; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 139; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP3]]) 140; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP2]], i32 [[TMP4]]) 141; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0 142; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 143; SI-NEXT: ret <2 x i32> [[MUL]] 144; 145; VI-LABEL: @umul24_v2i32( 146; VI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215> 147; VI-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215> 148; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[LHS24]], i64 0 149; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[LHS24]], i64 1 150; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[RHS24]], i64 0 151; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[RHS24]], i64 1 152; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP3]]) 153; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP2]], i32 [[TMP4]]) 154; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0 155; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1 156; VI-NEXT: ret <2 x i32> [[MUL]] 157; 158; DISABLED-LABEL: @umul24_v2i32( 159; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215> 160; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215> 161; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]] 162; DISABLED-NEXT: ret <2 x i32> [[MUL]] 163; 164 %lhs24 = and <2 x i32> %lhs, <i32 16777215, i32 16777215> 165 %rhs24 = and <2 x i32> %rhs, <i32 16777215, i32 16777215> 166 %mul = mul <2 x i32> %lhs24, %rhs24 167 ret <2 x i32> %mul 168} 169 170define i64 @smul24_i64(i64 %lhs, i64 %rhs) { 171; SI-LABEL: @smul24_i64( 172; SI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 173; SI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 174; SI-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 175; SI-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 40 176; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 177; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 178; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 179; SI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64 180; SI-NEXT: ret i64 [[MUL]] 181; 182; VI-LABEL: @smul24_i64( 183; VI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 184; VI-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 185; VI-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 186; VI-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 40 187; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 188; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 189; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 190; VI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64 191; VI-NEXT: ret i64 [[MUL]] 192; 193; DISABLED-LABEL: @smul24_i64( 194; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40 195; DISABLED-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40 196; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 40 197; DISABLED-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 40 198; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 199; DISABLED-NEXT: ret i64 [[MUL]] 200; 201 %shl.lhs = shl i64 %lhs, 40 202 %lhs24 = ashr i64 %shl.lhs, 40 203 %lshr.rhs = shl i64 %rhs, 40 204 %rhs24 = ashr i64 %lhs, 40 205 %mul = mul i64 %lhs24, %rhs24 206 ret i64 %mul 207} 208 209define i64 @umul24_i64(i64 %lhs, i64 %rhs) { 210; SI-LABEL: @umul24_i64( 211; SI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 212; SI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 213; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 214; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 215; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 216; SI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64 217; SI-NEXT: ret i64 [[MUL]] 218; 219; VI-LABEL: @umul24_i64( 220; VI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 221; VI-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 222; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32 223; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32 224; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 225; VI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64 226; VI-NEXT: ret i64 [[MUL]] 227; 228; DISABLED-LABEL: @umul24_i64( 229; DISABLED-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215 230; DISABLED-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215 231; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]] 232; DISABLED-NEXT: ret i64 [[MUL]] 233; 234 %lhs24 = and i64 %lhs, 16777215 235 %rhs24 = and i64 %rhs, 16777215 236 %mul = mul i64 %lhs24, %rhs24 237 ret i64 %mul 238} 239 240define i31 @smul24_i31(i31 %lhs, i31 %rhs) { 241; SI-LABEL: @smul24_i31( 242; SI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 243; SI-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 244; SI-NEXT: [[LSHR_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 245; SI-NEXT: [[RHS24:%.*]] = ashr i31 [[LHS]], 7 246; SI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32 247; SI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32 248; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 249; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 250; SI-NEXT: ret i31 [[MUL]] 251; 252; VI-LABEL: @smul24_i31( 253; VI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 254; VI-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 255; VI-NEXT: [[LSHR_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 256; VI-NEXT: [[RHS24:%.*]] = ashr i31 [[LHS]], 7 257; VI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32 258; VI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32 259; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 260; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 261; VI-NEXT: ret i31 [[MUL]] 262; 263; DISABLED-LABEL: @smul24_i31( 264; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7 265; DISABLED-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7 266; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i31 [[RHS:%.*]], 7 267; DISABLED-NEXT: [[RHS24:%.*]] = ashr i31 [[LHS]], 7 268; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]] 269; DISABLED-NEXT: ret i31 [[MUL]] 270; 271 %shl.lhs = shl i31 %lhs, 7 272 %lhs24 = ashr i31 %shl.lhs, 7 273 %lshr.rhs = shl i31 %rhs, 7 274 %rhs24 = ashr i31 %lhs, 7 275 %mul = mul i31 %lhs24, %rhs24 276 ret i31 %mul 277} 278 279define i31 @umul24_i31(i31 %lhs, i31 %rhs) { 280; SI-LABEL: @umul24_i31( 281; SI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 282; SI-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 283; SI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32 284; SI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32 285; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 286; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 287; SI-NEXT: ret i31 [[MUL]] 288; 289; VI-LABEL: @umul24_i31( 290; VI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 291; VI-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 292; VI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32 293; VI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32 294; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 295; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31 296; VI-NEXT: ret i31 [[MUL]] 297; 298; DISABLED-LABEL: @umul24_i31( 299; DISABLED-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215 300; DISABLED-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215 301; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]] 302; DISABLED-NEXT: ret i31 [[MUL]] 303; 304 %lhs24 = and i31 %lhs, 16777215 305 %rhs24 = and i31 %rhs, 16777215 306 %mul = mul i31 %lhs24, %rhs24 307 ret i31 %mul 308} 309 310define <2 x i31> @umul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) { 311; SI-LABEL: @umul24_v2i31( 312; SI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215> 313; SI-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215> 314; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 315; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 316; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 317; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 318; SI-NEXT: [[TMP5:%.*]] = zext i31 [[TMP1]] to i32 319; SI-NEXT: [[TMP6:%.*]] = zext i31 [[TMP3]] to i32 320; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP5]], i32 [[TMP6]]) 321; SI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 322; SI-NEXT: [[TMP9:%.*]] = zext i31 [[TMP2]] to i32 323; SI-NEXT: [[TMP10:%.*]] = zext i31 [[TMP4]] to i32 324; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP9]], i32 [[TMP10]]) 325; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 326; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0 327; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 328; SI-NEXT: ret <2 x i31> [[MUL]] 329; 330; VI-LABEL: @umul24_v2i31( 331; VI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215> 332; VI-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215> 333; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 334; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 335; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 336; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 337; VI-NEXT: [[TMP5:%.*]] = zext i31 [[TMP1]] to i32 338; VI-NEXT: [[TMP6:%.*]] = zext i31 [[TMP3]] to i32 339; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP5]], i32 [[TMP6]]) 340; VI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 341; VI-NEXT: [[TMP9:%.*]] = zext i31 [[TMP2]] to i32 342; VI-NEXT: [[TMP10:%.*]] = zext i31 [[TMP4]] to i32 343; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP9]], i32 [[TMP10]]) 344; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 345; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0 346; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 347; VI-NEXT: ret <2 x i31> [[MUL]] 348; 349; DISABLED-LABEL: @umul24_v2i31( 350; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215> 351; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215> 352; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]] 353; DISABLED-NEXT: ret <2 x i31> [[MUL]] 354; 355 %lhs24 = and <2 x i31> %lhs, <i31 16777215, i31 16777215> 356 %rhs24 = and <2 x i31> %rhs, <i31 16777215, i31 16777215> 357 %mul = mul <2 x i31> %lhs24, %rhs24 358 ret <2 x i31> %mul 359} 360 361define <2 x i31> @smul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) { 362; SI-LABEL: @smul24_v2i31( 363; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8> 364; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8> 365; SI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8> 366; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[LHS]], <i31 8, i31 8> 367; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 368; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 369; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 370; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 371; SI-NEXT: [[TMP5:%.*]] = sext i31 [[TMP1]] to i32 372; SI-NEXT: [[TMP6:%.*]] = sext i31 [[TMP3]] to i32 373; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]]) 374; SI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 375; SI-NEXT: [[TMP9:%.*]] = sext i31 [[TMP2]] to i32 376; SI-NEXT: [[TMP10:%.*]] = sext i31 [[TMP4]] to i32 377; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]]) 378; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 379; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0 380; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 381; SI-NEXT: ret <2 x i31> [[MUL]] 382; 383; VI-LABEL: @smul24_v2i31( 384; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8> 385; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8> 386; VI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8> 387; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[LHS]], <i31 8, i31 8> 388; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i31> [[LHS24]], i64 0 389; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i31> [[LHS24]], i64 1 390; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i31> [[RHS24]], i64 0 391; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i31> [[RHS24]], i64 1 392; VI-NEXT: [[TMP5:%.*]] = sext i31 [[TMP1]] to i32 393; VI-NEXT: [[TMP6:%.*]] = sext i31 [[TMP3]] to i32 394; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]]) 395; VI-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i31 396; VI-NEXT: [[TMP9:%.*]] = sext i31 [[TMP2]] to i32 397; VI-NEXT: [[TMP10:%.*]] = sext i31 [[TMP4]] to i32 398; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]]) 399; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31 400; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0 401; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1 402; VI-NEXT: ret <2 x i31> [[MUL]] 403; 404; DISABLED-LABEL: @smul24_v2i31( 405; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8> 406; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8> 407; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8> 408; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[LHS]], <i31 8, i31 8> 409; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]] 410; DISABLED-NEXT: ret <2 x i31> [[MUL]] 411; 412 %shl.lhs = shl <2 x i31> %lhs, <i31 8, i31 8> 413 %lhs24 = ashr <2 x i31> %shl.lhs, <i31 8, i31 8> 414 %lshr.rhs = shl <2 x i31> %rhs, <i31 8, i31 8> 415 %rhs24 = ashr <2 x i31> %lhs, <i31 8, i31 8> 416 %mul = mul <2 x i31> %lhs24, %rhs24 417 ret <2 x i31> %mul 418} 419 420define i33 @smul24_i33(i33 %lhs, i33 %rhs) { 421; SI-LABEL: @smul24_i33( 422; SI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 423; SI-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 424; SI-NEXT: [[LSHR_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 425; SI-NEXT: [[RHS24:%.*]] = ashr i33 [[LHS]], 9 426; SI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32 427; SI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32 428; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 429; SI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i33 430; SI-NEXT: ret i33 [[MUL]] 431; 432; VI-LABEL: @smul24_i33( 433; VI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 434; VI-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 435; VI-NEXT: [[LSHR_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 436; VI-NEXT: [[RHS24:%.*]] = ashr i33 [[LHS]], 9 437; VI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32 438; VI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32 439; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]]) 440; VI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i33 441; VI-NEXT: ret i33 [[MUL]] 442; 443; DISABLED-LABEL: @smul24_i33( 444; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9 445; DISABLED-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9 446; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i33 [[RHS:%.*]], 9 447; DISABLED-NEXT: [[RHS24:%.*]] = ashr i33 [[LHS]], 9 448; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 449; DISABLED-NEXT: ret i33 [[MUL]] 450; 451 %shl.lhs = shl i33 %lhs, 9 452 %lhs24 = ashr i33 %shl.lhs, 9 453 %lshr.rhs = shl i33 %rhs, 9 454 %rhs24 = ashr i33 %lhs, 9 455 %mul = mul i33 %lhs24, %rhs24 456 ret i33 %mul 457} 458 459define i33 @umul24_i33(i33 %lhs, i33 %rhs) { 460; SI-LABEL: @umul24_i33( 461; SI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 462; SI-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 463; SI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32 464; SI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32 465; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 466; SI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i33 467; SI-NEXT: ret i33 [[MUL]] 468; 469; VI-LABEL: @umul24_i33( 470; VI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 471; VI-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 472; VI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32 473; VI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32 474; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]]) 475; VI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i33 476; VI-NEXT: ret i33 [[MUL]] 477; 478; DISABLED-LABEL: @umul24_i33( 479; DISABLED-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215 480; DISABLED-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215 481; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]] 482; DISABLED-NEXT: ret i33 [[MUL]] 483; 484 %lhs24 = and i33 %lhs, 16777215 485 %rhs24 = and i33 %rhs, 16777215 486 %mul = mul i33 %lhs24, %rhs24 487 ret i33 %mul 488} 489 490define i32 @smul25_i32(i32 %lhs, i32 %rhs) { 491; SI-LABEL: @smul25_i32( 492; SI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 493; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 494; SI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 495; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 7 496; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 497; SI-NEXT: ret i32 [[MUL]] 498; 499; VI-LABEL: @smul25_i32( 500; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 501; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 502; VI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 503; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 7 504; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 505; VI-NEXT: ret i32 [[MUL]] 506; 507; DISABLED-LABEL: @smul25_i32( 508; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7 509; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7 510; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 7 511; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 7 512; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 513; DISABLED-NEXT: ret i32 [[MUL]] 514; 515 %shl.lhs = shl i32 %lhs, 7 516 %lhs24 = ashr i32 %shl.lhs, 7 517 %lshr.rhs = shl i32 %rhs, 7 518 %rhs24 = ashr i32 %lhs, 7 519 %mul = mul i32 %lhs24, %rhs24 520 ret i32 %mul 521} 522 523define i32 @umul25_i32(i32 %lhs, i32 %rhs) { 524; SI-LABEL: @umul25_i32( 525; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 526; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 527; SI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 528; SI-NEXT: ret i32 [[MUL]] 529; 530; VI-LABEL: @umul25_i32( 531; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 532; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 533; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 534; VI-NEXT: ret i32 [[MUL]] 535; 536; DISABLED-LABEL: @umul25_i32( 537; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431 538; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431 539; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]] 540; DISABLED-NEXT: ret i32 [[MUL]] 541; 542 %lhs24 = and i32 %lhs, 33554431 543 %rhs24 = and i32 %rhs, 33554431 544 %mul = mul i32 %lhs24, %rhs24 545 ret i32 %mul 546} 547 548define <2 x i33> @smul24_v2i33(<2 x i33> %lhs, <2 x i33> %rhs) { 549; SI-LABEL: @smul24_v2i33( 550; SI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9> 551; SI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9> 552; SI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9> 553; SI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[LHS]], <i33 9, i33 9> 554; SI-NEXT: [[TMP1:%.*]] = extractelement <2 x i33> [[LHS24]], i64 0 555; SI-NEXT: [[TMP2:%.*]] = extractelement <2 x i33> [[LHS24]], i64 1 556; SI-NEXT: [[TMP3:%.*]] = extractelement <2 x i33> [[RHS24]], i64 0 557; SI-NEXT: [[TMP4:%.*]] = extractelement <2 x i33> [[RHS24]], i64 1 558; SI-NEXT: [[TMP5:%.*]] = trunc i33 [[TMP1]] to i32 559; SI-NEXT: [[TMP6:%.*]] = trunc i33 [[TMP3]] to i32 560; SI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]]) 561; SI-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i33 562; SI-NEXT: [[TMP9:%.*]] = trunc i33 [[TMP2]] to i32 563; SI-NEXT: [[TMP10:%.*]] = trunc i33 [[TMP4]] to i32 564; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]]) 565; SI-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i33 566; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i33> undef, i33 [[TMP8]], i64 0 567; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1 568; SI-NEXT: ret <2 x i33> [[MUL]] 569; 570; VI-LABEL: @smul24_v2i33( 571; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9> 572; VI-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9> 573; VI-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9> 574; VI-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[LHS]], <i33 9, i33 9> 575; VI-NEXT: [[TMP1:%.*]] = extractelement <2 x i33> [[LHS24]], i64 0 576; VI-NEXT: [[TMP2:%.*]] = extractelement <2 x i33> [[LHS24]], i64 1 577; VI-NEXT: [[TMP3:%.*]] = extractelement <2 x i33> [[RHS24]], i64 0 578; VI-NEXT: [[TMP4:%.*]] = extractelement <2 x i33> [[RHS24]], i64 1 579; VI-NEXT: [[TMP5:%.*]] = trunc i33 [[TMP1]] to i32 580; VI-NEXT: [[TMP6:%.*]] = trunc i33 [[TMP3]] to i32 581; VI-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP5]], i32 [[TMP6]]) 582; VI-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i33 583; VI-NEXT: [[TMP9:%.*]] = trunc i33 [[TMP2]] to i32 584; VI-NEXT: [[TMP10:%.*]] = trunc i33 [[TMP4]] to i32 585; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]]) 586; VI-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i33 587; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i33> undef, i33 [[TMP8]], i64 0 588; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1 589; VI-NEXT: ret <2 x i33> [[MUL]] 590; 591; DISABLED-LABEL: @smul24_v2i33( 592; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9> 593; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9> 594; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9> 595; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[LHS]], <i33 9, i33 9> 596; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]] 597; DISABLED-NEXT: ret <2 x i33> [[MUL]] 598; 599 %shl.lhs = shl <2 x i33> %lhs, <i33 9, i33 9> 600 %lhs24 = ashr <2 x i33> %shl.lhs, <i33 9, i33 9> 601 %lshr.rhs = shl <2 x i33> %rhs, <i33 9, i33 9> 602 %rhs24 = ashr <2 x i33> %lhs, <i33 9, i33 9> 603 %mul = mul <2 x i33> %lhs24, %rhs24 604 ret <2 x i33> %mul 605} 606