Lines Matching refs:csio
724 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *csio, struct radeon_surf *surf) in gfx6_surface_settings() argument
726 surf->surf_alignment = csio->baseAlign; in gfx6_surface_settings()
727 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1; in gfx6_surface_settings()
731 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) { in gfx6_surface_settings()
732 surf->u.legacy.bankw = csio->pTileInfo->bankWidth; in gfx6_surface_settings()
733 surf->u.legacy.bankh = csio->pTileInfo->bankHeight; in gfx6_surface_settings()
734 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio; in gfx6_surface_settings()
735 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes; in gfx6_surface_settings()
736 surf->u.legacy.num_banks = csio->pTileInfo->banks; in gfx6_surface_settings()
737 surf->u.legacy.macro_tile_index = csio->macroModeIndex; in gfx6_surface_settings()
755 AddrBaseSwizzleIn.tileIndex = csio->tileIndex; in gfx6_surface_settings()
756 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex; in gfx6_surface_settings()
757 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo; in gfx6_surface_settings()
758 AddrBaseSwizzleIn.tileMode = csio->tileMode; in gfx6_surface_settings()