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/external/elfutils/tests/
Drun-allregs.sh48 29: %mm0 (mm0), unsigned 64 bits
49 30: %mm1 (mm1), unsigned 64 bits
50 31: %mm2 (mm2), unsigned 64 bits
51 32: %mm3 (mm3), unsigned 64 bits
52 33: %mm4 (mm4), unsigned 64 bits
53 34: %mm5 (mm5), unsigned 64 bits
54 35: %mm6 (mm6), unsigned 64 bits
55 36: %mm7 (mm7), unsigned 64 bits
85 0: %rax (rax), signed 64 bits
86 1: %rdx (rdx), signed 64 bits
[all …]
/external/OpenCSD/decoder/tests/snapshots/a57_single_step/
Ddevice1.ini7 X0(size:64)=0x00000000002971C8
8 X1(size:64)=0x00000000910163E0
9 X2(size:64)=0x00000000FFD0C1C4
10 X3(size:64)=0x0000000000345000
11 X4(size:64)=0x0000000000000004
12 X5(size:64)=0x00000000FC01EB50
13 X6(size:64)=0x00000000FC01EB4C
14 X7(size:64)=0x0000000000000000
15 X8(size:64)=0x00000000FC01E9C8
16 X9(size:64)=0xFFFFFFFFFFFFFFFF
[all …]
/external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/
Ddevice1.ini7 X0(size:64)=0x00000000002971C8
8 X1(size:64)=0x00000000910163E0
9 X2(size:64)=0x00000000FFD0C1C4
10 X3(size:64)=0x0000000000345000
11 X4(size:64)=0x0000000000000004
12 X5(size:64)=0x00000000FC01EB50
13 X6(size:64)=0x00000000FC01EB4C
14 X7(size:64)=0x0000000000000000
15 X8(size:64)=0x00000000FC01E9C8
16 X9(size:64)=0xFFFFFFFFFFFFFFFF
[all …]
/external/libgav1/libgav1/src/
Dprediction_mask.cc108 // This table (and the one below) contains a few leading zeros and trailing 64s
114 53, 60, 63, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
115 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
116 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64};
122 46, 58, 62, 63, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
123 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
124 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64};
129 43, 57, 62, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
130 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64};
175 64 - mask_value; in GenerateWedgeMask()
[all …]
/external/llvm/test/CodeGen/X86/
Davx512vbmi-intrinsics.ll3 declare <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
5 define <64 x i8>@test_int_x86_avx512_mask_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x…
15 …%res = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8>…
16 …%res1 = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8…
17 …%res2 = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8…
18 %res3 = add <64 x i8> %res, %res1
19 %res4 = add <64 x i8> %res3, %res2
20 ret <64 x i8> %res4
23 declare <64 x i8> @llvm.x86.avx512.mask.pmultishift.qb.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
25 define <64 x i8>@test_int_x86_avx512_mask_pmultishift_qb_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8…
[all …]
Dabi-isel.ll4 …n-linux-gnu -march=x86-64 -relocation-model=static -code-model=small -pre-RA-sched=list-ilp | File…
5 …own-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small -pre-RA-sched=list-ilp | FileC…
11 …pple-darwin -march=x86-64 -relocation-model=static -code-model=small -pre-RA-sched=list-ilp | File…
12 …-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small -pre-RA-sched=list-ilp | …
13 …apple-darwin -march=x86-64 -relocation-model=pic -code-model=small -pre-RA-sched=list-ilp | FileCh…
40 ; LINUX-64-STATIC-LABEL: foo00:
41 ; LINUX-64-STATIC: movl src(%rip), [[EAX:%e.x]]
42 ; LINUX-64-STATIC: movl [[EAX]], dst
43 ; LINUX-64-STATIC: ret
55 ; LINUX-64-PIC-LABEL: foo00:
[all …]
/external/llvm-project/clang/include/clang/Basic/
DBuiltinsHexagonMapCustomDep.def39 CUSTOM_BUILTIN_MAPPING(V6_vS32b_qpred_ai, 64)
41 CUSTOM_BUILTIN_MAPPING(V6_vS32b_nqpred_ai, 64)
43 CUSTOM_BUILTIN_MAPPING(V6_vS32b_nt_qpred_ai, 64)
45 CUSTOM_BUILTIN_MAPPING(V6_vS32b_nt_nqpred_ai, 64)
47 CUSTOM_BUILTIN_MAPPING(V6_vaddbq, 64)
49 CUSTOM_BUILTIN_MAPPING(V6_vsubbq, 64)
51 CUSTOM_BUILTIN_MAPPING(V6_vaddbnq, 64)
53 CUSTOM_BUILTIN_MAPPING(V6_vsubbnq, 64)
55 CUSTOM_BUILTIN_MAPPING(V6_vaddhq, 64)
57 CUSTOM_BUILTIN_MAPPING(V6_vsubhq, 64)
[all …]
/external/llvm-project/llvm/unittests/Bitcode/
DDataLayoutUpgradeTest.cpp18 UpgradeDataLayoutString("e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128", in TEST()
21 "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32", "i686-pc-windows-msvc"); in TEST()
22 std::string DL3 = UpgradeDataLayoutString("e-m:o-i64:64-i128:128-n32:64-S128", in TEST()
24 EXPECT_EQ(DL1, "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64" in TEST()
25 "-f80:128-n8:16:32:64-S128"); in TEST()
26 EXPECT_EQ(DL2, "e-m:w-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64" in TEST()
28 EXPECT_EQ(DL3, "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128" in TEST()
29 "-n32:64-S128"); in TEST()
33 EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"), "e-p:64:64-G1"); in TEST()
38 "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" in TEST()
[all …]
/external/llvm-project/llvm/test/MC/X86/
DX87-64.s14 // CHECK: faddl 64(%rdx)
16 faddl 64(%rdx)
18 // CHECK: faddl -64(%rdx,%rax,4)
20 faddl -64(%rdx,%rax,4)
22 // CHECK: faddl 64(%rdx,%rax,4)
24 faddl 64(%rdx,%rax,4)
26 // CHECK: faddl 64(%rdx,%rax)
28 faddl 64(%rdx,%rax)
42 // CHECK: fadds 64(%rdx)
44 fadds 64(%rdx)
[all …]
DI86-64.s7 // CHECK: adcb $0, 64(%rdx)
9 adcb $0, 64(%rdx)
11 // CHECK: adcb $0, 64(%rdx,%rax,4)
13 adcb $0, 64(%rdx,%rax,4)
15 // CHECK: adcb $0, -64(%rdx,%rax,4)
17 adcb $0, -64(%rdx,%rax,4)
19 // CHECK: adcb $0, 64(%rdx,%rax)
21 adcb $0, 64(%rdx,%rax)
39 // CHECK: adcb 64(%rdx), %r14b
41 adcb 64(%rdx), %r14b
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dabi-isel.ll4 …-model=static -code-model=small -pre-RA-sched=list-ilp | FileCheck %s -check-prefix=LINUX-64-STATIC
7 …cation-model=pic -code-model=small -pre-RA-sched=list-ilp | FileCheck %s -check-prefix=LINUX-64-PIC
13 …model=static -code-model=small -pre-RA-sched=list-ilp | FileCheck %s -check-prefix=DARWIN-64-STATIC
14 …amic-no-pic -code-model=small -pre-RA-sched=list-ilp | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
15 …ation-model=pic -code-model=small -pre-RA-sched=list-ilp | FileCheck %s -check-prefix=DARWIN-64-PIC
37 ; LINUX-64-STATIC-LABEL: foo00:
38 ; LINUX-64-STATIC: # %bb.0: # %entry
39 ; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
40 ; LINUX-64-STATIC-NEXT: movl (%rax), %eax
41 ; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rcx
[all …]
Davx512vbmi-intrinsics.ll5 declare <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8>, <64 x i8>)
7 define <64 x i8>@test_int_x86_avx512_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2) {
12 %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1)
13 ret <64 x i8> %1
16 define <64 x i8>@test_int_x86_avx512_mask_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x…
30 %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1)
31 %2 = bitcast i64 %x3 to <64 x i1>
32 %3 = select <64 x i1> %2, <64 x i8> %1, <64 x i8> %x2
33 ret <64 x i8> %3
36 define <64 x i8>@test_int_x86_avx512_maskz_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, i64 %x3) {
[all …]
Davx512vbmi-intrinsics-upgrade.ll5 declare <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
7 define <64 x i8>@test_int_x86_avx512_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2) {
12 …%res = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8>…
13 ret <64 x i8> %res
16 define <64 x i8>@test_int_x86_avx512_mask_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x…
30 …%res = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8>…
31 ret <64 x i8> %res
34 define <64 x i8>@test_int_x86_avx512_maskz_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, i64 %x3) {
46 …%res = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8>…
47 ret <64 x i8> %res
[all …]
Dvec-strict-cmp-128.ll3 …N: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=SSE-64
5 …UN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=AVX-64
7 …6_64-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=AVX512-64
9 …< %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=AVX512F-64
26 ; SSE-64-LABEL: test_v4f32_oeq_q:
27 ; SSE-64: # %bb.0:
28 ; SSE-64-NEXT: cmpeqps %xmm3, %xmm2
29 ; SSE-64-NEXT: andps %xmm2, %xmm0
30 ; SSE-64-NEXT: andnps %xmm1, %xmm2
31 ; SSE-64-NEXT: orps %xmm2, %xmm0
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dselect.ll5 …inux-gnu -mcpu=mips64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64
6 …ux-gnu -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64R2
7 …ux-gnu -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64R6
32 ; 64-LABEL: i32_icmp_ne_i32_val:
33 ; 64: # %bb.0: # %entry
34 ; 64-NEXT: movn $5, $6, $4
35 ; 64-NEXT: jr $ra
36 ; 64-NEXT: move $2, $5
38 ; 64R2-LABEL: i32_icmp_ne_i32_val:
39 ; 64R2: # %bb.0: # %entry
[all …]
/external/llvm/test/MC/Mips/
Drotations64.s1 # RUN: llvm-mc %s -arch=mips -mcpu=mips64 -show-encoding | FileCheck %s -check-prefix=CHECK-64
2 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
3 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
5 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r6 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
10 # CHECK-64: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
11 # CHECK-64: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
12 # CHECK-64: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
13 # CHECK-64: or $4, $4, $1 # encoding: [0x00,0x81,0x20,0x25]
14 # CHECK-64R: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
[all …]
/external/llvm-project/llvm/test/MC/Mips/
Drotations64.s1 # RUN: llvm-mc %s -arch=mips -mcpu=mips64 -show-encoding | FileCheck %s -check-prefix=CHECK-64
2 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
3 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
5 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r6 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
10 # CHECK-64: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
11 # CHECK-64: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
12 # CHECK-64: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
13 # CHECK-64: or $4, $4, $1 # encoding: [0x00,0x81,0x20,0x25]
14 # CHECK-64R: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
[all …]
/external/llvm/test/Object/
Dobj2yaml.test2 RUN: obj2yaml %p/Inputs/trivial-object-test.coff-x86-64 | FileCheck %s --check-prefix COFF-X86-64
5 RUN: obj2yaml %p/Inputs/trivial-object-test.elf-x86-64 | FileCheck %s --check-prefix ELF-X86-64
7 RUN: obj2yaml %p/Inputs/unwind-section.elf-x86-64 \
8 RUN: | FileCheck %s --check-prefix ELF-X86-64-UNWIND
93 COFF-X86-64: header:
94 COFF-X86-64-NEXT: Machine: IMAGE_FILE_MACHINE_AMD64
96 COFF-X86-64: sections:
97 COFF-X86-64-NEXT: - Name: .text
98 COFF-X86-64-NEXT: Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_R…
99 COFF-X86-64-NEXT: Alignment: 16
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dintrinsics-v60-vcmp.ll3 @d = external global <16 x i32>, align 64
9 %v0 = load <16 x i32>, <16 x i32>* @d, align 64
10 %v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)
11 %v2 = tail call <64 x i1> @llvm.hexagon.V6.veqb.and(<64 x i1> %v1, <16 x i32> %a, <16 x i32> %b)
12 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v2, i32 -1)
13 store <16 x i32> %v3, <16 x i32>* @d, align 64
21 %v0 = load <16 x i32>, <16 x i32>* @d, align 64
22 %v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)
23 %v2 = tail call <64 x i1> @llvm.hexagon.V6.veqh.and(<64 x i1> %v1, <16 x i32> %a, <16 x i32> %b)
24 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v2, i32 -1)
[all …]
Dlarge-number-of-preds.ll11 %v0 = alloca [64 x float], align 16
13 %v2 = bitcast [64 x float]* %v0 to i8*
16 %v4 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 35
18 %v5 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 0
22 %v8 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 36
24 %v9 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 1
26 %v10 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 37
28 %v11 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 2
30 %v12 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 34
32 %v13 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 33
[all …]
/external/llvm-project/clang/test/CodeGen/
Dtarget-data.c3 // I686-UNKNOWN: target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:…
7 // I686-DARWIN: target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:1…
11 // I686-WIN32: target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8…
15 // I686-CYGWIN: target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n…
19 // I686-MACHO: target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32…
23 // X86_64: target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S…
31 // SPARC-V8: target datalayout = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"
35 // SPARC-V9: target datalayout = "E-m:e-i64:64-n32:64-S128"
41 // MIPS-32EL: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
47 // MIPS-32EB: target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dminmax-64b.ll7 define <64 x i8> @test_00(<64 x i8> %v0, <64 x i8> %v1) #0 {
8 %t0 = icmp slt <64 x i8> %v0, %v1
9 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
10 ret <64 x i8> %t1
15 define <64 x i8> @test_01(<64 x i8> %v0, <64 x i8> %v1) #0 {
16 %t0 = icmp sle <64 x i8> %v0, %v1
17 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
18 ret <64 x i8> %t1
23 define <64 x i8> @test_02(<64 x i8> %v0, <64 x i8> %v1) #0 {
24 %t0 = icmp sgt <64 x i8> %v0, %v1
[all …]
Dminmax-128b.ll143 define <64 x i16> @test_10(<64 x i16> %v0, <64 x i16> %v1) #0 {
144 %t0 = icmp slt <64 x i16> %v0, %v1
145 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
146 ret <64 x i16> %t1
151 define <64 x i16> @test_11(<64 x i16> %v0, <64 x i16> %v1) #0 {
152 %t0 = icmp sle <64 x i16> %v0, %v1
153 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
154 ret <64 x i16> %t1
159 define <64 x i16> @test_12(<64 x i16> %v0, <64 x i16> %v1) #0 {
160 %t0 = icmp sgt <64 x i16> %v0, %v1
[all …]
Dalign2-64b.ll6 define <64 x i8> @test_00(<64 x i8> %v0, <64 x i8> %v1) #0 {
7 …%t0 = shufflevector <64 x i8> %v0, <64 x i8> %v1, <64 x i32><i32 0, i32 1, i32 2, i32 3, i32 4, i3…
8 ret <64 x i8> %t0
14 define <64 x i8> @test_01(<64 x i8> %v0, <64 x i8> %v1) #0 {
15 …%t0 = shufflevector <64 x i8> %v0, <64 x i8> %v1, <64 x i32><i32 1, i32 2, i32 3, i32 4, i32 5, i3…
16 ret <64 x i8> %t0
22 define <64 x i8> @test_02(<64 x i8> %v0, <64 x i8> %v1) #0 {
23 …%t0 = shufflevector <64 x i8> %v0, <64 x i8> %v1, <64 x i32><i32 2, i32 3, i32 4, i32 5, i32 6, i3…
24 ret <64 x i8> %t0
30 define <64 x i8> @test_03(<64 x i8> %v0, <64 x i8> %v1) #0 {
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/external/clang/test/CodeGen/
Dtarget-data.c3 // I686-UNKNOWN: target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
7 // I686-DARWIN: target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"
11 // I686-WIN32: target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
15 // I686-CYGWIN: target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
19 // X86_64: target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
27 // SPARC-V8: target datalayout = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"
31 // SPARC-V9: target datalayout = "E-m:e-i64:64-n32:64-S128"
35 // MIPS-32EL: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
39 // MIPS-32EB: target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
42 // RUN: FileCheck %s -check-prefix=MIPS-64EL
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