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/external/deqp-deps/glslang/Test/baseResults/
Dspv.accessChain.frag.out12 Name 4 "main"
13 Name 8 "S"
15 Name 11 "GetColor1(struct-S-vf31;"
16 Name 10 "i"
17 Name 18 "GetColor2(struct-S-vf31;i1;"
18 Name 16 "i"
19 Name 17 "comp"
20 Name 22 "GetColor3(struct-S-vf31;i1;"
21 Name 20 "i"
22 Name 21 "comp"
[all …]
Dspv.separate.frag.out17 Name 4 "main"
18 Name 6 "foo("
19 Name 11 "color"
20 Name 14 "t2d"
21 Name 18 "s"
22 Name 31 "t3d"
23 Name 34 "i"
24 Name 41 "sA"
25 Name 58 "tex2D"
26 Name 64 "texCube"
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Dspv.image.load-formatted.frag.out1 spv.image.load-formatted.frag
2 Warning, version 450 is not yet complete; most version-specific features are present, but some are …
23 Name 4 "main"
24 Name 9 "iv"
25 Name 15 "i1D"
26 Name 27 "i2D"
27 Name 38 "i3D"
28 Name 45 "iCube"
29 Name 55 "iCubeArray"
30 Name 62 "i2DRect"
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/external/llvm-project/llvm/test/tools/llvm-objcopy/MachO/
Dinstall-name-tool-change.test1 ## This test checks updating a dependent shared library install name in a MachO binary.
3 # RUN: yaml2obj %s -o %t
5 ## Specifying -change once:
7 # RUN: llvm-install-name-tool -change /usr/dylib/LOAD /usr/long/long/dylib/LOAD %t.copy
8 # RUN: llvm-objdump -p %t.copy | FileCheck %s --check-prefix=CHANGE --implicit-check-not='name /usr'
10 # CHANGE: name /usr/long/long/dylib/LOAD
11 # CHANGE: name /usr/dylib/WEAK
13 ## Specifying -change multiple times:
15 # RUN: llvm-install-name-tool -change /usr/dylib/WEAK /usr/sh/WEAK \
16 # RUN: -change /usr/dylib/LOAD /usr/sh/LOAD %t.copy
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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dload_4_unaligned.mir2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCh…
3 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -mcpu=mips32r6 -verify-machineinstrs %…
4 --- |
17 %0 = load float, float* @float_align1, align 1
23 %0 = load float, float* @float_align2, align 2
29 %0 = load float, float* @float_align4, align 4
35 %0 = load float, float* @float_align8, align 8
41 %0 = load i32, i32* @i32_align1, align 1
47 %0 = load i32, i32* @i32_align2, align 2
53 %0 = load i32, i32* @i32_align4, align 4
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-load-atomic-local.mir2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-is…
3 # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-is…
4 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-is…
6 ---
8 name: load_atomic_local_s32_seq_cst
17 ; GFX6-LABEL: name: load_atomic_local_s32_seq_cst
19 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
20 ; GFX6: $m0 = S_MOV_B32 -1
21 …; GFX6: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exe…
23 ; GFX7-LABEL: name: load_atomic_local_s32_seq_cst
[all …]
Dinst-select-load-constant.mir2 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-m…
3 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-m…
4 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-mac…
5 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-…
7 ---
9 name: load_constant_s32_from_4
19 ; GFX6-LABEL: name: load_constant_s32_from_4
21 ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
22 …; GFX6: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (lo…
24 ; GFX7-LABEL: name: load_constant_s32_from_4
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Dinst-select-load-local.mir2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-i…
3 # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-i…
4 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-ise…
5 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-is…
6 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-i…
8 ---
10 name: load_local_s32_from_4
19 ; GFX7-LABEL: name: load_local_s32_from_4
21 ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
22 ; GFX7: $m0 = S_MOV_B32 -1
[all …]
Dregbankselect-load.mir2 … llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=regbanksel…
3 … llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=regbanksel…
5 --- |
9 %tmp2 = load <8 x i32>, <8 x i32> addrspace(1)* %global.not.uniform.v8i32
16 %tmp2 = load <4 x i64>, <4 x i64> addrspace(1)* %global.not.uniform.v4i64
22 %tmp2 = load <16 x i32>, <16 x i32> addrspace(1)* %global.not.uniform.v16i32
28 %tmp2 = load <8 x i64>, <8 x i64> addrspace(1)* %global.not.uniform.v8i64
38 %tmp2 = load <8 x i32>, <8 x i32> addrspace(4)* %constant.not.uniform.v8i32
45 %tmp2 = load i256, i256 addrspace(4)* %constant.not.uniform
52 %tmp2 = load <16 x i16>, <16 x i16> addrspace(4)* %constant.not.uniform
[all …]
Dregbankselect.mir2 # RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=regbankselect %s -verify-ma…
4 --- |
14 %tmp0 = load i32, i32 addrspace(1)* %ptr1
19 %tmp0 = load i32, i32 addrspace(1)* %ptr1, !amdgpu.noclobber !0
24 %tmp0 = load i32, i32 addrspace(1)* %ptr1
29 %tmp0 = load i32, i32 addrspace(1)* %ptr1
34 %tmp0 = load i32, i32 addrspace(1)* %ptr1
41 %tmp2 = load i32, i32 addrspace(1)* %tmp1
56 ---
57 name: load_constant
[all …]
Dinst-select-load-atomic-flat.mir2 # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-is…
3 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-is…
5 ---
7 name: load_atomic_flat_s32_seq_cst
16 ; GFX7-LABEL: name: load_atomic_flat_s32_seq_cst
18 ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
19 …GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, …
21 ; GFX9-LABEL: name: load_atomic_flat_s32_seq_cst
23 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
24 …GFX9: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, …
[all …]
Dinst-select-load-global.s96.mir1 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-m…
2 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=inst…
3 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-mac…
4 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-m…
5 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-…
7 ---
9 name: load_global_v3s32
18 ; GFX7-LABEL: name: load_global_v3s32
20 ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
21 ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
[all …]
Dinst-select-load-local-128.mir2 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-m…
3 …-amdgpu-global-isel-new-legality -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-m…
5 ---
7 name: load_local_v4s32_align16
16 ; GFX7-LABEL: name: load_local_v4s32_align16
18 ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19 ; GFX7: $m0 = S_MOV_B32 -1
20 …; GFX7: [[DS_READ_B128_:%[0-9]+]]:vreg_128 = DS_READ_B128 [[COPY]], 0, 0, implicit $m0, implicit $…
22 ; GFX9-LABEL: name: load_local_v4s32_align16
24 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
[all …]
Dlegalize-sextload-flat.mir2 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check…
3 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -che…
4 ---
5 name: test_sextload_flat_i32_i8
10 ; SI-LABEL: name: test_sextload_flat_i32_i8
11 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
12 ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
14 ; VI-LABEL: name: test_sextload_flat_i32_i8
15 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
16 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dload-wro-addressing-modes.mir2 # RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -…
4 ---
5 name: shl_gep_sext_ldrwrow
18 ; In this case, we should get a roW load with two 1s, representing a shift
21 ; CHECK-LABEL: name: shl_gep_sext_ldrwrow
25 ; CHECK: %load:gpr32 = LDRWroW %base, %foo, 1, 1 :: (load 4)
26 ; CHECK: $w0 = COPY %load
34 %load:gpr(s32) = G_LOAD %ptr(p0) :: (load 4)
35 $w0 = COPY %load(s32)
38 ---
[all …]
Dxro-addressing-mode-constant.mir2 # RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -…
8 ---
9 name: use_xro_cannot_encode_add_lsl
23 ; CHECK-LABEL: name: use_xro_cannot_encode_add_lsl
27 ; CHECK: %load:gpr64 = LDRXroX %copy, %cst, 0, 0 :: (volatile load 8)
32 %load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
36 ---
37 name: use_xro_preferred_mov
52 ; CHECK-LABEL: name: use_xro_preferred_mov
55 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 61440
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dmerge-image-sample.mir1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | F…
3 # GFX9-LABEL: name: image_sample_l_merged_v1v3
4 …X9: %{{[0-9]+}}:vreg_128 = IMAGE_SAMPLE_L_V4_V4 %5, %3, %2, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit …
5 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
6 # GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
8 name: image_sample_l_merged_v1v3
16 …RDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
17 …_128, %3:sgpr_256, %2:sgpr_128, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable loa…
18 …128, %3:sgpr_256, %2:sgpr_128, 14, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable loa…
20 ---
[all …]
Dmerge-image-load-gfx10.mir1 # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | …
3 # GFX10-LABEL: name: image_load_merged_v1v3
4 …: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V2_gfx10 %5, %3, 15, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, implici…
5 # GFX10: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
6 # GFX10: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
8 name: image_load_merged_v1v3
16 …RDX2_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
17 …V1_V2_gfx10 %5:vreg_64, %3:sgpr_256, 1, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (derefere…
18 …3_V2_gfx10 %5:vreg_64, %3:sgpr_256, 14, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (derefere…
20 ---
[all …]
Dmemory-legalizer-local.mir1 # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck -check-pref…
3 ---
5 # GCN-LABEL: name: load_singlethread_unordered
7 # GCN-LABEL: bb.0:
8 # GCN-NOT: S_WAITCNT
10 # GCN-NOT: S_WAITCNT
13 name: load_singlethread_unordered
16 …$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 ad…
17 …D_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspa…
18 $m0 = S_MOV_B32 -1
[all …]
Dmemory-legalizer-region.mir1 # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck -check-pref…
3 ---
5 # GCN-LABEL: name: load_singlethread_unordered
7 # GCN-LABEL: bb.0:
8 # GCN-NOT: S_WAITCNT
10 # GCN-NOT: S_WAITCNT
13 name: load_singlethread_unordered
16 …$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 ad…
17 …D_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspa…
18 $m0 = S_MOV_B32 -1
[all …]
Dfp-atomic-to-s_denormmode.mir1 # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s |…
3 # GCN-LABEL: name: flat_atomic_fcmpswap_to_s_denorm_mode
5 # GCN-NEXT: S_NOP 2
6 # GCN-NEXT: S_DENORM_MODE
7 ---
8 name: flat_atomic_fcmpswap_to_s_denorm_mode
11 …, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_c…
12 S_DENORM_MODE 0, implicit-def $mode, implicit $mode
15 # GCN-LABEL: name: flat_atomic_fcmpswap_x2_to_s_denorm_mode
17 # GCN-NEXT: S_NOP 2
[all …]
Dmerge-image-load.mir1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | F…
3 # GFX9-LABEL: name: image_load_merged_v1v3
4 # GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec…
5 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
6 # GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
8 name: image_load_merged_v1v3
16 …RDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
17 …V1_V4 %5:vreg_128, %3:sgpr_256, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable loa…
18 …3_V4 %5:vreg_128, %3:sgpr_256, 14, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable loa…
20 ---
[all …]
/external/llvm/test/CodeGen/MIR/X86/
Dmemory-operands.mir1 # RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o - %s | FileCheck %s
5 --- |
9 %b = load i32, i32* %a
16 %b = load i32, i32* %"a value"
25 %b = load i32, i32* %0
33 %0 = load volatile i32, i32* %x
49 %v = load i32, i32* %x, !invariant.load !1
57 %v = load <8 x float>, <8 x float>* %vec
65 %v = load <8 x float>, <8 x float>* %vec
91 %a = load i32, i32* @G
[all …]
/external/llvm-project/llvm/test/CodeGen/MIR/X86/
Dmemory-operands.mir1 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
5 --- |
9 %b = load i32, i32* %a
16 %b = load i32, i32* %"a value"
25 %b = load i32, i32* %0
33 %0 = load volatile i32, i32* %x
49 %v = load i32, i32* %x, !invariant.load !1
57 %v = load <8 x float>, <8 x float>* %vec
65 %v = load <8 x float>, <8 x float>* %vec
91 %a = load i32, i32* @G
[all …]
/external/starlark-go/starlark/
Dexample_test.go2 // Use of this source code is governed by a BSD-style
36 if err := starlark.UnpackArgs(b.Name(), args, kwargs, "s", &s, "n?", &n); err != nil {
42 // The Thread defines the behavior of the built-in 'print' function.
44 Name: "example",
48 // This dictionary defines the pre-declared environment.
65 for _, name := range globals.Keys() {
66 v := globals[name]
67 fmt.Printf("%s (%s) = %s\n", name, v.Type(), v.String())
80 // implementation of 'load' that works sequentially.
83 "c.star": `load("b.star", "b"); c = b + "!"`,
[all …]

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