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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsplitkit-copy-live-lanes.mir21 ; CHECK: %2.sub1:sgpr_128 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
23 ; CHECK: %3.sub1:sgpr_128 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
32 …; CHECK: undef %47.sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET]].sub1, impl…
40 …; CHECK: undef %67.sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET1]].sub1, imp…
47 …; CHECK: undef %86.sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET2]].sub1, imp…
54 …; CHECK: undef %105.sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET3]].sub1, im…
60 …; CHECK: undef %122.sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET4]].sub1, im…
67 …; CHECK: undef %140.sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub1, im…
74 …; CHECK: undef %158.sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET6]].sub1, im…
79 …; CHECK: undef %40.sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET7]].sub1, imp…
[all …]
Drename-independent-subregs.mir9 # can be moved to a new virtual register. The third def of sub1 however is used
13 # CHECK: S_NOP 0, implicit-def undef %2.sub1
14 # CHECK: S_NOP 0, implicit %2.sub1
15 # CHECK: S_NOP 0, implicit-def undef %1.sub1
16 # CHECK: S_NOP 0, implicit %1.sub1
17 # CHECK: S_NOP 0, implicit-def %0.sub1
25 S_NOP 0, implicit-def %0.sub1
26 S_NOP 0, implicit %0.sub1
27 S_NOP 0, implicit-def %0.sub1
28 S_NOP 0, implicit %0.sub1
[all …]
Dregcoalesce-cannot-join-failures.mir14 ; CHECK: %0.sub1:sreg_64_xexec = COPY %0.sub0
27 %0.sub1:sreg_64_xexec = COPY %0.sub0:sreg_64_xexec
42 ; CHECK: %0.sub1:sreg_64 = COPY %0.sub0
43 ; CHECK: S_ENDPGM 0, implicit %0.sub1
46 %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
47 S_ENDPGM 0, implicit %1.sub1:sreg_64
57 ; CHECK: undef %0.sub1:sreg_64 = S_MOV_B32 -1
61 ; CHECK: dead %0.sub1:sreg_64 = COPY %0.sub0
62 ; CHECK: S_ENDPGM 0, implicit [[COPY]].sub1
65 undef %0.sub1:sreg_64 = S_MOV_B32 -1
[all …]
Ddetect-dead-lanes.mir9 # CHECK: %3:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3
11 # CHECK: S_NOP 0, implicit %3.sub1
16 # CHECK: S_NOP 0, implicit %4.sub1
31 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
33 S_NOP 0, implicit %3.sub1
38 S_NOP 0, implicit %4.sub1
49 # CHECK: S_NOP 0, implicit undef %1.sub1
53 # CHECK: S_NOP 0, implicit undef %2.sub1
58 # CHECK: S_NOP 0, implicit undef %4.sub1
64 # CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub1
[all …]
Dpromote-constOffset-to-imm.mir21 %9:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, %8, %subreg.sub1
24 %12:sgpr_32 = COPY %1.sub1
29 %19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
32 … %23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec
36 %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
41 %37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1
50 …REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BASE_LO]], %subreg.sub0, [[BASE_HI]], %subreg.sub1
56 …G_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BASE1_LO]], %subreg.sub0, [[BASE1_HI]], %subreg.sub1
74 %9:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, %8, %subreg.sub1
77 %12:sgpr_32 = COPY %1.sub1
[all …]
Dpromote-constOffset-to-imm-gfx10.mir21 %9:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, %8, %subreg.sub1
24 %12:sgpr_32 = COPY %1.sub1
29 %19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
32 …%23:vgpr_32, dead %24:sreg_32_xm0_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $e…
36 %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
41 %37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1
50 …REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BASE_LO]], %subreg.sub0, [[BASE_HI]], %subreg.sub1
57 …G_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BASE1_LO]], %subreg.sub0, [[BASE1_HI]], %subreg.sub1
74 %9:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, %8, %subreg.sub1
77 %12:sgpr_32 = COPY %1.sub1
[all …]
Ddpp_combine.mir481 # GCN: %7:vgpr_32 = V_MUL_I32_I24_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
493 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
494 %5:vreg_64 = INSERT_SUBREG %4, %1, %subreg.sub1 ; %5.sub0 is taken from %4
496 %7:vgpr_32 = V_MUL_I32_I24_e32 %6, %0.sub1, implicit $exec
500 # GCN: %5:vgpr_32 = V_ADD_U32_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
511 %3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted
512 %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec
513 %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
517 # GCN: %5:vgpr_32 = V_ADD_U32_dpp undef %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec
528 %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef
[all …]
Dregcoalesce-keep-valid-lanes-implicit-def-bug39602.mir14 ; CHECK: undef %0.sub1:sreg_64 = IMPLICIT_DEF
18 ; CHECK: dead %0.sub1:sreg_64 = COPY %0.sub0
19 ; CHECK: S_ENDPGM 0, implicit [[COPY]].sub1
22 undef %0.sub1:sreg_64 = IMPLICIT_DEF
27 dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
28 S_ENDPGM 0, implicit %1.sub1:sreg_64
41 ; CHECK: undef %0.sub1:sreg_64 = S_MOV_B32 -1
45 ; CHECK: dead %0.sub1:sreg_64 = COPY %0.sub0
46 ; CHECK: S_ENDPGM 0, implicit [[COPY]].sub1
49 undef %0.sub1:sreg_64 = S_MOV_B32 -1
[all …]
Dsdwa-ops.mir30 …%64:vgpr_32, dead %66:sreg_64_xexec = nuw V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $ex…
31 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
36 …%164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
37 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
42 …%174:vgpr_32, dead %176:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %175, 0, implicit $exec
43 %172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1
75 …%164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
76 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
78 %64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
79 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
[all …]
Dspill-empty-live-interval.mir10 # CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $mode, …
12 # CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
13 # CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $mode, implicit $exec
15 # CHECK: S_NOP 0, implicit %6.sub1
17 # CHECK-NEXT: S_NOP 0, implicit %8.sub1
29 …undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $mode, implicit…
30 undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
31 dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $mode, implicit $exec
34 S_NOP 0, implicit %2.sub1
35 S_NOP 0, implicit %0.sub1
Drename-independent-subregs-mac-operands.mir58 %13.sub1 = COPY %8
66 %14 = COPY %1.sub1
69 %15.sub1 = COPY killed %14
80 # GCN: undef %8.sub1:vreg_128 = nofpexcept V_MAC_F32_e32 undef %2:vgpr_32, undef %1:vgpr_32, undef …
86 # GCN: %8.sub1:vreg_128 = nofpexcept V_ADD_F32_e32 %8.sub1, %8.sub1, implicit $mode, implicit $exec
90 # GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0,
120 …undef %6.sub1 = nofpexcept V_MAC_F32_e32 undef %2, undef %1, undef %6.sub1, implicit $mode, implic…
131 %6.sub1 = nofpexcept V_ADD_F32_e32 %6.sub1, %6.sub1, implicit $mode, implicit $exec
137 …BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, 0, 0, implicit…
147 # GCN-NEXT: dead undef %3.sub1:vreg_128 = COPY %2.sub0
[all …]
Dmubuf-legalize-operands.mir16 # W64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.su…
21 # W64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
22 # W64: [[STMP0:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1
26 # W64: [[STMP1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[SRSRC2]], %subreg.sub0, [[SRSRC3]], %subreg.sub1
29 # W64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1…
40 # W32: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.su…
45 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
46 # W32: [[STMP0:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1
50 # W32: [[STMP1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[SRSRC2]], %subreg.sub0, [[SRSRC3]], %subreg.sub1
53 # W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1…
[all …]
Dsubreg-undef-def-with-other-subreg-defs.mir8 # current vreg uses because it shared no lanes with %0.sub1 use on the
23 ; CHECK: %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
30 … 851978 /* regdef:VGPR_LO16 */, def undef %0.sub0, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub1
31 ; CHECK: S_NOP 0, implicit %0.sub1
36 %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
43 INLINEASM &"", 1, 851978, def undef %0.sub0, 851978, def %0.sub1
44 S_NOP 0, implicit %0.sub1
61 ; CHECK: %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
68 … /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub1, 851978 /* regdef:V…
69 ; CHECK: S_NOP 0, implicit %0.sub1
[all …]
/external/llvm-project/compiler-rt/test/fuzzer/
Dfuzzer-dirs.test3 RUN: rm -rf %t/SUB1
4 RUN: mkdir -p %t/SUB1/SUB2/SUB3
5 RUN: echo a > %t/SUB1/a
6 RUN: echo b > %t/SUB1/SUB2/b
7 RUN: echo c > %t/SUB1/SUB2/SUB3/c
8 RUN: %run %t-SimpleTest %t/SUB1 -runs=0 2>&1 | FileCheck %s --check-prefix=SUBDIRS
10 RUN: echo -n zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz > %t/SUB1/f64
11 RUN: cat %t/SUB1/f64 %t/SUB1/f64 %t/SUB1/f64 %t/SUB1/f64 > %t/SUB1/f256
12 RUN: cat %t/SUB1/f256 %t/SUB1/f256 %t/SUB1/f256 %t/SUB1/f256 > %t/SUB1/f1024
13 RUN: cat %t/SUB1/f1024 %t/SUB1/f1024 %t/SUB1/f1024 %t/SUB1/f1024 > %t/SUB1/f4096
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dusub-overflow-known-by-implied-cond.ll22 %sub1 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
23 %r1 = extractvalue { i32, i1 } %sub1, 0
24 %c1 = extractvalue { i32, i1 } %sub1, 1
41 ; CHECK-NEXT: [[SUB1:%.*]] = sub nuw i32 [[A]], [[B]]
42 ; CHECK-NEXT: ret i32 [[SUB1]]
50 %sub1 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
51 %r1 = extractvalue { i32, i1 } %sub1, 0
52 %c1 = extractvalue { i32, i1 } %sub1, 1
78 %sub1 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
79 %r1 = extractvalue { i32, i1 } %sub1, 0
[all …]
Dselect-ctlz-to-cttz.ll26 %sub1 = xor i32 %lz, 31
27 %cond = select i1 %tobool, i32 %lz, i32 %sub1
40 %sub1 = xor i32 %lz, 31
41 %cond = select i1 %tobool, i32 %lz, i32 %sub1
54 %sub1 = xor <2 x i32> %lz, <i32 31, i32 31>
55 %cond = select <2 x i1> %tobool, <2 x i32> %lz, <2 x i32> %sub1
64 ; CHECK-NEXT: [[SUB1:%.*]] = xor i32 [[LZ]], 31
65 ; CHECK-NEXT: call void @use(i32 [[SUB1]])
73 %sub1 = xor i32 %lz, 31
74 call void @use(i32 %sub1)
[all …]
/external/tensorflow/tensorflow/python/kernel_tests/distributions/
Dkullback_leibler_test.py101 class Sub1(normal.Normal): class
111 class Sub11(Sub1):
117 @kullback_leibler.RegisterKL(Sub1, Sub1)
119 return "sub1-1"
121 @kullback_leibler.RegisterKL(Sub1, Sub2)
123 return "sub1-2"
125 @kullback_leibler.RegisterKL(Sub2, Sub1)
131 sub1 = Sub1(loc=0.0, scale=1.0)
135 self.assertEqual("sub1-1", fn(sub1, sub1))
136 self.assertEqual("sub1-2", fn(sub1, sub2))
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Drename-independent-subregs.mir7 # can be moved to a new virtual register. The third def of sub1 however is used
11 # CHECK: S_NOP 0, implicit-def undef %2:sub1
12 # CHECK: S_NOP 0, implicit %2:sub1
13 # CHECK: S_NOP 0, implicit-def undef %1:sub1
14 # CHECK: S_NOP 0, implicit %1:sub1
15 # CHECK: S_NOP 0, implicit-def %0:sub1
24 S_NOP 0, implicit-def %0:sub1
25 S_NOP 0, implicit %0:sub1
26 S_NOP 0, implicit-def %0:sub1
27 S_NOP 0, implicit %0:sub1
[all …]
Ddetect-dead-lanes.mir21 # CHECK: S_NOP 0, implicit %3:sub1
26 # CHECK: S_NOP 0, implicit %4:sub1
42 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
44 S_NOP 0, implicit %3:sub1
49 S_NOP 0, implicit %4:sub1
60 # CHECK: S_NOP 0, implicit undef %1:sub1
64 # CHECK: S_NOP 0, implicit undef %2:sub1
69 # CHECK: S_NOP 0, implicit undef %4:sub1
106 S_NOP 0, implicit %1:sub1
110 S_NOP 0, implicit %2:sub1
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dregbankselect-reg-sequence.mir18 …QUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
21 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
35 …CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1
36 %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1
52 …QUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
55 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
69 …CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
70 %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
86 …QUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
89 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
[all …]
Dinst-select-ptr-add.mir21 ; GFX6: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
22 ; GFX6: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
25 …:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
32 ; GFX8: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
33 ; GFX8: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
36 …:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
43 ; GFX9: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
44 ; GFX9: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
47 …:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
54 ; GFX10-WAVE64: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
[all …]
Dinst-select-atomicrmw-add-flat.mir86 …[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
89 ; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
90 ; GFX7: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
93 …G_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %10, %subreg.sub1
108 …[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
111 ; GFX10: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
112 ; GFX10: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
115 …G_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %10, %subreg.sub1
142 …[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
145 ; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
[all …]
Dinst-select-load-flat.mir723 …[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
726 ; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
727 ; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
730 …EG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %9, %subreg.sub1
738 …[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
741 ; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
742 ; GFX8: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
745 …EG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %9, %subreg.sub1
758 …[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
761 ; GFX10: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
[all …]
/external/perfetto/src/protozero/test/
Dcppgen_conformance_unittest.cc163 auto* sub1 = i == 0 ? msg_v2.mutable_sub1() : msg_v2.add_sub1_rep(); in TEST() local
164 sub1->set_sub1_int(12); in TEST()
165 sub1->set_sub1_string("sub1-string"); in TEST()
166 sub1->set_sub1_int_v2(13); in TEST()
167 sub1->set_sub1_string_v2("sub1-string-v2"); in TEST()
176 lazy.set_sub1_string("sub1-lazy-string"); in TEST()
178 lazy.set_sub1_string_v2("sub1-lazy-string-v2"); in TEST()
212 auto* sub1 = i == 0 ? &msg_v1.sub1() : &msg_v1.sub1_rep()[i - 1]; in TEST() local
213 EXPECT_EQ(sub1->sub1_int(), 12); in TEST()
214 EXPECT_EQ(sub1->sub1_string(), "sub1-string"); in TEST()
[all …]
/external/snakeyaml/src/test/java/org/yaml/snakeyaml/ruby/
DTestObject.java19 private Sub1 sub1; field in TestObject
22 public Sub1 getSub1() { in getSub1()
23 return sub1; in getSub1()
26 public void setSub1(Sub1 sub1) { in setSub1() argument
27 this.sub1 = sub1; in setSub1()

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